When entering numeric values in the answer fields, you can use integers (1000), floating-point numbers (1000.0), scientific notation (1e3), or JSim numeric scale factors (1K).

Problem 1. The following questions are multiple-choice. Using the "check" button, you can of course simply keep guessing until you get the right answer. But you'll be in a much better position to take the quizzes if you take the time to actually figure out the answers.

1. If we set the inputs of a particular CMOS gate to voltages that correspond to valid logic levels, we would expect the static power dissipation of the gate to be

   --select answer--0non-zero, but very small (picowatts)depends on whether output voltage is low or highunknown with the facts given

2. Measuring a particular CMOS device G, we find 1.5V noise margins. If the width of all mosfets inside of G were doubled, we would expect the noise margins of the new gate to

   --select answer--stay about the sameincrease noticeablydecrease noticeablychange noticeably, but can't tell which way

3. To decrease the output rise time of a CMOS gate one could

   --select answer--increase the length of all pfetsincrease the width of all pfetsincrease the length of all nfetsincrease the width of all nfetsnone of the above

4. Suppose one wanted to decrease the propagation time of a CMOS circuit. Which of the following actions would lead to the greatest possible speed up?

   --select answer--decrease the power supply voltage and lower the operating temperaturedecrease the power supply voltage and raise the operating temperatureincrease the power supply voltage and lower the operating temperatureincrease the power supply voltage and raise the operating temperature

Problem 2. Almost all of the power dissipated by CMOS circuits goes into charging and discharging nodal capacitances. This power can be computed as C(V²)F where C is the capacitance being switched, V is the change in voltage, and F is the frequency at which the switching happens. In CMOS circuits, nodes are switched between ground (0 volts) and the power supply voltage (VDD volts), so V is either +VDD or -VDD and so V² is VDD².

1. Suppose we have a device implemented in a technology where VDD = 5V. If we have the option of reimplementing the device in a technology where VDD = 3.3V, what sort of speedup (i.e., change in F) could be specified for the reimplementation assuming we want to keep the power budget unchanged?

   Speedup (eg, 2.0 would be twice as fast):

Problem 3. As we saw in Lecture 4, there are 16 possible 2-input combinational logic gates. The cost of implementing these gates varies dramatically, requiring somewhere between 0 and 10 mosfets depending on the gate. For example, it takes 2 mosfets to implement "F = NOT A", but 4 mosfets (organized as two inverters) to implement "F = A".

For each of the 2-input gates whose Karnaugh maps are given below, indicate the minimum number of mosfets required to implement the gate. You should only consider static fully-complementary circuits like those shown in lecture; these implementations meet the following criteria:

• no static power dissipation
• Vol = 0V, Voh = power supply voltage
• Nfets appear only in pulldown paths, Pfets appear only in pullup paths
• the pullup and pulldown are complementary, i.e., when one path is "on", the other is "off"
• the pullup and pulldown circuits can be decomposed into series and parallel connections of mosfets
• all gate implementations restore incoming logic levels (so a wire connecting an input terminal to an output terminal would not be a legal gate implementation)

1. 
   

   NOR		A
   		0	1
   B	0	1	0
   	1	0	0

   Number of mosfets needed to implement "NOR" :

2. 
   

   AND		A
   		0	1
   B	0	0	0
   	1	0	1

   Number of mosfets needed to implement "AND" :

3. 
   

   XNOR		A
   		0	1
   B	0	1	0
   	1	0	1

   Number of mosfets needed to implement "XNOR" :

4. 
   

   NOT B		A
   		0	1
   B	0	1	1
   	1	0	0

   Number of mosfets needed to implement "NOT B" :

5. 
   

   A > B		A
   		0	1
   B	0	0	1
   	1	0	0

   Number of mosfets needed to implement "A > B" :