| Simple program to test cache configurations.

.include beta.uasm

. = 0				| Reset vector at 0
	BR(Start)

Start:	LD(firstadr,r1)
	LD(lastadr,r2)
	LD(increment,r3)

| 4-instruction loop, starting at location 16 = 4*4:
| Note that there are 4 words of instruction fetch
|   per loop, and a single data memory read.

loop:	LD(r1, 0, r0)		| r0 <- <r1>
	ADD(r3, r1, r1)		| r1 <- <r1> + increment
	CMPLT(r1, r2, r0)	| if (<r1> < <r2>)
	BT(r0, loop)		|  then goto loop

	HALT()
	BR(Start)

firstadr: LONG(epgm)		| 1st adr after pgm
lastadr:  LONG(0x10000)		| end of DRAM+1
increment:LONG(16)		| The "stride"

epgm = .
. = 0x10000