When entering numeric values in the answer fields, you can use integers (1000), floating-point numbers (1000.0), scientific notation (1e3), or JSim numeric scale factors (1K).

Problem 1. A possible implementation of a finite state with two inputs and one output is shown below.

1. If the register is 5 bits wide (i.e., k = 5) what is the appropriate size of the ROM? Give the number of locations and the number of bits in each location.

B. 

2. If the register is 5 bits wide what is the maximum number of states in an FSM implemented using this circuit?

3. What is the smallest possible value for the ROM's contamination delay that still ensures the necessary timing specifications are met?

4. Assume that the ROM's t_CD = 3ns. What is the shortest possible clock period that still ensures that the necessary timing specifications are met?

Problem 2. Shown below is a state transition diagram for an FSM, F, with a single binary input B. The FSM has a single output, a light which is on for the three states marked by a gray dot. The starting state is marked by the heavy circle.

1. Is there a synchronizing sequence of inputs which will return this FSM from an unknown state to its starting state?

2. Does this FSM have a pair of equivalent states that may be merged to yield a 3-state FSM?

3. The following circuit is used to implement the above 4-state FSM:

It is known that the starting state of the 4-state FSM corresponds to 00 on the state variable input, and the light output is 1 when the light is to be on. What is the value of the light output when all three inputs to the ROM are zero?

4. Fill in the unspecified rows of the following truth table so that it implements the state transition diagram. You will need to enter some combination of three zeros or ones in each field. Other characters in the fields (e.g., spaces) will be ignored. Remember the starting state is 00.

S1 S0  B

S1' S0' light

 0  0  0

 0  0  1

 0  1  0

 1   1   1

 0  1  1

 0   0   1

 1  0  0

 1  0  1

 1  1  0

 1  1  1