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When entering numeric values in the answer fields, you can
use integers (1000), floating-point numbers (1000.0),
scientific notation (1e3), or JSim numeric scale factors (1K).
Problem 1.
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Report the mosfet Ids you measured from the device curves
for Vgs = 5V and Vds = 1.2V.
Compute the effective channel sheet resistance using (Vds)/(Ids)
as an estimate for the channel resistance of the test mosfet.
Don't forget to correct for the W/L of the test device!
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Report the mosfet Ids you measured from the device curves
for Vgs = 0V and Vds = 2.5V.
Calculate the time it would take to discharge 0.05pF capacitor
from 5V to 2.5V
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Determine a scaled width (SW) for the two pullup mosfets
so that the Vin and Vout curves for the NAND gate intersect
at VDD/2 (1.65V).
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What is the largest noise immunity we could specify and still
have the NAND gate qualify as a legal device? Please
fill in your answer with a precision of .01 volts.
Hint: to measure the low noise margin, use the VTC to determine
what Vin has to be in order for Vout to be 3V, then subtract
Vol (0.3V) from that number. To measure the high noise margin,
use the VTC to determine what Vin has to be in order for Vout to
be 0.3V, then subtract that number from Voh (3.0V).
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Following standard practice, choose the logic thresholds
as follows:
Vol = 10% of power supply voltage = 0.3V
Vil = 20% of power supply voltage = 0.6V
Vih = 80% of power supply voltage = 2.6V
Voh = 90% of power supply voltage = 3.0V
Measure the contamination and propagation times for
your NAND gate using both the falling and rising output
transitions.
Use these measurements compute estimates for
an upper bound for tC and a lower
bound for tP.
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Recompute your bounds for tC and tP
this including the measurements you made at 0 degrees C and 100 degrees C.
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Compute derating factors for worst case and best case conditions.
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Compute extrinsic delay for falling and rising output transition.
Remember to convert the answer to the correct units!
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