| R1 |
Diagnostic Review: First Order Differential Equations; One-dimensional Electrostatics; Linear Equivalent Circuits and Linear Circuit Analysis. |
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| L1 |
Introduction. Intrinsic Semiconductors, Bond Structure, Holes and Electrons; ni(T). Dopants - Donors and Acceptors. no and po in Extrinsic (Doped). Sic: Thermal Equilibrium, Detailed Balance, nopo Product; no, po Given NA, ND. |
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| R2 |
Calculations of no, po in Variously Doped Examples to Review "no, po given NA, ND" from lecture. Drift, Basic Concepts: Net Velocity vs. Field, Mobility; Conductivity, Resistivity. Concept of n-type and p-type. |
PS #1 Out |
| T1 |
Review of Electrostatics (8.02) and Poisson's Equation; ρ, Ε, Φ; Parallel Plate Capacitors. Doping and Carrier Type Issues as Needed. |
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| T1/L2 |
Review of Electrostatics (8.02) and Poisson's Equation; ρ, Ε, Φ; Parallel Plate Capacitors. Doping and Carrier Type Issues as Needed (contd.)
Uniform Excitations: Uniform Electric Field and Drift (Review from Rec. 2). Uniform Optical Injection. Low Level Injection. Minority Carrier Lifetimes. Homogeneous Solution. |
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| R3 |
Typical Values of Mobility, Conductivity, Resistivity. Comparison with Metals, Insulators. Population Transients. Responses to Various Common Waveforms. Analogy with RC Circuits. |
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| L3 |
Non-uniform Injection and/or Doping. Diffusion. Continuity/Conservation. The Five Basic Equations. |
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| R4 |
Complete Discussion of Optical Injection. Diffusion Video. Haynes-Shockley Video. |
PS #1 Due
PS #2 Out |
| T2 |
Population Transient Problems. Identification of Simple Situations as Special Cases of the Five Basic Equations. |
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| L4 |
Linearization and Decoupling of 5 Basic Equations in Flow Problem Regime: Quasineutrality, Debye Length, LDx, and Dielectric Relaxation Time, τD; Minority Carrier Flow by Diffusion. Diffusion Equation(s) for n': General Solutions; Boundary Conditions; Procedure to find n, p, Je, Jh, Ex having n'. |
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| R5 |
Boundary Conditions for Flow Problems: Ohmic Contacts, Reflecting Surfaces, Continuity at Internal Boundaries. Example of Injection in middle of a Bar; Short-base and Long-base Limits. |
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| L5 |
Non-uniformly Doped Material in Thermal Equilibrium. Electrostatic Potential (Using Einstein Relation); Poisson equation. no(x), po(x), Φ(x) when Doping Varies Slowly; Quasi-neutral Approximation; Extrinsic Debye Length, LDx. Begin Abrupt p-n Junction. |
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| R6 |
Review Concepts in L5. Typical values of Φn, Φp; Emphasize Weak Dependence on no, po; 60 mV/decade Rule. Look no, po, and Φ's in Vicinity of an Abrupt p-n Junction. More (Final) Discussion and Solutions of Flow Problems as needed. |
PS #2 Due
PS #3 Out |
| T3 |
More (Final) Discussion of Flow Problems, Boundary Conditions, and Solutions. Long Diffusion Length (Infinite Lifetime) approximation; Integral Solutions, Nature of Profiles. Electrostatic Potential of Various Metals and Semiconductors, and Consideration of Φ(x) around a Circuit and through Contacts in T.E. |
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| L6 |
Abrupt p-n Junction in Thermal Equilibrium; the Depletion Approximation. Expressions for W, xn, xp, Epk, Φb. Extension of Model to Biased Junctions: Argue can Replace Φb by (Φb - vA) if Charge Due to Currents Can be Neglected and All vA Appears across Junction. |
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| R7 |
Review Depletion Approximation Model for Junction and the Effect of Bias; Comment on Φ(x) around a circuit through Contacts. Charge Store associated with SCL and Depletion Capacitance. |
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| L7 |
Forward Biased Abrupt p-n Junction. Carrier Equilibrium with/across Space Charge Layer; Current Flow. Derivation of I-V Expression. Plots of Carrier Populatioins through Forward and Reverse Biased Short Base p-n Diodes (Empahisize Injection is into Lightly Doped Side). |
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| R8 |
Charge Storage Associated with Minority Carrier Injection; Diffusion Capacitance. |
PS #3 Due
PS #4 Out |
| T4 |
Examples of Graded Junction Profiles as a way of Reinforcing Understanding of the Depletion Approximation and the Electrosatics of p-n Junctions. |
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| T4/L8 |
Examples of Graded Junction Profiles as a way of Reinforcing Understanding of the Depletion Approximation and the Electrosatics of p-n Junctions (contd.)
Review Diodes Current, and QN Region Excess Charge Stores and Diffusion Capacitance; Introduce BJT Structure, and Bipolar Junction Transistor (BJT) Operating Principles; Derive Currents for npn BJT in Forward Active Region; Introduce Base and Emitter Defects. |
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| R9 |
Review of BJT Issues, Focusing on Reverse Biased CB Diode and Impact of Carrier Injection toward it. Schematic Symbols for BJTs and Example Inverter/Amplifier Circuits; Compare to MOSFET from 6.002; Discuss two Viewpoints: Base-emitter Voltage and Base Current as Controlling Collector Current. |
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| L9 |
Superposition, Ebers-Moll Model for npn. Expressions for α and β. Large Signal BJT Characteristics and Models: Regions of Operation; Approximate Model Valid in Forward Active Region. β-model. Discussion of Limitations of Model and Extremes of Operation; Non-ideal Elements. |
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| R10 |
Complete Discussion of Large Signal BJT Models. Use Large Signal BJT Model to Calculate Transfer Characteristic of Common Emitter Amplifier. |
PS #4 Due
PS #5 Out |
| T5 |
Plots of Carrier Populations and Current Densities Through BJTs in Various Operating Regions Review of Material to Date in Preparation for First Exam. |
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| T5/L10 |
Plots of Carrier Populations and Current Densities Through BJTs in Various Operating Regions Review of Material to Date in Preparation for First Exam (contd.)
Other Junction Devices (a Disguised Quiz Review): LEDs, Illuminated p-n Diodes; Superposition Solar Cells and Photodiodes. |
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No Formal Recitation Sessions. Instructors will be available to answer questions and Review Issues for the Quiz. |
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| Q1 |
Closed Book. Covering Material through R8 and PS #4 (i.e., through p-n Diodes). |
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| L11 |
MOS Structures. Discussion of Accumulation, Depletion, Inversion. Application of Depletion Approximation to MOS Capacitor to Relate Channel Charges to Gate Voltage. Flat Band Voltage; Threshold Voltage. |
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| R11 |
Review Accumulation, Depletion, and Inversion in MOS, and Model Relating Channel Charge to Gate Voltage in Excess of Threshold. C-V Relationship for MOS Structure. |
PS #5 Due
PS #6 Out |
| T6 |
Discussion of MOS Structure and MOS Capacitor Issues. |
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| L12 |
Gradual Channel Approximation for MOSFET i-v Characteristics; Quadratic Approx. Discussion of Pinch-off. Regions of Operation. |
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| R12 |
Review of Gradual Channel Model. Features of Characteristics. Possible MOSFET Device Types: n- and p-channel, Enhancement and Depletion Mode. |
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| L13 |
Summary of Static Large Signal BJT and MOSFET Models. Enhancements: Base Width/Channel Length Modulation (Early Effects); Charge Stores (diffusion and Depletion Stores in BJTs and MOSFETs). |
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| R13 |
Complete Discussion of MOSFET Modeling. Use of Large Signal Model to Calculate Transfer Characteristics of Common-source Inverter with Resistor Pull-up. |
PS #6 Due
PS #7 Out |
| T7 |
MOSFET Models, Large and Small Signal, for n- and p Channel Devices, Enhancement and Depletion Mode. |
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| T7/L14 |
MOSFET Models, Large and Small Signal, for n- and p Channel Devices, Enhancement and Depletion Mode (contd.)
Incremental Models for BJT (Hybrid-π) and MOSFET. npn vs. pnp; n-channel vs. p-channel; go, Early Voltage; Capacitances. Importance of Stable Bias Point. |
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| R14 |
Review Incremental Models, Including Diodes. Establishing a Stable Bias Point Using Current Sources in Source/Emitter Circuit. Current Source Design. |
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| L15 |
Basic Inverters as Building Blocks for Digital Logic, Memory; Performance Critieria. Begin MOS Logic; Inverter Options; Why CMOS. |
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| R15 |
Discuss Calculation of MOSFET Inverter Transfer Characteristics; Working of Specific Examples (Saturated n-MOS Pull-up, CMOS) |
PS #7 Due
PS #8 Out |
| T8 |
HSPICE for p-n Diodes, BJTs, and MOSFETs. (HSPICE Sessions in Electronic Classroom.) |
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| T8/L16 |
HSPICE for p-n Diodes, BJTs, and MOSFETs. (HSPICE Sessions in Electronic Classroom) (contd.)
CMOS in All its Glory: Comparison of Various Loads in Logic Context - Logic Swing, Speed, Power, Manufacturablity. Memory Cells. |
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| R16 |
Final CMOS Comments. Begin Linear Amplifiers by Doing Analysis of Simple Resistor-loaded Common-emitter Amplifier and Discussing: Using the Large Signal Model to Determine Bias Point, Evaluating the Parameters in the Incremental Model, and Calculating Mid-band Gain |
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| L17 |
Begin Transistor Amplifiers; Common-source as Example. Performance Metrics: Voltage, Current, and Power Gains; Input and Output Resistances. Concept of Mid-band Frequency Range. |
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| R17 |
Common-source and Common-emitter Amplifiers with Current Source Loads. |
PS #8 Due
PS #9 Out |
| T9 |
Review in Preparation for Second Exam. |
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| T9/L18 |
Review in Preparation for Second Exam (contd.)
Basic Single Transistor Amplifier Stages. Common-base/-Gate and Emitter-/Source-Follower Amplifier Stages. Degenerate-Emitter/-Source Stages; Analysis and Features. Two-port Models. |
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No formal Recitation Sessions. Instructors will be available to answer Questions and Review Issues for the Quiz. |
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| Q2 |
Closed Book. Covering Material through R16 and PS #8. |
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| L19 |
Differential Amplifiers: Large Signal Analysis and Transfer Characteristics; Incremental Analysis and Half-circuit Analysis Techniques. |
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| R18 |
Discuss Differential Amplifier Issues: Biasing and Current Source Circuits; Examples of Small Signal Analysis Using Half-circuit Techniques and Importance of Knowing Single Transistor Stages. |
Design Problem Out |
| R19 |
Overview of Design Problem Circuit. Understanding the Performance Specifications. General Approach to Analysis. |
PS #9 Due |
| L20 |
Complete General Differential Amplifiers. Current-source Biasing Circuits. Achieving Maximum Gain while Staying in Forward Active Region: Resistor Loads, Non-linear Loads. |
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| R20 |
More Discussion of Differential Amplifier Issues Relevant to, and in the Context of, the Design Problem. |
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| T10 |
Design Problem Discussion. |
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| L21 |
Active Loads: Lee Load; Current Mirror Loads; Double- to Single-ended Output Conversion. Multi-stage Amplifiers; Issues of Bias, Loading, Stage Choice. Applications and Advantages of CMOS. |
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| R21 |
Continued Consideration of Multi-stage Differential Amplifiers. Calculation of Input and Output Resistances. Determination of Common- and Difference-mode Voltage Swings. |
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| L22 |
Bounding Mid-band; Methods of Open- and of Short-circuit Time Constants in High Frequency Analysis of Multi-stage Amplifiers. High Frequency Gain of Common-emitter/-Source Stage; Miller Capacitance. |
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| R22 |
General Miller Capacitance Phenomenon. Lack of Miller Capacitance in Common-gate/-Base and Followers. Final Design Problem Comments. |
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| T11 |
Discussion of Design Problem Issues. |
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| T11/L23 |
Discussion of Design Problem Issues (contd.)
A Look at the a Commercial Op-amp Design (741?); Use to Discuss Some Special Stages (Darlington, Cascode, Push-Pull, etc.) Use of Capacitor to Stabilize Circuit. Expand upon Cascode as Important Multi-transistor Stage: Large Output Resistance, Excellent High Frequency Performance. |
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| R23 |
IC Fabrication Technology; Berkeley CMOS Fabrication Video. |
Design Problem Due
PS #10 Out |
| L24 |
Intrinsic Limits to High Frequency Performance of MOSFETs and BJTs: wα, wβ, wt. Limits of Quasi-static Approx.
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| R24 |
High Frequency Analysis. Method Of Open-circuit Time Constants; OCTC Example. |
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| L25 |
CMOS Gate Delay and Power Estimates; Relation to Device Dimensions. Scaling Rules. Example of Scaling: 386/486/Pentium. |
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| R25 |
Complete Discussion of Scaling. Driving Signals Off-chip; Digital Buffer Ideas, Issues, and Design. |
PS #10 Due |
| T12 |
Discussion of Design Problem Solution, and Consideration of the High Frequency Performance of the Circuit. |
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| L26 |
Overview of the IC Industry, Analog and Digital. Review of Course and Suggestions for Follow-on Subjects. |
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| R26 |
Course Review and Wrap-up. |
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Final Exam. Closed Book. Covering all Material in Subject. |
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