1 00:00:00 --> 00:00:07 2 00:00:07 --> 00:00:10 We have put some of the quiz stats here. 3 00:00:10 --> 00:00:15 The mean was about 75%. And I must tell you that that 4 00:00:15 --> 00:00:19 is very impressive. I guess MIT undergrads never 5 00:00:19 --> 00:00:24 cease to amaze me. And this was not an easy quiz. 6 00:00:24 --> 00:00:28 This was a relatively hard quiz. 7 00:00:28 --> 00:00:34 And that average implies that you guys did well on a 8 00:00:34 --> 00:00:38 relatively hard quiz. Good. 9 00:00:38 --> 00:00:45 Let's get back to our final lecture on amplifiers and small 10 00:00:45 --> 00:00:51 signal circuits. And as always let me start with 11 00:00:51 --> 00:00:56 a review. Very quickly -- 12 00:00:56 --> 00:01:02 13 00:01:02 --> 00:01:09 -- we came up with a notation to represent small signals. 14 00:01:09 --> 00:01:13 And our notation looked like this. 15 00:01:13 --> 00:01:20 Our total variable was small and capital, and this was a DC 16 00:01:20 --> 00:01:26 bias and this was a small signal. 17 00:01:26 --> 00:01:32 18 00:01:32 --> 00:01:36 This is also called the operating point. 19 00:01:36 --> 00:01:42 And the small signal is also called the incremental signal. 20 00:01:42 --> 00:01:47 In general, if you have some function, some variable of 21 00:01:47 --> 00:01:53 interest in the circuit, say a total variable V out, 22 00:01:53 --> 00:02:00 let's say it relates to some input variable as F of VI. 23 00:02:00 --> 00:02:08 So mathematically we can find out V out by simply finding the 24 00:02:08 --> 00:02:15 slope of this function at the operating point and then 25 00:02:15 --> 00:02:23 multiplying it by the incremental change in the input. 26 00:02:23 --> 00:02:29 Gold standard math. So we do the slope of this 27 00:02:29 --> 00:02:37 function and evaluate it at the operating point. 28 00:02:37 --> 00:02:40 So this would give us the slope of the function. 29 00:02:40 --> 00:02:44 And multiply that by small VI, which is incremental change. 30 00:02:44 --> 00:02:48 This is standard math. What this will tell you is 31 00:02:48 --> 00:02:52 given a small change in VI this function gives you, 32 00:02:52 --> 00:02:57 this expression gives you the small change in V out. 33 00:02:57 --> 00:03:05 And in lecture we have pretty much used this method so far, 34 00:03:05 --> 00:03:12 used the math to get to where we wanted it to be. 35 00:03:12 --> 00:03:20 And then the way we provided biasing and so on was for our 36 00:03:20 --> 00:03:26 amplifier in particular we had a bias voltage, 37 00:03:26 --> 00:03:32 some small signal value, VS. 38 00:03:32 --> 00:03:36 And this was output which was also given to be some output 39 00:03:36 --> 00:03:41 operating point plus a small change, which was a change in 40 00:03:41 --> 00:03:45 the output voltage. So what we have done here is 41 00:03:45 --> 00:03:48 mathematically computed small V out. 42 00:03:48 --> 00:03:53 And what I am showing you here is to get the same effect in a 43 00:03:53 --> 00:03:58 circuit is you build your circuit and replace what used to 44 00:03:58 --> 00:04:04 be a total variable with a DC bias plus a small change. 45 00:04:04 --> 00:04:08 And then you will get your output here. 46 00:04:08 --> 00:04:13 And this output will relate to this input using this 47 00:04:13 --> 00:04:15 expression. 48 00:04:15 --> 00:04:22 49 00:04:22 --> 00:04:34 So this is more review. To continue on with the math 50 00:04:34 --> 00:04:45 review, for our amplifier VO was given to be VS-K/2(vI-VT)^2 RL. 51 00:04:45 --> 00:04:54 So this was the output versus input relationship for the 52 00:04:54 --> 00:05:00 amplifier. And mathematically I could get 53 00:05:00 --> 00:05:06 the small change in the output VO by simply differentiating 54 00:05:06 --> 00:05:12 this function with respect to VI, evaluating that function, 55 00:05:12 --> 00:05:18 at capital VI and multiplying by the small change in the 56 00:05:18 --> 00:05:22 input. And the resulting expression 57 00:05:22 --> 00:05:26 that we got for small VO -- 58 00:05:26 --> 00:05:32 59 00:05:32 --> 00:05:37 -- was simply minus K, this was our DC value, 60 00:05:37 --> 00:05:44 and RL times small VI. So we derived all of this the 61 00:05:44 --> 00:05:48 last time. So nothing new so far. 62 00:05:48 --> 00:05:55 So my small signal output was some function given by 63 00:05:55 --> 00:06:03 K(VI-VT)RL times small vi. And notice that this is how VI 64 00:06:03 --> 00:06:07 relates to VO. And this is a constant with 65 00:06:07 --> 00:06:11 respect to VI. V capital I is a DC bias, 66 00:06:11 --> 00:06:17 so this is a constant. So therefore this is the linear 67 00:06:17 --> 00:06:21 relationship that we had set out to get. 68 00:06:21 --> 00:06:25 This term here, for reasons we will see today, 69 00:06:25 --> 00:06:31 this term here K(VI-VT) is called gm. 70 00:06:31 --> 00:06:34 Transconductance. We will look at it in more 71 00:06:34 --> 00:06:36 detail a little later. 72 00:06:36 --> 00:06:44 73 00:06:44 --> 00:06:46 Even more review. 74 00:06:46 --> 00:06:56 75 00:06:56 --> 00:07:02 So I can draw the transfer function and plot VO versus VI. 76 00:07:02 --> 00:07:07 Another way to graphically view what is going on is by plotting 77 00:07:07 --> 00:07:12 the load line curve for this circuit, so this is VI. 78 00:07:12 --> 00:07:17 And I said we draw that by first plotting the -- 79 00:07:17 --> 00:07:26 80 00:07:26 --> 00:07:30 These were our MOSFET curves. And we know that at some point 81 00:07:30 --> 00:07:37 the MOSFET gets into saturation, so this curve was iDS=K/2 VO^2. 82 00:07:37 --> 00:07:41 And to the right side of the curve the MOSFET is in 83 00:07:41 --> 00:07:45 saturation. And we said we will adhere to 84 00:07:45 --> 00:07:50 the saturation discipline and operate in this regime. 85 00:07:50 --> 00:07:56 When the MOSFET gets into this region it is in its triode 86 00:07:56 --> 00:08:01 region. And then we could draw the load 87 00:08:01 --> 00:08:05 line here. The load line codified the 88 00:08:05 --> 00:08:10 following relationship, iDS=VS/RL-VO/RL. 89 00:08:10 --> 00:08:16 This was a load line. So I have superimposed a load 90 00:08:16 --> 00:08:20 line on the device characteristics, 91 00:08:20 --> 00:08:27 and I am going to show you a little demonstration based on 92 00:08:27 --> 00:08:33 that at this point. So these curves were drawn for 93 00:08:33 --> 00:08:38 increasing values of VI. And if I choose some operating 94 00:08:38 --> 00:08:43 point here then this point would correspond to some bias, 95 00:08:43 --> 00:08:48 this bias point would correspond to some input voltage 96 00:08:48 --> 00:08:53 VI, a corresponding output bias VO and a corresponding current 97 00:08:53 --> 00:08:55 iDS. So iDS capitals, 98 00:08:55 --> 00:08:58 VO capitals, VI capitals represent the 99 00:08:58 --> 00:09:04 operating point values for our little circuit. 100 00:09:04 --> 00:09:11 So far there is nothing new. One thing we stopped the last 101 00:09:11 --> 00:09:18 time by pointing out that the gain of our amplifier, 102 00:09:18 --> 00:09:22 this is the gain, -K(VI-VT)RL. 103 00:09:22 --> 00:09:28 That is the gain A of the amplifier. 104 00:09:28 --> 00:09:33 That gain related to VI. A gain was proportional to 105 00:09:33 --> 00:09:37 VI-VT. So therefore if I increased VI, 106 00:09:37 --> 00:09:42 I would get more gain. So the question is how do we 107 00:09:42 --> 00:09:47 choose a bias point? And in our particular example, 108 00:09:47 --> 00:09:52 let's say we are free to play around with VI. 109 00:09:52 --> 00:10:00 So we play around with VI and I can choose various bias points. 110 00:10:00 --> 00:10:02 So where do you set the bias point? 111 00:10:02 --> 00:10:07 What are the various characteristics of the circuit 112 00:10:07 --> 00:10:10 that relate to my bias point? Well, first, 113 00:10:10 --> 00:10:14 of course, is gain. The gain depends on how I 114 00:10:14 --> 00:10:17 choose VI. I will show you that in a 115 00:10:17 --> 00:10:20 moment. The second important thing, 116 00:10:20 --> 00:10:24 in other words, if I choose a bias point that 117 00:10:24 --> 00:10:30 is a small VI then my gain is going to be smaller. 118 00:10:30 --> 00:10:35 If I choose a bias point that's at a much higher value of VI, 119 00:10:35 --> 00:10:38 I get a bigger gain. The second important 120 00:10:38 --> 00:10:42 consideration is operating range. 121 00:10:42 --> 00:10:48 122 00:10:48 --> 00:10:57 Notice that if I choose a bias point here then as the input 123 00:10:57 --> 00:11:01 changes -- Notice VI in this graph goes up 124 00:11:01 --> 00:11:05 or down, and I would be traversing and following 125 00:11:05 --> 00:11:09 different lines here in my MOSFET characteristic. 126 00:11:09 --> 00:11:14 And as VI increases the operating point would come up 127 00:11:14 --> 00:11:17 here and so on. So if about this operating 128 00:11:17 --> 00:11:23 point I varied my input voltage VI then, so let's say about this 129 00:11:23 --> 00:11:25 operating point, if my input VI, 130 00:11:25 --> 00:11:30 my small signal VI varied about a small range then 131 00:11:30 --> 00:11:35 correspondingly the output value would vary about this part of my 132 00:11:35 --> 00:11:39 load line. So notice now that the 133 00:11:39 --> 00:11:43 operating range, how far can VI vary before the 134 00:11:43 --> 00:11:47 MOSFET goes out of its saturation discipline? 135 00:11:47 --> 00:11:52 Well, on the low side my VI can come down to here. 136 00:11:52 --> 00:11:56 And we looked at the operating ranges for an amplifier. 137 00:11:56 --> 00:12:01 And I can come all the way down to VT. 138 00:12:01 --> 00:12:03 At that point the output will come here. 139 00:12:03 --> 00:12:07 Similarly at the high end VI could get up to a high value. 140 00:12:07 --> 00:12:10 And we computed that value in the last lecture. 141 00:12:10 --> 00:12:14 And the corresponding value of the input would be here. 142 00:12:14 --> 00:12:18 So in some sense I can traverse all the way from here to here 143 00:12:18 --> 00:12:20 and have the MOSFET remain in saturation. 144 00:12:20 --> 00:12:24 Remember we are not talking about linearity right now, 145 00:12:24 --> 00:12:28 just about the valid operating range based on my definition 146 00:12:28 --> 00:12:33 which is that the MOSFET should stay in saturation. 147 00:12:33 --> 00:12:37 So if I chose my operating point here then I get this range 148 00:12:37 --> 00:12:39 here. And, on the other hand, 149 00:12:39 --> 00:12:44 if I chose my operating point to be here, for negative 150 00:12:44 --> 00:12:49 excursions of the input signal I have a very small amount before 151 00:12:49 --> 00:12:52 I hit cutoff. So if I chose my operating 152 00:12:52 --> 00:12:56 point here then for negative traversals of VI about the 153 00:12:56 --> 00:13:01 operating point I very quickly hit cutoff. 154 00:13:01 --> 00:13:05 So if I want symmetric swings then this is the best that I can 155 00:13:05 --> 00:13:09 do in terms of the valid input operating range if I want 156 00:13:09 --> 00:13:12 symmetric swings given that this is my bias point. 157 00:13:12 --> 00:13:15 On the other hand, if I chose my bias point 158 00:13:15 --> 00:13:19 somewhere here, or very carefully chose my bias 159 00:13:19 --> 00:13:23 point then my input can vary on a much wider region and still 160 00:13:23 --> 00:13:27 get symmetric swings. And so therefore the choice of 161 00:13:27 --> 00:13:31 bias point also influences the maximum swing range of my input 162 00:13:31 --> 00:13:36 signal. I shouldn't call this operating 163 00:13:36 --> 00:13:40 range. I should call it input swing 164 00:13:40 --> 00:13:43 range. We defined the valid input 165 00:13:43 --> 00:13:50 operating range as the range for which the amplifier satisfied 166 00:13:50 --> 00:13:55 the saturation discipline. So the two key issues, 167 00:13:55 --> 00:14:02 gain and the input swing. Let me show you a quick demo 168 00:14:02 --> 00:14:09 and try to point out on a graph some of the characteristics that 169 00:14:09 --> 00:14:15 relate to the matter we have been talking about so far. 170 00:14:15 --> 00:14:21 So what I show here are these curves for the MOSFET. 171 00:14:21 --> 00:14:26 This is VO and this iDS. This is the zero point. 172 00:14:26 --> 00:14:33 Ignore this line down here. This line up here corresponds 173 00:14:33 --> 00:14:37 to the output voltage VO. What I am going to do now is, 174 00:14:37 --> 00:14:41 through some careful circuit hacking, I'm going to show show 175 00:14:41 --> 00:14:46 you a load line and show you the bias point, and show you how the 176 00:14:46 --> 00:14:50 bias point can be moved up and down by changing the input 177 00:14:50 --> 00:14:55 voltage which changes the corresponding output voltage. 178 00:14:55 --> 00:15:00 179 00:15:00 --> 00:15:02 It is hardly visible out there. 180 00:15:02 --> 00:15:08 181 00:15:08 --> 00:15:09 Is it there? OK. 182 00:15:09 --> 00:15:13 It is not really clear, but notice that as I increase 183 00:15:13 --> 00:15:16 my input, I am increasing my input. 184 00:15:16 --> 00:15:20 My output keeps coming down. And I hope your eyesight is 185 00:15:20 --> 00:15:24 better than mine because I don't see a dot up there. 186 00:15:24 --> 00:15:27 I am amazed. This is the first time this has 187 00:15:27 --> 00:15:30 happened to me. That's OK. 188 00:15:30 --> 00:15:33 All right. As you can see, 189 00:15:33 --> 00:15:38 as I change the input value the output operating point changes, 190 00:15:38 --> 00:15:43 and the dot out there traverses, articulates a load 191 00:15:43 --> 00:15:46 line. I guess I have to believe that 192 00:15:46 --> 00:15:51 there is a dot out there. Next what I will do is show you 193 00:15:51 --> 00:15:55 some more fun stuff. What I will do is instead of 194 00:15:55 --> 00:16:00 having just a dot by having a DC voltage, let me apply an input 195 00:16:00 --> 00:16:05 sinusoid. So if I apply an input sinusoid 196 00:16:05 --> 00:16:09 at some bias then I should see an articulation of the 197 00:16:09 --> 00:16:14 corresponding region of the load line corresponding to the input. 198 00:16:14 --> 00:16:18 So, as you can see here, now the bottom line, 199 00:16:18 --> 00:16:21 here is my input and this is my output. 200 00:16:21 --> 00:16:26 And notice that this the region of the load line articulated 201 00:16:26 --> 00:16:30 when the input is of this magnitude. 202 00:16:30 --> 00:16:33 Now let's have some fun. As I increase my input, 203 00:16:33 --> 00:16:37 you can see that a larger portion of the load line is 204 00:16:37 --> 00:16:39 articulated, right? There you go. 205 00:16:39 --> 00:16:43 And as I decrease my input a smaller region of the load line 206 00:16:43 --> 00:16:46 is articulated. Let's leave it here for a 207 00:16:46 --> 00:16:49 moment. And what I will do next, 208 00:16:49 --> 00:16:52 this is the region here that we are looking at, 209 00:16:52 --> 00:16:55 let me increase the bias. If I increase the bias, 210 00:16:55 --> 00:16:59 if I increase VI, what do you think should happen 211 00:16:59 --> 00:17:04 to this line here? Well, if I increase the bias, 212 00:17:04 --> 00:17:06 the line should go up, right? 213 00:17:06 --> 00:17:09 Because remember the dot? The dot is in the middle of 214 00:17:09 --> 00:17:12 this thing here. If I increase the bias this 215 00:17:12 --> 00:17:15 should move up here. So that line moves up. 216 00:17:15 --> 00:17:19 Do you expect anything else to happen to that line? 217 00:17:19 --> 00:17:20 Pardon? It increases, 218 00:17:20 --> 00:17:23 exactly. If I increase the bias point to 219 00:17:23 --> 00:17:26 here then this must also increase because my gain has 220 00:17:26 --> 00:17:30 increased. Let me do that. 221 00:17:30 --> 00:17:32 So let me increase the input bias. 222 00:17:32 --> 00:17:38 Indeed notice that the region of the load line articulated is 223 00:17:38 --> 00:17:41 larger now. Let me decrease the bias. 224 00:17:41 --> 00:17:46 And notice that because the gain is smaller the little 225 00:17:46 --> 00:17:51 segment shown is also smaller. I have shown you two things so 226 00:17:51 --> 00:17:54 far. One is that I as I increase my 227 00:17:54 --> 00:18:00 bias the line indeed rises up corresponding to a higher value 228 00:18:00 --> 00:18:06 for the input operating point. And the second is that I get a 229 00:18:06 --> 00:18:11 larger swing in the output as I increase the bias. 230 00:18:11 --> 00:18:16 Just to show that for those like me who were visually 231 00:18:16 --> 00:18:21 challenged in terms of viewing that little dot up there, 232 00:18:21 --> 00:18:26 let me get some audio so you can actually hear the sinusoidal 233 00:18:26 --> 00:18:30 tone. It is a big annoying. 234 00:18:30 --> 00:18:35 235 00:18:35 --> 00:18:39 As I reduce the bias the gain is decreased. 236 00:18:39 --> 00:18:45 As I increase the bias you can see that the gain is increased 237 00:18:45 --> 00:18:50 and the tone is louder. Let's have some more fun and 238 00:18:50 --> 00:18:56 let's play some music now. And what I am going to show you 239 00:18:56 --> 00:19:01 with the music -- The reason I play the music is 240 00:19:01 --> 00:19:05 not just for fun. Well, it's 85% fun and 15% 241 00:19:05 --> 00:19:08 learning. Can we turn it on for a second? 242 00:19:08 --> 00:19:12 What I would like to do is, as we play the music, 243 00:19:12 --> 00:19:17 the reason I am playing the music for that 15% is so you can 244 00:19:17 --> 00:19:21 listen to distortion. I want you to listen to the 245 00:19:21 --> 00:19:24 distortion. That is when the articulation 246 00:19:24 --> 00:19:30 is here you are not going to get much distortion. 247 00:19:30 --> 00:19:34 But as I get into cutoff you should be getting a bunch of 248 00:19:34 --> 00:19:37 distortion. Similarly, as you get into the 249 00:19:37 --> 00:19:42 triode region you should also be getting distortion because the 250 00:19:42 --> 00:19:47 amplification from being somewhat nonlinear here becomes 251 00:19:47 --> 00:19:50 highly nonlinear at those two points. 252 00:19:50 --> 00:19:54 So let's just play the signal. So volume increases, 253 00:19:54 --> 00:19:58 or rather the amplitude increases by increasing the 254 00:19:58 --> 00:20:02 bias. Now you should hear the volume 255 00:20:02 --> 00:20:05 go down and distortion. 256 00:20:05 --> 00:20:15 257 00:20:15 --> 00:20:17 So notice now that the bias point is way down here. 258 00:20:17 --> 00:20:20 So the gain is very low, and plus there is a distortion 259 00:20:20 --> 00:20:23 because of cutoff. Now what I will do is blast it 260 00:20:23 --> 00:20:26 up here, and you will see that the volume has gone up but then 261 00:20:26 --> 00:20:29 you see distortion again. Let's see if you can stand the 262 00:20:29 --> 00:20:31 volume here. 263 00:20:31 --> 00:20:54 264 00:20:54 --> 00:20:56 Even the CD doesn't like that. 265 00:20:56 --> 00:21:02 266 00:21:02 --> 00:21:05 Notice that as I went up here the volume kept increasing 267 00:21:05 --> 00:21:09 because the gain kept increasing, but as I got into 268 00:21:09 --> 00:21:12 the triode region I began to lose my gain because, 269 00:21:12 --> 00:21:17 remember, the amplifier doesn't have gain in the triode region, 270 00:21:17 --> 00:21:21 MOSFET in its triode region, and we also get a bunch of 271 00:21:21 --> 00:21:24 distortion out there. Finally, it turns out that as 272 00:21:24 --> 00:21:28 people are building amplifiers -- 273 00:21:28 --> 00:21:33 I think this was in the mid to late `50s and `60s and so on. 274 00:21:33 --> 00:21:38 They said man, electrical engineers are not 275 00:21:38 --> 00:21:44 going to get their thing right. So they invented a new kind of 276 00:21:44 --> 00:21:48 music which was much more tolerant to distortion. 277 00:21:48 --> 00:21:52 And I will play that music for you. 278 00:21:52 --> 00:21:57 It is called hard rock. I challenge you to tell me it 279 00:21:57 --> 00:22:00 is distorting. 280 00:22:00 --> 00:22:20 281 00:22:20 --> 00:22:22 Sounds good to me. 282 00:22:22 --> 00:22:30 283 00:22:30 --> 00:22:31 OK. All right. 284 00:22:31 --> 00:22:34 That'll do it. Thank you. 285 00:22:34 --> 00:22:40 I hope there are no hard rock musicians in here who will come 286 00:22:40 --> 00:22:45 and beat me up after lecture or something. 287 00:22:45 --> 00:22:49 All right. Believe it or not most of that 288 00:22:49 --> 00:22:53 was review. There is nothing new today 289 00:22:53 --> 00:22:59 besides some fun and games and so on. 290 00:22:59 --> 00:23:03 I will give you a breather for five seconds before jumping into 291 00:23:03 --> 00:23:05 something even more fun. 292 00:23:05 --> 00:23:27 293 00:23:27 --> 00:23:30 I want you to look at the middle board here. 294 00:23:30 --> 00:23:33 And, as I told you in the beginning of 6.002, 295 00:23:33 --> 00:23:36 engineering is about building useful systems. 296 00:23:36 --> 00:23:40 Engineering is not about showing off at math or saying 297 00:23:40 --> 00:23:43 man, I am really cool in math and stuff. 298 00:23:43 --> 00:23:46 Engineering is about building useful systems, 299 00:23:46 --> 00:23:49 and you want to find the simplest, easiest, 300 00:23:49 --> 00:23:53 cheapest way to get there. Unlike deep areas of math and 301 00:23:53 --> 00:23:55 theory and so on, the beauty is in the 302 00:23:55 --> 00:23:59 simplicity. So the aesthetics are in how 303 00:23:59 --> 00:24:02 simply can we make things and still get to where we want to 304 00:24:02 --> 00:24:04 be? All through the course what you 305 00:24:04 --> 00:24:08 will be seeing happening again and again and again is when 306 00:24:08 --> 00:24:11 things begin to get too grovelly in terms of math, 307 00:24:11 --> 00:24:14 we will step back and say oops, we are engineers, 308 00:24:14 --> 00:24:16 remember? Let's find a much simpler way 309 00:24:16 --> 00:24:19 to do it and use intuition. So time and time and time 310 00:24:19 --> 00:24:23 again, I am going to take you on a simpler path where you can 311 00:24:23 --> 00:24:25 solve things by inspection by pure intuition. 312 00:24:25 --> 00:24:30 Most circuit designers do that. So take a look at this. 313 00:24:30 --> 00:24:33 I don't like this nasty differentiation here. 314 00:24:33 --> 00:24:37 That's getting into late high school calculus and so on. 315 00:24:37 --> 00:24:42 Let's avoid the math and let's see if you find some way of 316 00:24:42 --> 00:24:45 doing it that is even much more simpler. 317 00:24:45 --> 00:24:50 And that is what I will do next and show you what is called the 318 00:24:50 --> 00:24:54 small signal circuit view. A purely circuit way of 319 00:24:54 --> 00:24:58 developing the small signal model. 320 00:24:58 --> 00:25:02 So let me just start by drawing the large signal equivalent 321 00:25:02 --> 00:25:06 circuit for you. I will draw it here for reasons 322 00:25:06 --> 00:25:10 that will be obvious at the end of the class. 323 00:25:10 --> 00:25:45 324 00:25:45 --> 00:25:48 All right. This is the large signal 325 00:25:48 --> 00:25:54 equivalent circuit model for our MOSFET amplifier. 326 00:25:54 --> 00:25:59 VS and here is my current source. 327 00:25:59 --> 00:26:02 iDS relates to the square of VI minus VT. 328 00:26:02 --> 00:26:06 So stare at that for a second. And that is a nonlinear 329 00:26:06 --> 00:26:10 circuit. iDS relates to the square of VI 330 00:26:10 --> 00:26:13 minus VT. Let me start by making the 331 00:26:13 --> 00:26:17 following claim. Let me shoot from the hip here 332 00:26:17 --> 00:26:22 and make the following grand claim, and then I will show you 333 00:26:22 --> 00:26:26 how I can prove that claim. The grand claim I am about to 334 00:26:26 --> 00:26:32 make says the following. A bunch of little devices here. 335 00:26:32 --> 00:26:37 It is a nonlinear circuit. Just suppose for a moment we do 336 00:26:37 --> 00:26:41 a Gedanken experiment. Suppose I replace each of my 337 00:26:41 --> 00:26:46 circuit elements here with its linearized element equivalent. 338 00:26:46 --> 00:26:49 In other words, here is a VS source, 339 00:26:49 --> 00:26:54 here is a dependent current source, let me replace them with 340 00:26:54 --> 00:26:59 their linear equivalent circuit models. 341 00:26:59 --> 00:27:02 In other words, with their corresponding small 342 00:27:02 --> 00:27:05 signal element models. And I will show you what those 343 00:27:05 --> 00:27:08 are in a second. The resistor has a 344 00:27:08 --> 00:27:10 corresponding small signal element. 345 00:27:10 --> 00:27:15 The dependent current source has a corresponding small signal 346 00:27:15 --> 00:27:18 behavioral element model. And what I am going to do is 347 00:27:18 --> 00:27:22 keep the same circuit connections and simply pull out 348 00:27:22 --> 00:27:26 the large signal model for the element and replace it with a 349 00:27:26 --> 00:27:31 small signal element model. And by the nature of the small 350 00:27:31 --> 00:27:34 signal model they are all going to be linear. 351 00:27:34 --> 00:27:37 So what I am going to be left with is a linear circuit with 352 00:27:37 --> 00:27:39 simple linear circuit elements in there. 353 00:27:39 --> 00:27:42 And then once I have a linear circuit, I should be able to 354 00:27:42 --> 00:27:45 analyze that linear circuit using methods 1, 355 00:27:45 --> 00:27:48 2 and 3, superposition, Thevenin, node method and so 356 00:27:48 --> 00:27:50 on. And certainly the intuitive 357 00:27:50 --> 00:27:53 methods like superposition and Thevenin, which make life a lot 358 00:27:53 --> 00:27:56 easier for me with linear models, and thereby get the 359 00:27:56 --> 00:28:00 function that I am looking for very quickly. 360 00:28:00 --> 00:28:04 Again, my claim is that I can replace each of these large 361 00:28:04 --> 00:28:09 signal models by just small signal equivalents and then just 362 00:28:09 --> 00:28:14 analyze the resultant circuit. And I claim that I should be 363 00:28:14 --> 00:28:18 able to get the same answer. That's a claim. 364 00:28:18 --> 00:28:21 All right? So what I will do is give you 365 00:28:21 --> 00:28:24 an informal proof for why I can do that. 366 00:28:24 --> 00:28:29 And I also ask you to refer to Section 8.2.1 of the course 367 00:28:29 --> 00:28:33 notes to go through the foundations of the small circuit 368 00:28:33 --> 00:28:39 model in more detail. The intuition is that, 369 00:28:39 --> 00:28:43 remember KVL and KCL? I can write down KVL and KCL 370 00:28:43 --> 00:28:49 for every loop in that circuit and every node in that circuit. 371 00:28:49 --> 00:28:53 If I do KVL and KCL, I will end up with something 372 00:28:53 --> 00:28:57 like this. For the input loop I get VI 373 00:28:57 --> 00:29:00 something or the other applying KVL. 374 00:29:00 --> 00:29:07 For the output loop I get V out something or the other. 375 00:29:07 --> 00:29:11 And then applying KCL I get some other equation in iDS. 376 00:29:11 --> 00:29:16 So here are my KVL and KCL equations for that circuit. 377 00:29:16 --> 00:29:22 Now, KVL and KCL are simply a different representation of the 378 00:29:22 --> 00:29:27 circuit because within those KVL and KCL is encoded the topology 379 00:29:27 --> 00:29:32 of the circuit. Remember each KVL equation 380 00:29:32 --> 00:29:36 represents a loop and each KCL equation represents how nodes 381 00:29:36 --> 00:29:41 are connected together. So KVL and KCL equations encode 382 00:29:41 --> 00:29:44 within them the topology of my circuit. 383 00:29:44 --> 00:29:47 What I do next is, say, I replace each of these 384 00:29:47 --> 00:29:52 with the bias plus the small signal, so I get the bias plus 385 00:29:52 --> 00:29:57 the small signal and keep the equations the same. 386 00:29:57 --> 00:30:10 387 00:30:10 --> 00:30:14 All I have done in my big set of KVL, KCL equations, 388 00:30:14 --> 00:30:18 I have simply replaced the total variable with the large 389 00:30:18 --> 00:30:21 signal variable and the small signal quantity. 390 00:30:21 --> 00:30:26 Then comes a key trick. The key trick is that because 391 00:30:26 --> 00:30:30 the bias point variables, they are a valid solution to 392 00:30:30 --> 00:30:33 the circuit. The circuit is in this 393 00:30:33 --> 00:30:36 quiescent state, and those are valid solutions 394 00:30:36 --> 00:30:39 to circuit. So therefore I can cancel them 395 00:30:39 --> 00:30:42 out. So the VI, the large signal 396 00:30:42 --> 00:30:45 values can be cancelled out leaving just small signal 397 00:30:45 --> 00:30:48 variables in there. So from the KVL, 398 00:30:48 --> 00:30:52 KCL equations I can cancel out the large signal values, 399 00:30:52 --> 00:30:56 the DC bias points because they satisfy the KVL and KCL 400 00:30:56 --> 00:30:59 themselves. In other words, 401 00:30:59 --> 00:31:02 I could have written VI plus V out and so on. 402 00:31:02 --> 00:31:07 Since they are satisfied I just strike out the large signal 403 00:31:07 --> 00:31:11 variable from both sides of each of these equations, 404 00:31:11 --> 00:31:16 so what is left is the same KVL, KCL equations but with 405 00:31:16 --> 00:31:20 small variables in place of the big variables. 406 00:31:20 --> 00:31:24 What that should tell you, this informal proof should tell 407 00:31:24 --> 00:31:29 you is that the small signal variables should then satisfy 408 00:31:29 --> 00:31:34 the same form of the KVL, KCL equations that the total 409 00:31:34 --> 00:31:38 variables satisfy. And because the KVL, 410 00:31:38 --> 00:31:43 KCL equations are a reflection of the topology of the circuit, 411 00:31:43 --> 00:31:48 what that says is that the small signal variables must also 412 00:31:48 --> 00:31:52 satisfy KVL and KCL. And since these arrive from the 413 00:31:52 --> 00:31:56 small signal elements that says that I can replace the big 414 00:31:56 --> 00:32:01 elements with the small elements and KVL and KCL will hold for 415 00:32:01 --> 00:32:06 the resulting circuit. This is a very quick breeze 416 00:32:06 --> 00:32:11 through, an informal proof to show that I can replace the big 417 00:32:11 --> 00:32:17 elements with the corresponding little element models and then 418 00:32:17 --> 00:32:22 simply apply linear techniques. Refer to Section 8.2.1 for more 419 00:32:22 --> 00:32:28 foundations and more discussion about the foundations for why we 420 00:32:28 --> 00:32:34 can do this. That brings up the small signal 421 00:32:34 --> 00:32:40 circuit method. The circuit method for small 422 00:32:40 --> 00:32:47 signal analysis has three steps. The first step is find 423 00:32:47 --> 00:32:55 operating point by using LS. First you analyze your large 424 00:32:55 --> 00:33:02 signal circuit and find the operating point. 425 00:33:02 --> 00:33:06 You have to do this, because remember, 426 00:33:06 --> 00:33:14 the small signal models depend on the operating point values. 427 00:33:14 --> 00:33:21 Remember the gain of our amplifier depended on the bias 428 00:33:21 --> 00:33:25 point. Second step is develop small 429 00:33:25 --> 00:33:34 signal models of elements. Second step is take each of the 430 00:33:34 --> 00:33:41 elements in your circuit and find their equivalent small 431 00:33:41 --> 00:33:46 circuit model for each of the elements. 432 00:33:46 --> 00:33:55 Third step is replace original elements with their small signal 433 00:33:55 --> 00:34:01 model elements. Third step is simply take the 434 00:34:01 --> 00:34:08 large elements and replace them with their small signal 435 00:34:08 --> 00:34:14 equivalent models. Then analyze resulting circuit, 436 00:34:14 --> 00:34:19 and that circuit will be a linear circuit. 437 00:34:19 --> 00:34:26 So let's do an example. I will just use the amplifier 438 00:34:26 --> 00:34:34 as an example of this method. And convince you that you are 439 00:34:34 --> 00:34:40 going to get the same expression at the end, but just so, 440 00:34:40 --> 00:34:46 so simply without even the smallest amount of grubby math. 441 00:34:46 --> 00:34:51 Three steps. The first step is to find the 442 00:34:51 --> 00:34:56 operating point using the large signal model. 443 00:34:56 --> 00:35:01 And let me just do that here. I get my V out = 444 00:35:01 --> 00:35:07 VS-K/2(VI-VT)^2 RL. Let me just write down that out 445 00:35:07 --> 00:35:09 here. Don't worry about copying that 446 00:35:09 --> 00:35:12 down. It is on the last page of your 447 00:35:12 --> 00:35:15 notes. The first step of the method 448 00:35:15 --> 00:35:19 simply applies the large signal model and finds out the behavior 449 00:35:19 --> 00:35:24 of that circuit to find out what the bias point values are. 450 00:35:24 --> 00:35:28 The second step is to develop the small signal model of my 451 00:35:28 --> 00:35:33 elements. How do I go about developing 452 00:35:33 --> 00:35:36 the small signal models of elements? 453 00:35:36 --> 00:35:42 Let's start with the MOSFET. The large signal model for the 454 00:35:42 --> 00:35:46 MOSFET looks like this. 455 00:35:46 --> 00:35:53 456 00:35:53 --> 00:35:56 Here is my Vgs. This is my gate. 457 00:35:56 --> 00:36:00 This is my drain. This is my source. 458 00:36:00 --> 00:36:03 And I know my iDS to be K/2(Vgs-VT)^2. 459 00:36:03 --> 00:36:07 So this is the large signal model for the MOSFET, 460 00:36:07 --> 00:36:12 again in saturation. I am talking about all of these 461 00:36:12 --> 00:36:15 models are under the saturation discipline. 462 00:36:15 --> 00:36:20 So Vgs relates to iDS in the following way for the MOSFET. 463 00:36:20 --> 00:36:24 That is iDS, is K/2 and that is my square 464 00:36:24 --> 00:36:28 law relationship. So what is a corresponding 465 00:36:28 --> 00:36:34 small signal model? I go ahead and start with this. 466 00:36:34 --> 00:36:40 The corresponding small signal model simply says that iDS 467 00:36:40 --> 00:36:43 relates to Vgs in the following way. 468 00:36:43 --> 00:36:49 All I have to do is find a small signal equivalent where I 469 00:36:49 --> 00:36:54 need to find out, given a small change in the 470 00:36:54 --> 00:37:00 input Vgs, what is the small change in the iDS? 471 00:37:00 --> 00:37:04 So I can apply my standard trick to a much simpler 472 00:37:04 --> 00:37:08 expression here, which is iDS simply, 473 00:37:08 --> 00:37:14 I differentiate this function with respect to Vgs. 474 00:37:14 --> 00:37:19 475 00:37:19 --> 00:37:24 So I don't completely eliminate the math here, 476 00:37:24 --> 00:37:28 but it is a much simpler problem here. 477 00:37:28 --> 00:37:34 At Vgs equals the bias point times small vgs. 478 00:37:34 --> 00:37:41 I can find the small change in iDS corresponding to a small 479 00:37:41 --> 00:37:47 change in the input using this expression. 480 00:37:47 --> 00:37:52 That gives me iDS as simply K(Vgs-VT) vgs. 481 00:37:52 --> 00:37:58 I call this gm, and I will tell you why in a 482 00:37:58 --> 00:38:02 second. So what does this expression 483 00:38:02 --> 00:38:05 say? This expression says that if I 484 00:38:05 --> 00:38:10 have a small change in Vgs then this will be my small change in 485 00:38:10 --> 00:38:12 iDS. Notice that the resulting small 486 00:38:12 --> 00:38:16 signal model is also a dependent current source. 487 00:38:16 --> 00:38:20 It is a voltage controlled dependent current source. 488 00:38:20 --> 00:38:25 So the output is the current, and it is a dependent current 489 00:38:25 --> 00:38:30 source and it depends on the input voltage. 490 00:38:30 --> 00:38:33 The good news is that notice that this one, 491 00:38:33 --> 00:38:39 this expression here gm is a constant related to the bias 492 00:38:39 --> 00:38:42 point values. Therefore, notice that the 493 00:38:42 --> 00:38:47 small signal model for the MOSFET in saturation, 494 00:38:47 --> 00:38:51 not surprisingly, is a linear voltage controlled 495 00:38:51 --> 00:38:56 current source according to the following expression. 496 00:38:56 --> 00:39:01 So iDS=gm Vgs. Gm is a representation for 497 00:39:01 --> 00:39:05 K(Vgs-VT) and is called a transconductance. 498 00:39:05 --> 00:39:10 It is called a transconductance because it, in some sense, 499 00:39:10 --> 00:39:15 deflects the conductance properties of this based on the 500 00:39:15 --> 00:39:19 input. So it is a transconductance. 501 00:39:19 --> 00:39:24 So this value is called Vgs. Therefore, I can build the 502 00:39:24 --> 00:39:32 small signal model as follows. Vgs is a voltage controlled 503 00:39:32 --> 00:39:38 current source and iDS is simply gm Vgs. 504 00:39:38 --> 00:39:45 So this is my gate, drain, source. 505 00:39:45 --> 00:39:55 506 00:39:55 --> 00:39:59 So that is the small signal model for my MOSFET. 507 00:39:59 --> 00:40:05 As a next step what are the other elements in my circuit? 508 00:40:05 --> 00:40:08 Let's see. I have a voltage source and I 509 00:40:08 --> 00:40:12 have a resistor, so let me find out the 510 00:40:12 --> 00:40:17 corresponding small signal model for a DC supply VS. 511 00:40:17 --> 00:40:21 This is Page 7. I will do it mathematically for 512 00:40:21 --> 00:40:27 you, but often times it is always good to do a sanity check 513 00:40:27 --> 00:40:31 using intuition. Let me ask you, 514 00:40:31 --> 00:40:38 the large signal for a DC supply looks like this. 515 00:40:38 --> 00:40:44 516 00:40:44 --> 00:40:49 The element law for a voltage source is VS equals some capital 517 00:40:49 --> 00:40:52 VS. It is a constant voltage. 518 00:40:52 --> 00:40:58 So what do you expect to be the small signal model for a voltage 519 00:40:58 --> 00:41:01 source? In other words, 520 00:41:01 --> 00:41:05 for a small change, suppose I have a small change 521 00:41:05 --> 00:41:09 in the current, by how much should the output 522 00:41:09 --> 00:41:12 VS change? It shouldn't change. 523 00:41:12 --> 00:41:16 It is a voltage source. So what does intuition tell you 524 00:41:16 --> 00:41:20 is a small signal model for the voltage source? 525 00:41:20 --> 00:41:23 A short. So the key here is that a 526 00:41:23 --> 00:41:28 voltage source behaves like a short circuit for small 527 00:41:28 --> 00:41:32 perturbations. In other words, 528 00:41:32 --> 00:41:38 if I change the current flowing through it by a small amount 529 00:41:38 --> 00:41:42 somehow, the output is still going to held at VS. 530 00:41:42 --> 00:41:47 In other words, small signals are simply going 531 00:41:47 --> 00:41:52 to scoot through this voltage source without having any impact 532 00:41:52 --> 00:41:58 whatsoever on the voltage. Or mathematically I could also 533 00:41:58 --> 00:42:04 do small vs is del by del IS of VS evaluated at IS equals some 534 00:42:04 --> 00:42:10 capital IS times small IS. And therefore VS equals zero. 535 00:42:10 --> 00:42:15 What that means is that the small signal model for my 536 00:42:15 --> 00:42:20 voltage source is simply a short circuit. 537 00:42:20 --> 00:42:26 538 00:42:26 --> 00:42:31 So in a small circuit voltage sources appear like a short 539 00:42:31 --> 00:42:37 circuit. Finally, I have a resistor, 540 00:42:37 --> 00:42:42 my resistor R. Let me find out its 541 00:42:42 --> 00:42:47 corresponding small signal model. 542 00:42:47 --> 00:42:54 The large signal model looks like this R, VR, 543 00:42:54 --> 00:42:58 IR. And I know that VR is simply 544 00:42:58 --> 00:43:04 RIR. And to find the small signal 545 00:43:04 --> 00:43:09 equivalent I do del of IRR divided by del IR for IR 546 00:43:09 --> 00:43:14 calculated at some constant value times small IR. 547 00:43:14 --> 00:43:21 What I am looking to do is to find out what is the change in 548 00:43:21 --> 00:43:29 the voltage across R for a small perturbation in the current? 549 00:43:29 --> 00:43:33 Again, let me exhort you to rely on intuition to at least 550 00:43:33 --> 00:43:36 sanity check your answers. So what do you think this 551 00:43:36 --> 00:43:39 should look like? It's a resistor and I have a 552 00:43:39 --> 00:43:43 small change in the current, by what do you expect the 553 00:43:43 --> 00:43:45 voltage to change? Think about, 554 00:43:45 --> 00:43:49 for the next five seconds, what the small signal model for 555 00:43:49 --> 00:43:54 this should look like and then I will go ahead and write down the 556 00:43:54 --> 00:43:56 answer. 557 00:43:56 --> 00:44:06 558 00:44:06 --> 00:44:09 So differentiating I simply get RIR. 559 00:44:09 --> 00:44:15 In other words, for a resistor the small signal 560 00:44:15 --> 00:44:19 model is the resistor itself. 561 00:44:19 --> 00:44:29 562 00:44:29 --> 00:44:33 So what I have done so far, let me just take you through 563 00:44:33 --> 00:44:37 where we are right now, give you the big picture there. 564 00:44:37 --> 00:44:41 I began by suggesting that looking to find an even simpler 565 00:44:41 --> 00:44:46 way to do small signal analysis. I gave you an informal proof to 566 00:44:46 --> 00:44:50 show that if I had small signal element models for all of my 567 00:44:50 --> 00:44:55 elements, I could simply replace them in the circuit and then do 568 00:44:55 --> 00:44:59 a corresponding linear circuit analysis phase to get the result 569 00:44:59 --> 00:45:04 I am looking for. There are three steps to the 570 00:45:04 --> 00:45:06 method. As a first step we began by 571 00:45:06 --> 00:45:10 finding small signal models for each of our elements. 572 00:45:10 --> 00:45:14 For the nonlinear MOSFET the small signal model was a linear 573 00:45:14 --> 00:45:18 dependent current source. For a voltage source the 574 00:45:18 --> 00:45:21 corresponding small signal model was a short circuit. 575 00:45:21 --> 00:45:25 Again, that makes sense intuitively if I change the 576 00:45:25 --> 00:45:30 current through a voltage source by a small amount. 577 00:45:30 --> 00:45:32 By how much does the voltage change? 578 00:45:32 --> 00:45:34 It is a voltage source, silly. 579 00:45:34 --> 00:45:38 The voltage doesn't change. So the small signal V, 580 00:45:38 --> 00:45:43 the small change in the voltage is zero, and that is the same 581 00:45:43 --> 00:45:47 thing as a short circuit. For a resistor by how much does 582 00:45:47 --> 00:45:51 the voltage change if I change the current by a small amount? 583 00:45:51 --> 00:45:55 Well, it will change by R times the current change, 584 00:45:55 --> 00:46:00 and that is the property of a resistor, R. 585 00:46:00 --> 00:46:04 As a final step what I would like to do, on Page 8, 586 00:46:04 --> 00:46:10 I'd like to very quickly draw for you the small signal circuit 587 00:46:10 --> 00:46:14 and then analyze it. This is the large signal 588 00:46:14 --> 00:46:18 circuit. That is a large signal circuit. 589 00:46:18 --> 00:46:22 And let me draw the small signal circuit. 590 00:46:22 --> 00:46:27 And the method says simply pluck out, gouge out each of 591 00:46:27 --> 00:46:32 these elements. And simply replace each of 592 00:46:32 --> 00:46:37 these nasty nonlinear elements with the corresponding small 593 00:46:37 --> 00:46:41 signal linear equivalents. So let's do that. 594 00:46:41 --> 00:46:47 Remember, for the input you replace input with its small 595 00:46:47 --> 00:46:52 signal voltage because I am telling you that it's sourcing a 596 00:46:52 --> 00:46:55 small change in VI. So that is VI. 597 00:46:55 --> 00:47:00 And then I replace a short for VS. 598 00:47:00 --> 00:47:10 I replace an R for RL because it is an RL itself for the small 599 00:47:10 --> 00:47:17 signal model. And then for the dependent 600 00:47:17 --> 00:47:27 source, we discovered that the dependent source was a linear 601 00:47:27 --> 00:47:35 dependent source given where ids=gmvi. 602 00:47:35 --> 00:47:38 Remember, this was my small VO. Here you go. 603 00:47:38 --> 00:47:43 I have a small signal circuit here where I have simply created 604 00:47:43 --> 00:47:48 that by replacing each of the big elements by little 605 00:47:48 --> 00:47:51 rinky-dink elements. Now these are all linear 606 00:47:51 --> 00:47:56 elements so I can do a really simple linear analysis. 607 00:47:56 --> 00:48:01 What method shall we use? Well, this is so simple. 608 00:48:01 --> 00:48:06 I will just go ahead and use the node method. 609 00:48:06 --> 00:48:11 So applying the node method at the node with voltage VO, 610 00:48:11 --> 00:48:17 what I will do is the current going up, VO divided by RL 611 00:48:17 --> 00:48:20 equals the current going down iDS. 612 00:48:20 --> 00:48:27 And so the current going up is VO divided by RL and the current 613 00:48:27 --> 00:48:33 going down is -- Oops, I should have done this. 614 00:48:33 --> 00:48:41 The total current going out is zero, so the sum of these two is 615 00:48:41 --> 00:48:45 zero. That is my good old node method 616 00:48:45 --> 00:48:49 here. And I know that iDS is simply 617 00:48:49 --> 00:48:54 gmvi equals zero. So right there I have the 618 00:48:54 --> 00:49:03 relationship between VO and VI. So VO is simply minus gmviRL. 619 00:49:03 --> 00:49:11 And remember gm was simply K VI minus VT. 620 00:49:11 --> 00:49:17 621 00:49:17 --> 00:49:18 We are done, OK? 622 00:49:18 --> 00:49:21 What have we here? I created a linear circuit 623 00:49:21 --> 00:49:25 which simply comprised small signal models for each of my big 624 00:49:25 --> 00:49:28 elements. And then I simply did a 625 00:49:28 --> 00:49:32 straightforward linear analysis using any one of the linear 626 00:49:32 --> 00:49:36 techniques I knew about. This is simple enough so I 627 00:49:36 --> 00:49:40 apply the node method. And I've got the equation at 628 00:49:40 --> 00:49:44 this node, simplified it and I directly got the answer. 629 00:49:44 --> 00:49:48 In one or two steps I directly gave you the output as a 630 00:49:48 --> 00:49:52 function of the input. It can't get any simpler. 631 00:49:52 --> 49:55 Thank you.