1 00:00:00 --> 00:00:17 2 00:00:17 --> 00:00:20 All right. Good morning. 3 00:00:20 --> 00:00:26 Let's get going. In today's lecture we continue 4 00:00:26 --> 00:00:34 with the operational amplifier, "op amp" for short. 5 00:00:34 --> 00:00:40 And what we are going to do is just build up a bunch of fun 6 00:00:40 --> 00:00:43 building blocks using the op amp. 7 00:00:43 --> 00:00:46 As a quick review -- 8 00:00:46 --> 00:00:57 9 00:00:57 --> 00:01:01 To quickly review what we've seen about the op amp -- 10 00:01:01 --> 00:01:09 11 00:01:09 --> 00:01:16 We represented the op amp as a device that looked like this 12 00:01:16 --> 00:01:23 where the amplifier had an incredibly high gain. 13 00:01:23 --> 00:01:30 So, if I had a small voltage difference here -- 14 00:01:30 --> 00:01:34 I call this v plus and this v minus with respect to ground. 15 00:01:34 --> 00:01:39 And if I had a small voltage difference then this gain here 16 00:01:39 --> 00:01:43 would multiply the difference by a large number and thereby 17 00:01:43 --> 00:01:48 giving me an output that was on the order of a million times 18 00:01:48 --> 00:01:53 greater than this difference. And because of that when I use 19 00:01:53 --> 00:01:57 the op amp in a mode like this without any negative feedback 20 00:01:57 --> 00:02:02 the output would usually crank up to the positive rail or the 21 00:02:02 --> 00:02:07 negative rail. We also saw that it had 22 00:02:07 --> 00:02:14 infinite input resistance so that the current flowing in here 23 00:02:14 --> 00:02:20 or here was zero and also had zero output resistance. 24 00:02:20 --> 00:02:27 This is my ideal op amp where irrespective of what load I 25 00:02:27 --> 00:02:35 connect here the op amp would supply pretty much any current. 26 00:02:35 --> 00:02:38 Now, in practical op amps that's not the case. 27 00:02:38 --> 00:02:42 But suffice it to say that when used as an ideal op amp the 28 00:02:42 --> 00:02:46 output impedance, the output resistance is going 29 00:02:46 --> 00:02:49 to be zero. The op amp is a huge workhorse 30 00:02:49 --> 00:02:53 of the analog industry. You will see based both on what 31 00:02:53 --> 00:02:57 you've done on Tuesday and Wednesday but also today that 32 00:02:57 --> 00:03:03 it's very, very simple to build circuits using the op amp. 33 00:03:03 --> 00:03:07 When you use the amplifier, you don't have to worry about 34 00:03:07 --> 00:03:11 things like nonlinear analysis. You don't have to worry about 35 00:03:11 --> 00:03:16 am I really meeting the criteria for saturation limits and so on? 36 00:03:16 --> 00:03:20 To some extent you have to think about that with the op 37 00:03:20 --> 00:03:24 amp, too, because if the output hits the positive rail or 38 00:03:24 --> 00:03:30 negative rail it isn't going to behave like you expect it to. 39 00:03:30 --> 00:03:33 But fundamentally with this primitive model, 40 00:03:33 --> 00:03:37 this idea model it becomes really simple to build circuits 41 00:03:37 --> 00:03:41 with the op amp. Therefore it has become a key 42 00:03:41 --> 00:03:45 building block for circuits. When circuit designers build 43 00:03:45 --> 00:03:50 analog circuits very often their primitive building blocks are 44 00:03:50 --> 00:03:53 really an amplifier of this sort, an op amp, 45 00:03:53 --> 00:03:58 resistors, capacitors and some of our other primitive building 46 00:03:58 --> 00:04:01 elements. If you look at the course notes 47 00:04:01 --> 00:04:05 the readings are -- There are a bunch of examples 48 00:04:05 --> 00:04:09 solved in Chapter 16. And you will see that using the 49 00:04:09 --> 00:04:13 op amp it is indeed possible to build current sources that look 50 00:04:13 --> 00:04:15 like more or less ideal current sources. 51 00:04:15 --> 00:04:18 It is also possible to build voltage sources and so on. 52 00:04:18 --> 00:04:22 It is an incredibly neat building block using which you 53 00:04:22 --> 00:04:25 can do all kinds of cool stuff. 54 00:04:25 --> 00:04:33 55 00:04:33 --> 00:04:38 In this course you will see a whole bunch of example circuits 56 00:04:38 --> 00:04:43 using the op amp. In today's lecture you will see 57 00:04:43 --> 00:04:48 things like a subtractor. You will also see integrators 58 00:04:48 --> 00:04:53 and a differentiator. And then in your lab, 59 00:04:53 --> 00:04:58 lab four, you will build a really fun mixed signal circuit 60 00:04:58 --> 00:05:04 involving both digital and analog components. 61 00:05:04 --> 00:05:09 And you will build what is called a digital to an analog 62 00:05:09 --> 00:05:14 converter using the op amp. And of course I can build all 63 00:05:14 --> 00:05:19 our good-old amplifiers and circuits of that sort. 64 00:05:19 --> 00:05:24 In a later lecture you will also see how we can build 65 00:05:24 --> 00:05:30 filters using an op amp. This is going to be using the 66 00:05:30 --> 00:05:33 knowledge you learn in terms of connecting resistors, 67 00:05:33 --> 00:05:37 capacitors and inductors together and doing a frequency 68 00:05:37 --> 00:05:40 domain analysis, well we can throw the op amp in 69 00:05:40 --> 00:05:42 there and build filters, too. 70 00:05:42 --> 00:05:46 This is just to give you a preview of upcoming attractions. 71 00:05:46 --> 00:05:50 For today I am going to focus on these circuits. 72 00:05:50 --> 00:05:53 I won't be covering any new theory or any new set of 73 00:05:53 --> 00:05:58 foundations but pretty much take the simple properties that I 74 00:05:58 --> 00:06:02 have explained to you about the op amp. 75 00:06:02 --> 00:06:07 And using those simple properties very quickly build up 76 00:06:07 --> 00:06:13 a bunch of circuits that you can use to analyze signals in a 77 00:06:13 --> 00:06:17 variety of ways. Let's start with the following 78 00:06:17 --> 00:06:21 circuit. With op amps I start with this 79 00:06:21 --> 00:06:25 little guy. And what I am going to do is 80 00:06:25 --> 00:06:30 use two voltage sources, v1, and this is a resistor, 81 00:06:30 --> 00:06:34 not an inductor. And value R1, 82 00:06:34 --> 00:06:38 value R2. So, I have a voltage connected 83 00:06:38 --> 00:06:42 by a divider, voltage divider to the plus 84 00:06:42 --> 00:06:46 input. And I am going to provide some 85 00:06:46 --> 00:06:50 negative feedback in the following way. 86 00:06:50 --> 00:06:56 This is going to be R2, the same as this one here, 87 00:06:56 --> 00:07:01 a resistor R1. And then a voltage source v2 88 00:07:01 --> 00:07:05 that I connect out here. So notice that- Oh, 89 00:07:05 --> 00:07:09 and I take the output vOUT out here. 90 00:07:09 --> 00:07:13 And that vOUT of course is with respect to ground, 91 00:07:13 --> 00:07:18 and R2, v1 and v2 are also connected to ground. 92 00:07:18 --> 00:07:22 What I am going to do is analyze the circuit it two 93 00:07:22 --> 00:07:26 different ways, and as I analyze it describe 94 00:07:26 --> 00:07:32 some other interesting properties to you. 95 00:07:32 --> 00:07:35 In the last lecture the technique I used to analyze op 96 00:07:35 --> 00:07:39 amps was one in which I replaced the op amp with its ideal model 97 00:07:39 --> 00:07:43 involving a dependent source and so on with a large gain A and 98 00:07:43 --> 00:07:46 showed that. I wrote the expression and then 99 00:07:46 --> 00:07:50 I let A increase to infinity to the limits and got an expression 100 00:07:50 --> 00:07:53 that was independent of A. And then in recitation 101 00:07:53 --> 00:07:57 yesterday you would have covered another technique which makes it 102 00:07:57 --> 00:08:04 much simpler to analyze op amps. Let me very quickly review that 103 00:08:04 --> 00:08:07 method. We fondly call that technique, 104 00:08:07 --> 00:08:13 there is no formal name for it, but we fondly call that v plus 105 00:08:13 --> 00:08:17 more or less equal to v minus method. 106 00:08:17 --> 00:08:23 This is also variously called the virtual ground method and so 107 00:08:23 --> 00:08:29 on, but we shall call it the v plus more or less equal to v 108 00:08:29 --> 00:08:33 minus method. The insight here is that 109 00:08:33 --> 00:08:37 whenever I use the op amp in a way in which I am giving it 110 00:08:37 --> 00:08:41 negative feedback, so I am feeding some portion of 111 00:08:41 --> 00:08:43 the output to its negative input. 112 00:08:43 --> 00:08:45 I am giving it negative feedback. 113 00:08:45 --> 00:08:49 That's one property. Second property is that my 114 00:08:49 --> 00:08:52 inputs, v1 and v2, and my resistance values are 115 00:08:52 --> 00:08:55 chosen such that the output is not in saturation. 116 00:08:55 --> 00:09:01 So, the op amp is not at the plus VS rail or minus VS rail. 117 00:09:01 --> 00:09:05 Rather it's somewhere in the middle in its active region. 118 00:09:05 --> 00:09:10 When that happens we claim that the v minus and v plus for the 119 00:09:10 --> 00:09:16 op amp are more or less equal. And to give you some intuition 120 00:09:16 --> 00:09:20 as to why that is so, let's say the output is 6 volts 121 00:09:20 --> 00:09:24 and my supply is plus/minus 12. This is 6 volts and the 122 00:09:24 --> 00:09:30 amplifier is a gain of a million, ten to the six. 123 00:09:30 --> 00:09:33 To sustain 6 volts at the output all I need is a 124 00:09:33 --> 00:09:38 difference of 6 microvolts here. Six divided by ten to the six 125 00:09:38 --> 00:09:42 is the difference between v plus and v minus. 126 00:09:42 --> 00:09:44 It's very, very, very small. 127 00:09:44 --> 00:09:49 It's so small as to make v plus more or less equal to v minus. 128 00:09:49 --> 00:09:54 All it takes is a very small differential voltage here to 129 00:09:54 --> 00:09:59 give you 6 volts at the output. The key thing to observe is 130 00:09:59 --> 00:10:03 under negative feedback, when the op amp is not in 131 00:10:03 --> 00:10:07 saturation the property that v plus equals v minus holds. 132 00:10:07 --> 00:10:11 And the way it works is that it's not that it's a magical 133 00:10:11 --> 00:10:14 property. It is simply that when I apply 134 00:10:14 --> 00:10:18 negative feedback the negative feedback is such that it will 135 00:10:18 --> 00:10:23 force this v minus node here to be at more or less the same 136 00:10:23 --> 00:10:26 voltage as v plus. Remember the when in doubt 137 00:10:26 --> 00:10:30 simply go back and think about the anti lock brakes example we 138 00:10:30 --> 00:10:35 did last time. For example if v plus increases 139 00:10:35 --> 00:10:39 the output will increase and so will the voltage here and tend 140 00:10:39 --> 00:10:42 to make these two equal. What we can do, 141 00:10:42 --> 00:10:46 being rather tricky here, what we'll do is say look, 142 00:10:46 --> 00:10:50 if we know for a fact that under negative feedback the op 143 00:10:50 --> 00:10:54 amp is going to engineer these two node voltages to be more or 144 00:10:54 --> 00:10:58 less equal then why don't I just use that fact to begin with and 145 00:10:58 --> 00:11:03 analyze my circuit assuming that it's true. 146 00:11:03 --> 00:11:06 This is just a bit of inverted logic here that says look, 147 00:11:06 --> 00:11:08 the circuit is going to make that happen. 148 00:11:08 --> 00:11:11 If the circuit is going to make that happen to analyze the 149 00:11:11 --> 00:11:14 circuit in its steady state, why don't I just go ahead and 150 00:11:14 --> 00:11:17 assume that to begin with? This again goes back to us 151 00:11:17 --> 00:11:21 wanting to be engineers here and do whatever is simply and find 152 00:11:21 --> 00:11:23 the simplest possible way of getting some place. 153 00:11:23 --> 00:11:26 I want to use that method, the v plus equals v minus 154 00:11:26 --> 00:11:30 method. Let me just first write down 155 00:11:30 --> 00:11:36 some values that I know about. I know that v plus is simply a 156 00:11:36 --> 00:11:42 voltage divider relation here. That's v1 times R2 divided by 157 00:11:42 --> 00:11:45 R1 plus R2. And by the v plus equals v 158 00:11:45 --> 00:11:51 minus method I know that this is going to be equal to v minus. 159 00:11:51 --> 00:11:57 And this is going to be true because I am giving you negative 160 00:11:57 --> 00:12:02 feedback here. And we are going to engineer 161 00:12:02 --> 00:12:06 the values of R1, R2, v1 and v2 such that the op 162 00:12:06 --> 00:12:09 amp is not in saturation. So, we know that. 163 00:12:09 --> 00:12:14 The next thing that we know, let's say this is a current i. 164 00:12:14 --> 00:12:19 This current i flows here. Know that there is no current 165 00:12:19 --> 00:12:23 going in here. Op amp has an infinite input 166 00:12:23 --> 00:12:26 resistance so there is nothing going in there. 167 00:12:26 --> 00:12:31 There is no current going in there. 168 00:12:31 --> 00:12:35 If there is no current going in here, what must happen to i? 169 00:12:35 --> 00:12:39 Remember, from the foundations of the universe Maxwell's 170 00:12:39 --> 00:12:42 equations and therefore KVL and KCL hold. 171 00:12:42 --> 00:12:45 KVL and KCL simply come straight from nature. 172 00:12:45 --> 00:12:47 You and I cannot mess with that. 173 00:12:47 --> 00:12:50 Bad things happen to you if you do. 174 00:12:50 --> 00:12:52 So, nature, Maxwell's equations, KVL, 175 00:12:52 --> 00:12:54 KCL. It's simply nature. 176 00:12:54 --> 00:12:59 So, KCL applies here. Current comes in here. 177 00:12:59 --> 00:13:01 Nothing goes there. Don't argue. 178 00:13:01 --> 00:13:04 The current has to go here, period. 179 00:13:04 --> 00:13:08 No if, ands or buts. There is i coming in here, 180 00:13:08 --> 00:13:12 nothing goes there, so that current must flow here. 181 00:13:12 --> 00:13:16 It has no choice. It's from basic nature. 182 00:13:16 --> 00:13:21 I can write down what my current i is going to look like. 183 00:13:21 --> 00:13:24 What is i going to look like? Well, I know v2, 184 00:13:24 --> 00:13:30 I know v minus. v minus is the same as v plus. 185 00:13:30 --> 00:13:33 And v plus is the i expression given here. 186 00:13:33 --> 00:13:38 So, I can write i as v2 minus v minus divided by R1. 187 00:13:38 --> 00:13:44 Let me keep track of those two and then go ahead and compute 188 00:13:44 --> 00:13:47 vOUT. So, my goal in life is compute 189 00:13:47 --> 00:13:52 vOUT as a function of the two input voltages v1 and v2. 190 00:13:52 --> 00:13:58 And just for kicks I have gone ahead and computed some of the 191 00:13:58 --> 00:14:03 intermediate node voltages and currents. 192 00:14:03 --> 00:14:08 How do I write vOUT? What is vOUT? 193 00:14:08 --> 00:14:12 vOUT is simply v minus from KVL. 194 00:14:12 --> 00:14:21 vOUT is simply v minus minus the drop across this resistor. 195 00:14:21 --> 00:14:30 So, the drop across that resistor is simply iR2. 196 00:14:30 --> 00:14:33 From good-old KVL from the first lecture, 197 00:14:33 --> 00:14:37 a voltage minus the drop across the resistor is equal to vOUT. 198 00:14:37 --> 00:14:40 Therefore it's simply v minus minus iR2. 199 00:14:40 --> 00:14:45 One thing to be very cautious about, I will tell you right 200 00:14:45 --> 00:14:49 now, is that the output here relates to the inversion of the 201 00:14:49 --> 00:14:54 voltage across this resistor R2. Be very, very careful in that 202 00:14:54 --> 00:14:59 if I have a voltage across this resistor here that impacts vOUT 203 00:14:59 --> 00:15:03 with a minus sign attached to it. 204 00:15:03 --> 00:15:08 Notice that iR2 is the voltage across R2 and vOUT relates to 205 00:15:08 --> 00:15:12 the negative of that. Be very cautious. 206 00:15:12 --> 00:15:18 That's one of the commonest silly mistakes I have seen 207 00:15:18 --> 00:15:22 people make in solving problems like this. 208 00:15:22 --> 00:15:27 Let's go ahead. I know v minus and I don't know 209 00:15:27 --> 00:15:29 i. Let me substitute for i for 210 00:15:29 --> 00:15:37 now, and that is v2 minus v minus divided by R1 times R2. 211 00:15:37 --> 00:15:43 Let me go ahead and collect all the v minuses. 212 00:15:43 --> 00:15:51 v minus, I get a one here, minus minus becomes a plus, 213 00:15:51 --> 00:15:56 and so I get R2 divided by R1 out there. 214 00:15:56 --> 00:16:03 And then I minus v2 R2 divided by R1. 215 00:16:03 --> 00:16:08 That is vOUT. Now let me go ahead and 216 00:16:08 --> 00:16:15 substitute for v minus. And that is simply v1 R2 217 00:16:15 --> 00:16:20 divided by R1 plus R2. That is v minus. 218 00:16:20 --> 00:16:27 And this character here is simplified to be R1, 219 00:16:27 --> 00:16:34 R1 plus R2 minus v2 R2 divided by R1. 220 00:16:34 --> 00:16:39 What do we get? I cancel these two suckers out 221 00:16:39 --> 00:16:46 and what I end up with is v1 R2 divided by R1 minus v2 R2 222 00:16:46 --> 00:16:51 divided by R1, which is simply R2/R1(v1-v2). 223 00:16:51 --> 00:16:58 What is interesting here is that what I have ended up 224 00:16:58 --> 00:17:04 building is a very primitive subtractor. 225 00:17:04 --> 00:17:08 So, my output relates to v1 minus v2 multiplied by the 226 00:17:08 --> 00:17:13 constant factor given by R2 divided by R1. 227 00:17:13 --> 00:17:19 228 00:17:19 --> 00:17:22 Again, as I pointed out to you at the beginning of this 229 00:17:22 --> 00:17:25 lecture, no knew foundations today, no new theories, 230 00:17:25 --> 00:17:26 no new disciplines, no new laws. 231 00:17:26 --> 00:17:30 We are just going to take what you have learned -- 232 00:17:30 --> 00:17:32 Three simple things, infinite gain, 233 00:17:32 --> 00:17:36 infinite input resistance, zero output resistance, 234 00:17:36 --> 00:17:39 plus this new thing v plus equals v minus. 235 00:17:39 --> 00:17:44 And just being armed with those four principles we are just 236 00:17:44 --> 00:17:48 going to charge ahead and analyze a bunch of circuits. 237 00:17:48 --> 00:17:52 It is purely intellectual and pure applications today. 238 00:17:52 --> 00:17:56 This is one way of doing it. There is another way of solving 239 00:17:56 --> 00:18:00 it. We can solve the circuit. 240 00:18:00 --> 00:18:04 Remember, whenever you see a linear circuit and you see two 241 00:18:04 --> 00:18:09 sources or three sources, just think superposition, 242 00:18:09 --> 00:18:12 right? You see a linear circuit and 243 00:18:12 --> 00:18:15 two or three sources, think superposition. 244 00:18:15 --> 00:18:19 We should be able to apply superposition to this. 245 00:18:19 --> 00:18:23 The op amp is simply another building block. 246 00:18:23 --> 00:18:27 It's a linear circuit. So, let's see if we get the 247 00:18:27 --> 00:18:33 same answer. Let's try to solve the circuit 248 00:18:33 --> 00:18:38 using superposition and see if we get the same answer. 249 00:18:38 --> 00:18:43 To do superposition what I am going to do is build two 250 00:18:43 --> 00:18:48 subcircuits. One subcircuit in which v1 is 251 00:18:48 --> 00:18:52 zero, and that subcircuit looks like this. 252 00:18:52 --> 00:18:58 If I set v1 to be zero then I get R1 parallel R2 going to 253 00:18:58 --> 00:19:03 ground. So, if v1 is set to zero then 254 00:19:03 --> 00:19:09 R1 goes to ground. And I get R1 parallel R2 here. 255 00:19:09 --> 00:19:13 And of course I have v2 as before. 256 00:19:13 --> 00:19:16 And this was R1, this was R2, 257 00:19:16 --> 00:19:21 and let me call that vOUT1. Oh, I'm sorry. 258 00:19:21 --> 00:19:28 Let me call it vOUT2 corresponding to that component 259 00:19:28 --> 00:19:35 of the output that relates to v2 acting alone. 260 00:19:35 --> 00:19:38 Remember superposition? Build two subcircuits, 261 00:19:38 --> 00:19:43 one that depends on v2 and another one that depends on v1. 262 00:19:43 --> 00:19:46 Let's do the second one, too. 263 00:19:46 --> 00:19:51 Second one is v2 going to zero. Here is my little op amp. 264 00:19:51 --> 00:19:56 And what I will do is simply flip the op amp just to see if 265 00:19:56 --> 00:20:01 you can identify some interesting patterns. 266 00:20:01 --> 00:20:07 Just flip the op amp around. And this is v1 as before. 267 00:20:07 --> 00:20:15 And recall that v1 was going to the plus node through a resistor 268 00:20:15 --> 00:20:19 R1. And then I had a R2 to ground. 269 00:20:19 --> 00:20:23 And then let me short v2 to ground. 270 00:20:23 --> 00:20:30 And when I short v2 to ground what happens? 271 00:20:30 --> 00:20:35 When I short v2 to ground what happens is that the tail of R1 272 00:20:35 --> 00:20:40 here goes to ground. And so it is as if the output 273 00:20:40 --> 00:20:44 is connected to the node v minus through a resistor, 274 00:20:44 --> 00:20:50 so it as if the output v R2 is connected to the minus input 275 00:20:50 --> 00:20:54 through a resistor. We will draw it like this. 276 00:20:54 --> 00:20:58 And the minus input goes through a resistor R1, 277 00:20:58 --> 00:21:02 to ground. If you thought that patterns 278 00:21:02 --> 00:21:07 were important in the earlier part of the course doing voltage 279 00:21:07 --> 00:21:11 divider patterns and current divider patterns and amplifier 280 00:21:11 --> 00:21:14 pattern, the source follower pattern, op amps is all about 281 00:21:14 --> 00:21:17 patterns. You should remember two or 282 00:21:17 --> 00:21:20 three simple patterns and be able to write down the 283 00:21:20 --> 00:21:23 expression for those just by observation. 284 00:21:23 --> 00:21:27 So, this is one common pattern that you have seen before in the 285 00:21:27 --> 00:21:32 very first lecture. And I just wrote it down in 286 00:21:32 --> 00:21:35 that manner. Let me go ahead and solve this 287 00:21:35 --> 00:21:37 circuit. It turns out that this is also 288 00:21:37 --> 00:21:40 a pattern. I will analyze it today but in 289 00:21:40 --> 00:21:45 the future v2 going to this node through R1 and then R2 to the 290 00:21:45 --> 00:21:47 output. You have probably also seen 291 00:21:47 --> 00:21:52 this in your recitation. This one is called an inverting 292 00:21:52 --> 00:21:55 connection and this one here is called a non-inverting 293 00:21:55 --> 00:22:00 connection. Let's go ahead and do vOUT2. 294 00:22:00 --> 00:22:05 vOUT2 is simply given by, notice that since this is 295 00:22:05 --> 00:22:10 ground, no current flowing here, this voltage is zero. 296 00:22:10 --> 00:22:15 If this voltage is zero, this voltage is zero by the v 297 00:22:15 --> 00:22:19 plus equals v minus method. If this is zero, 298 00:22:19 --> 00:22:25 the current that goes through here is v2 divided by R1. 299 00:22:25 --> 00:22:31 And that same current must flow through the resistance R2 as 300 00:22:31 --> 00:22:35 well. If the current v2 divided by R1 301 00:22:35 --> 00:22:40 flows through this resistor, the drop across this resistor 302 00:22:40 --> 00:22:44 is simply given by, let me hide this for a second, 303 00:22:44 --> 00:22:48 is simply given by v2. So, v2 divided by R1 is the 304 00:22:48 --> 00:22:50 current here. This is zero. 305 00:22:50 --> 00:22:54 So, the drop across this resistor is v2 R1 multiplied by 306 00:22:54 --> 00:22:57 R2. That's a drop across this 307 00:22:57 --> 00:23:01 resistor. This voltage is simply zero 308 00:23:01 --> 00:23:03 minus a drop across the resistor. 309 00:23:03 --> 00:23:08 So, it's zero minus the drop across the resistor and that 310 00:23:08 --> 00:23:11 gives me v2. Again, remember this minus sign 311 00:23:11 --> 00:23:16 comes in when I want to convert this to get the output voltage 312 00:23:16 --> 00:23:20 from that. This is a very common pattern. 313 00:23:20 --> 00:23:24 It's called an inverting connection where the output is 314 00:23:24 --> 00:23:29 some factor of the input voltage and the factor is given by R2 315 00:23:29 --> 00:23:35 divided by R1. Let's go ahead and analyze this 316 00:23:35 --> 00:23:39 guy now. What is vOUT1 equal to? 317 00:23:39 --> 00:23:47 I should have called this vOUT1 because it relates to v1. 318 00:23:47 --> 00:23:50 vOUT1. There is a v plus here. 319 00:23:50 --> 00:23:58 From our first lecture I know that vOUT1 relates to v plus in 320 00:23:58 --> 00:24:04 the following way. I know that it is v plus times 321 00:24:04 --> 00:24:08 the sum of the resistances divided by R1. 322 00:24:08 --> 00:24:12 Based on the first lecture this is true. 323 00:24:12 --> 00:24:17 vOUT1 is simply an amplified version of v plus where the 324 00:24:17 --> 00:24:23 amplification factor is given by R1 plus R2 divided by R1. 325 00:24:23 --> 00:24:30 And I know v plus is simply a voltage divider action here. 326 00:24:30 --> 00:24:35 And I can take a simple voltage divider action here because the 327 00:24:35 --> 00:24:40 current going in is zero. Looking in here this is as if 328 00:24:40 --> 00:24:45 it's an infinite resistance, so it is as if the element 329 00:24:45 --> 00:24:50 simply does not exist. The voltage here is simply v1 330 00:24:50 --> 00:24:56 divided by R1 plus R2 multiplied by R2, our voltage divider 331 00:24:56 --> 00:24:59 pattern. So, I get v1 times R2 divided 332 00:24:59 --> 00:25:05 by R1 plus R2 times R1 plus R2 divided by R1. 333 00:25:05 --> 00:25:14 These two cancel out which gives me vOUT1 is simply v1 R2 334 00:25:14 --> 00:25:21 divided by R1. To get vOUT I add up the two. 335 00:25:21 --> 00:25:28 vOUT is vOUT1 plus vOUT2, which is my goal. 336 00:25:28 --> 00:25:37 And that is simply v1 R2 by R1 minus v2 R2 by R1. 337 00:25:37 --> 00:25:40 Thankfully what we have here is the same as here. 338 00:25:40 --> 00:25:45 Again, there is really nothing new that I am going to cover 339 00:25:45 --> 00:25:47 today. Simply apply, 340 00:25:47 --> 00:25:50 apply, apply, four simple principles. 341 00:25:50 --> 00:25:55 Here I have used superposition and I am showing you a circuit. 342 00:25:55 --> 00:26:00 So, it turns out with op amps you should really remember that 343 00:26:00 --> 00:26:04 pattern. You will see it again and again 344 00:26:04 --> 00:26:07 and again. And each time you see it, 345 00:26:07 --> 00:26:11 it will save you six minutes of having to solve the circuit 346 00:26:11 --> 00:26:16 without knowing the pattern. So, remember this pattern. 347 00:26:16 --> 00:26:20 You can pick up another three or four minutes by remembering 348 00:26:20 --> 00:26:24 this pattern here. This pattern is simply v2 R2 349 00:26:24 --> 00:26:28 divided by R1. Imprint those two patterns into 350 00:26:28 --> 00:26:32 your brains. OK, so those are a couple of 351 00:26:32 --> 00:26:35 simple circuits using the op amp. 352 00:26:35 --> 00:26:38 We built a subtractor. The next step, 353 00:26:38 --> 00:26:42 let's go ahead and try to build an integrator. 354 00:26:42 --> 00:26:47 Using this little building block we can go ahead and try to 355 00:26:47 --> 00:26:51 build a bunch of circuits. We can build filters, 356 00:26:51 --> 00:26:55 A to D converters and so on. Let's build an integrator. 357 00:26:55 --> 00:27:00 Abstractly I need to build this box. 358 00:27:00 --> 00:27:04 Which when fed a vI, I want that box to integrate 359 00:27:04 --> 00:27:08 and give me a vO which is vI integrated over time. 360 00:27:08 --> 00:27:13 That is what I want to build. How do I go about building it? 361 00:27:13 --> 00:27:19 What I would like to do next is give you some flavor for design. 362 00:27:19 --> 00:27:23 How do you go about designing things with an op amp? 363 00:27:23 --> 00:27:28 Knowing that you do not know the pattern for this yet, 364 00:27:28 --> 00:27:33 how do you go about designing things? 365 00:27:33 --> 00:27:36 Well, let's start with the following intuition. 366 00:27:36 --> 00:27:41 The intuition that I begin with is that if I have a current i, 367 00:27:41 --> 00:27:46 and remember that capacitors and inductors related to, 368 00:27:46 --> 00:27:51 you saw differentiation and integration happening when we 369 00:27:51 --> 00:27:53 dealt with capacitors and inductors. 370 00:27:53 --> 00:28:00 So, I think we have to invoke a capacitor here or an inductor. 371 00:28:00 --> 00:28:04 In this example I invoke a capacitor. 372 00:28:04 --> 00:28:10 Notice that if I stick a capacitor in here this current 373 00:28:10 --> 00:28:16 is i, capacitance C, then my voltage vO is given by 374 00:28:16 --> 00:28:20 what? Voltage is simply the integral 375 00:28:20 --> 00:28:28 of the current flowing through it or vice versa i is C dv/dt. 376 00:28:28 --> 00:28:36 If i is C dv/dt then v is simply one by C integral. 377 00:28:36 --> 00:28:44 If I can pass the current through a capacitor then the 378 00:28:44 --> 00:28:52 voltage across the capacitor must be a current. 379 00:28:52 --> 00:29:00 Notice then that vO is related to i dt. 380 00:29:00 --> 00:29:02 I have some multiplying constants and so on, 381 00:29:02 --> 00:29:06 but fundamentally what I have found is if I can stick a 382 00:29:06 --> 00:29:11 current through a capacitor then the voltage across the capacitor 383 00:29:11 --> 00:29:13 relates to the integral of the current. 384 00:29:13 --> 00:29:17 OK, that's interesting. So, I have an integral in 385 00:29:17 --> 00:29:18 there. But I have a current. 386 00:29:18 --> 00:29:21 Notice my goal was to integrate a voltage. 387 00:29:21 --> 00:29:25 What I figured out how to do was if I can turn that voltage 388 00:29:25 --> 00:29:31 into a current -- If I can turn that voltage into 389 00:29:31 --> 00:29:38 a proportional current and then pump that current through a 390 00:29:38 --> 00:29:44 capacitor I will get the integration that I want. 391 00:29:44 --> 00:29:50 How do I convert my vI to i? How do I do that? 392 00:29:50 --> 00:29:55 Well, let's take a stab at it. Here is my vI. 393 00:29:55 --> 00:30:02 Let's take the resistor R. And remember I need to stick 394 00:30:02 --> 00:30:06 the capacitor here. I have some current I here. 395 00:30:06 --> 00:30:09 I don't know what the current is yet. 396 00:30:09 --> 00:30:13 And I stick a voltage here. And what I am trying to do is 397 00:30:13 --> 00:30:18 trying to see if I stick a voltage and a resistance in 398 00:30:18 --> 00:30:23 series then there is some relationship between the current 399 00:30:23 --> 00:30:27 and this voltage. Recall that I am trying to make 400 00:30:27 --> 00:30:33 this current be directly proportional to the voltage vI. 401 00:30:33 --> 00:30:38 But it turns out that i here is not equal to vI divided by R. 402 00:30:38 --> 00:30:42 If i was vI divided by R somehow, I am done. 403 00:30:42 --> 00:30:46 If i was vI divided by R, by some magic, 404 00:30:46 --> 00:30:50 then I have converted my voltage to a current, 405 00:30:50 --> 00:30:56 I feed that current through my capacitor and vO is my integral 406 00:30:56 --> 00:31:01 that I am looking for. But unfortunately i is not 407 00:31:01 --> 00:31:04 equal to vI divided by R. You know that. 408 00:31:04 --> 00:31:09 i relates to vI minus the capacitor voltage divided by R. 409 00:31:09 --> 00:31:14 So, i is not simply vI divided by R for all time but i is 410 00:31:14 --> 00:31:19 really vI minus the capacitor voltage divided by R. 411 00:31:19 --> 00:31:22 And, in fact, when we did RC circuits you 412 00:31:22 --> 00:31:28 wrote this equation to represent the dynamics of the circuit, 413 00:31:28 --> 00:31:34 RC dvO by dt plus vO equals vI. We wrote down this circuit for 414 00:31:34 --> 00:31:39 a first order RC, wrote this equation for a first 415 00:31:39 --> 00:31:43 order RC circuit. Now, it does turn out, 416 00:31:43 --> 00:31:48 to wrap up on this wild goose chase that we went on, 417 00:31:48 --> 00:31:53 it does turn out that if this term here is much bigger than 418 00:31:53 --> 00:31:57 that term. If this term is much bigger 419 00:31:57 --> 00:32:03 than that term then I can ignore that term and write down RC dvO 420 00:32:03 --> 00:32:10 by dt more or less equal to vI. If that were true, 421 00:32:10 --> 00:32:15 this would be true, and then vO would be more or 422 00:32:15 --> 00:32:20 less equal to one by RC integral of vI dt. 423 00:32:20 --> 00:32:27 Again, if this were true. If this were true for all time 424 00:32:27 --> 00:32:32 then vO would be integral of vI dt. 425 00:32:32 --> 00:32:35 Again, remember this is all a wild goose chase. 426 00:32:35 --> 00:32:39 Just write down WGC there just so you don't get confused. 427 00:32:39 --> 00:32:43 I am on this wild goose hunt here trying to find a way to get 428 00:32:43 --> 00:32:48 a current from a voltage which I can then feed into a capacitor. 429 00:32:48 --> 00:32:52 This was one thing I knew, but this was not what I want. 430 00:32:52 --> 00:32:56 But it does turn out to be what I want when vO is very, 431 00:32:56 --> 00:32:58 very small. So, I see some glimmer of hope 432 00:32:58 --> 00:33:03 but not quite. It turns that in R and C, 433 00:33:03 --> 00:33:08 if I make R and C very, very big, if I have a huge time 434 00:33:08 --> 00:33:12 constant, with a huge time constant the voltage vO looks 435 00:33:12 --> 00:33:17 like an integral of vI, but only when I have a very 436 00:33:17 --> 00:33:21 huge time constant. So, I give up on that track. 437 00:33:21 --> 00:33:25 Instead I try something else. 438 00:33:25 --> 00:33:34 439 00:33:34 --> 00:33:38 Another try. I would like you to notice if 440 00:33:38 --> 00:33:42 you take your op amp, here is your op amp, 441 00:33:42 --> 00:33:48 if you take this op amp and you stick the positive terminal to 442 00:33:48 --> 00:33:53 ground, under reasonable feedback, under reasonable 443 00:33:53 --> 00:34:00 negative feedback what do you notice about the current? 444 00:34:00 --> 00:34:04 If I had a current i flowing here what did you notice? 445 00:34:04 --> 00:34:09 Look at this picture. I had a current i flowing in 446 00:34:09 --> 00:34:14 here, v2 divided by R1. And because this resistance was 447 00:34:14 --> 00:34:19 infinite all the current went through the upper terminal. 448 00:34:19 --> 00:34:24 So, this is zero volts. And by the v plus equals v 449 00:34:24 --> 00:34:30 minus method this is also more or less equal to zero. 450 00:34:30 --> 00:34:35 And I have a current i flowing in here, nothing goes here, 451 00:34:35 --> 00:34:37 so then the i must flow up there. 452 00:34:37 --> 00:34:42 So, all I am doing here is causing a reflection of the 453 00:34:42 --> 00:34:48 current from this grounded node. My current is being reflected 454 00:34:48 --> 00:34:53 into, or deflected if you feel like it, the upper edge here 455 00:34:53 --> 00:34:56 after coming in through this edge. 456 00:34:56 --> 00:35:00 That is interesting. We are just one step away from 457 00:35:00 --> 00:35:02 the key insight. 458 00:35:02 --> 00:35:10 459 00:35:10 --> 00:35:14 I have an i coming in here, an i going out there. 460 00:35:14 --> 00:35:16 Notice that, as I said before, 461 00:35:16 --> 00:35:21 this is zero volts. How do I get my voltage vI to 462 00:35:21 --> 00:35:25 look like a current, to become proportional to a 463 00:35:25 --> 00:35:27 current? It is simple now. 464 00:35:27 --> 00:35:34 All I do is put a voltage vI and put a resistor R out there. 465 00:35:34 --> 00:35:36 If I do that, and since this is zero, 466 00:35:36 --> 00:35:39 the current i is given by vI divided by R. 467 00:35:39 --> 00:35:42 I have gotten to where I want to be. 468 00:35:42 --> 00:35:46 So, by using an op amp and using the fact that the minus 469 00:35:46 --> 00:35:51 node here, v minus is at the same potential as v plus when 470 00:35:51 --> 00:35:55 there is negative feedback then I can stick a resistor here. 471 00:35:55 --> 00:35:59 And because this is zero the current here is simply vI 472 00:35:59 --> 00:36:04 divided by R. I have gotten to the first 473 00:36:04 --> 00:36:07 place. Now all I need to do is simply 474 00:36:07 --> 00:36:13 pump this current through a capacitor and I get the integral 475 00:36:13 --> 00:36:18 of the, the voltage becomes an integral of the current. 476 00:36:18 --> 00:36:22 That is easy. I stick my capacitor here and I 477 00:36:22 --> 00:36:27 get my answer out there as vO. Notice that when I do this, 478 00:36:27 --> 00:36:32 let's say this is plus/minus VC. 479 00:36:32 --> 00:36:34 This is zero. So, vO is minus VC. 480 00:36:34 --> 00:36:38 Again, I will keep emphasizing it maybe 17 times throughout 481 00:36:38 --> 00:36:43 this course that if this is zero then the output here is related 482 00:36:43 --> 00:36:47 to the negative of this voltage, common, common, 483 00:36:47 --> 00:36:50 common mistake. I will be very upset after 484 00:36:50 --> 00:36:54 doing all this if I see this mistake happen in any of the 485 00:36:54 --> 00:36:57 future homeworks or finals or whatever. 486 00:36:57 --> 00:37:05 This should not happen. So, vO is a minus sign here VC. 487 00:37:05 --> 00:37:15 And I know that if I have a current i through a capacitor 488 00:37:15 --> 00:37:22 what is VC? If I have current i through a 489 00:37:22 --> 00:37:29 capacitor than this is simply t i dt. 490 00:37:29 --> 00:37:36 And i by design is -- So, I have my integrator. 491 00:37:36 --> 00:37:40 It is a two-step process. I stuck a resistor here, 492 00:37:40 --> 00:37:44 so the current became equal to vI divided by R. 493 00:37:44 --> 00:37:49 Then I took that current and pumped it through a capacitor 494 00:37:49 --> 00:37:54 through this terminal here, and the voltage across the 495 00:37:54 --> 00:38:00 capacitor for a current i is given by this expression. 496 00:38:00 --> 00:38:04 This is Capacitors 101. OK Capacitors 101 says that the 497 00:38:04 --> 00:38:09 voltage across the capacitor is simply one by C integral i dt. 498 00:38:09 --> 00:38:14 Another way of looking at it is the voltage across the capacitor 499 00:38:14 --> 00:38:17 is C, I'm sorry, the current through a capacitor 500 00:38:17 --> 00:38:20 is C dv/dt. This is simply the integral 501 00:38:20 --> 00:38:24 form of that equation. And I am done with my 502 00:38:24 --> 00:38:27 integrator. So, this is another very common 503 00:38:27 --> 00:38:31 building block. Remember this. 504 00:38:31 --> 00:38:36 Most of the circuits we will be seeing with op amps simply 505 00:38:36 --> 00:38:39 involve something here and some there. 506 00:38:39 --> 00:38:43 And the output in this inverting connection is the 507 00:38:43 --> 00:38:47 output times, if it is a resistance it is 508 00:38:47 --> 00:38:51 simply R2 divided by R1, if it's a capacitor I get the 509 00:38:51 --> 00:38:56 integral form looking like this. Yes. 510 00:38:56 --> 00:39:01 511 00:39:01 --> 00:39:05 Can someone tell me where the negative sign went? 512 00:39:05 --> 00:39:10 The blackboard ate it up. Good catch. 513 00:39:10 --> 00:39:27 514 00:39:27 --> 00:39:30 After all that lecture about watching the negative sign. 515 00:39:30 --> 00:39:34 After this little bit of faux pas here, now I will be doubly 516 00:39:34 --> 00:39:36 mad if you guys make that mistake. 517 00:39:36 --> 00:39:38 All right. Now that we have built the 518 00:39:38 --> 00:39:42 integrator, I could give this out as a homework problem. 519 00:39:42 --> 00:39:45 And you should be able to design a differentiator based on 520 00:39:45 --> 00:39:49 what you've learned here. You now have the tools to go 521 00:39:49 --> 00:39:52 and do some design like this, but we don't have any more 522 00:39:52 --> 00:39:56 homeworks left so I guess I will go ahead and solve this for you 523 00:39:56 --> 00:40:00 right here and do the design for you. 524 00:40:00 --> 00:40:06 The building block that we need looks like this, 525 00:40:06 --> 00:40:11 d/dt here. Let me take a vI and stick a vI 526 00:40:11 --> 00:40:16 in there. That's what I want to build. 527 00:40:16 --> 00:40:23 And what I built here is that different integrator box. 528 00:40:23 --> 00:40:33 And what I would like to do now is build a differentiator box. 529 00:40:33 --> 00:40:37 How do I go about doing it? I will go really slow here so 530 00:40:37 --> 00:40:42 you will have some time to think about it for yourselves and see 531 00:40:42 --> 00:40:46 if you folks are crack op amp circuit designers already, 532 00:40:46 --> 00:40:49 if you have the right instincts here. 533 00:40:49 --> 00:40:53 Again, when you see differentiation integration 534 00:40:53 --> 00:40:57 think capacitors or inductors, it doesn't matter. 535 00:40:57 --> 00:41:00 In fact, as a homework exercise, you may want to go 536 00:41:00 --> 00:41:07 back and see how you can get a similar effect using inductors. 537 00:41:07 --> 00:41:11 Can you play with inductors and get a similar effect? 538 00:41:11 --> 00:41:15 So, inductors are devices that are a dual of the capacitor. 539 00:41:15 --> 00:41:20 Whatever we will do with capacitors, there must be a 540 00:41:20 --> 00:41:22 corresponding way with inductors. 541 00:41:22 --> 00:41:25 You can try it out in your spare time. 542 00:41:25 --> 00:41:33 Let's go back to this one here. I will stick with the capacitor 543 00:41:33 --> 00:41:40 way of looking at things. I need a differentiation now. 544 00:41:40 --> 00:41:45 Remember this. If I have a vI and I stick this 545 00:41:45 --> 00:41:51 across a capacitor, I have a current C and some 546 00:41:51 --> 00:42:00 voltage vc across the capacitor, what does i relate to? 547 00:42:00 --> 00:42:09 i is simply C dv/dt and vc in this case is simply C dvI/dt. 548 00:42:09 --> 00:42:18 If I can stick a voltage across a capacitor, if my input voltage 549 00:42:18 --> 00:42:28 is stuck across a capacitor then the resulting current relates to 550 00:42:28 --> 00:42:33 dvI/dt. Here we have the opposite 551 00:42:33 --> 00:42:36 problem. By doing this simple trick, 552 00:42:36 --> 00:42:41 I can obtain a current that has the right form. 553 00:42:41 --> 00:42:46 Now what I need to do is somehow convert that current 554 00:42:46 --> 00:42:51 into a voltage because the abstraction that I need is a 555 00:42:51 --> 00:42:54 voltage to voltage. The next step, 556 00:42:54 --> 00:42:59 what I need to do is somehow convert a current to a voltage. 557 00:42:59 --> 00:43:07 How do I go about doing that? Again, remember for the op amp, 558 00:43:07 --> 00:43:14 if I have a current i flowing here then by the reflection 559 00:43:14 --> 00:43:22 property i gets pushed up into this edge, provided that the 560 00:43:22 --> 00:43:30 whole circuit is working with descent negative feedback. 561 00:43:30 --> 00:43:35 Given this trick what I can do is say look, suppose I did this. 562 00:43:35 --> 00:43:40 Remember, my goal here is how do I convert a current to a 563 00:43:40 --> 00:43:43 voltage? I have a current i coming in 564 00:43:43 --> 00:43:48 here, and I can turn that into a voltage because I know the 565 00:43:48 --> 00:43:54 current must come out here, I know this current must come 566 00:43:54 --> 00:43:57 out there. All I have to do is stick a 567 00:43:57 --> 00:44:03 resistor in there. If I stick a resistor in there 568 00:44:03 --> 00:44:08 what is vO equal to? vO is simply iR, 569 00:44:08 --> 00:44:11 right? That's right. 570 00:44:11 --> 00:44:16 vO, I get i here, so i pumps through here. 571 00:44:16 --> 00:44:24 Remember, what comes in here must get reflected up because 572 00:44:24 --> 00:44:30 the current going in here is zero. 573 00:44:30 --> 00:44:35 All the i must come out here. So, that i must pump through 574 00:44:35 --> 00:44:40 this resistor. The drop across this resistor 575 00:44:40 --> 00:44:43 is iR. That's the voltage drop across 576 00:44:43 --> 00:44:47 that resistor. And since this at a virtual 577 00:44:47 --> 00:44:53 ground the output here is simply zero minus this drop which is 578 00:44:53 --> 00:44:57 minus iR. So, I have gotten to where I 579 00:44:57 --> 00:45:02 want to be. I have my current i being 580 00:45:02 --> 00:45:06 converted to a voltage. I have taken my current, 581 00:45:06 --> 00:45:11 and I have been able to convert that into a voltage by sticking 582 00:45:11 --> 00:45:14 a resistor in here. As a final step, 583 00:45:14 --> 00:45:18 I simply need to produce the current. 584 00:45:18 --> 00:45:23 And that is pretty easy to do. Abstractly what I need to do, 585 00:45:23 --> 00:45:28 again, this is design here so we will talk about abstract 586 00:45:28 --> 00:45:32 stuff. If I had a voltage vI, 587 00:45:32 --> 00:45:39 I need to produce a current which relates to C dvI/dt. 588 00:45:39 --> 00:45:44 And I know I can do that by simply doing this. 589 00:45:44 --> 00:45:50 By doing this I know my i is C dvI, correct? 590 00:45:50 --> 00:45:56 If I can get this effect, I put this in quotes because 591 00:45:56 --> 00:46:03 that's my pattern. I am looking for a pattern, 592 00:46:03 --> 00:46:10 where a voltage vI is directly applied across a capacitor. 593 00:46:10 --> 00:46:17 And when that happens the current relates to C dv/dt. 594 00:46:17 --> 00:46:22 Let's go back to our op amp pattern here, 595 00:46:22 --> 00:46:29 op amp circuit. So far I have achieved -- 596 00:46:29 --> 00:46:33 I just repeated this out there. And so somehow I need to take 597 00:46:33 --> 00:46:38 this pattern here and learn from that pattern and apply the 598 00:46:38 --> 00:46:40 pattern here. So, what I can do is, 599 00:46:40 --> 00:46:43 this is a ground node, correct? 600 00:46:43 --> 00:46:47 Now, the poor little capacitor, what does it care, 601 00:46:47 --> 00:46:51 whether it's a ground node or a virtual ground node? 602 00:46:51 --> 00:46:55 As long as it's a zero volt node down here what does it 603 00:46:55 --> 00:46:59 care? What I am going to do is stick 604 00:46:59 --> 00:47:04 this point, not here but into a virtual ground node. 605 00:47:04 --> 00:47:10 I am going to grab that point, take it here and stick it here. 606 00:47:10 --> 00:47:14 The poor little capacitor doesn't know the difference. 607 00:47:14 --> 00:47:18 I have really suckered the little beast. 608 00:47:18 --> 00:47:20 This is vI. Remember this. 609 00:47:20 --> 00:47:25 My i through the capacitor is proportional to C dv/dt. 610 00:47:25 --> 00:47:31 Instead what I have done is taken this guy and stuck it here 611 00:47:31 --> 00:47:36 to get something like this. Just remember these four or 612 00:47:36 --> 00:47:39 five little tricks. And you apply them in op amp 613 00:47:39 --> 00:47:42 circuits again and again and again and again. 614 00:47:42 --> 00:47:45 So, this is vI, this is my virtual ground. 615 00:47:45 --> 00:47:48 As far as this poor little capacitor is concerned, 616 00:47:48 --> 00:47:52 it is chugging along merrily thinking that it is connected to 617 00:47:52 --> 00:47:55 ground. Little does it know it is only 618 00:47:55 --> 00:47:58 a virtual ground, all right? 619 00:47:58 --> 00:48:03 But the current i here is simply C dvI/dt. 620 00:48:03 --> 00:48:08 And that current, the C dvI/dt, 621 00:48:08 --> 00:48:15 that current flows through here and gives me vO as iR. 622 00:48:15 --> 00:48:23 So, vO is simply minus R. Let me substitute for i there, 623 00:48:23 --> 00:48:29 C dvI/dt. OK, so notice then that my vO 624 00:48:29 --> 00:48:37 is now proportional to dvI/dt. So, vO is some RC time constant 625 00:48:37 --> 00:48:41 times dvI/dt. Therefore, I have my 626 00:48:41 --> 00:48:45 differentiator circuit. Remember this as a closing 627 00:48:45 --> 00:48:49 thought. Remember this v plus more or 628 00:48:49 --> 00:48:54 less equal to v minus trick. And to the extent possible 629 00:48:54 --> 00:48:59 simply use that trick to analyze op amp circuits under feedback 630 00:48:59 --> 00:49:04 and not in saturation. Just remember these two. 631 00:49:04 --> 00:49:09 Very quickly for the demo, I have a square wave input here 632 00:49:09 --> 00:49:12 to the op amp, that's my vI to the integrator. 633 00:49:12 --> 00:49:16 And this is the output vO. The integral of a square wave 634 00:49:16 --> 00:49:19 is a triangular wave, as you can see. 635 00:49:19 --> 00:49:22 And we will do the same thing for a differentiator. 636 00:49:22 --> 00:49:27 And for the differentiator, I input the square wave to this 637 00:49:27 --> 00:49:31 differentiator circuit. And I get this, 638 00:49:31 --> 00:49:35 wherever there is a sharp rise, I get this huge negative spike 639 00:49:35 --> 00:49:39 and a positive spike because of the minus sign. 640 00:49:39 --> 00:49:41 So, this is the differentiator circuit. 641 00:49:41 --> 00:49:44 Then I feed this into the op amp. 642 00:49:44 --> 49:47 OK. Thank you.