1 00:00:00 --> 00:00:05 All right, let's get moving. Good morning. 2 00:00:05 --> 00:00:13 Let me take a quick poll. So, how many of you have 3 00:00:13 --> 00:00:17 completed Lab 4. Completed Lab 4? 4 00:00:17 --> 00:00:24 Wow, that's great. So, how many people have begun 5 00:00:24 --> 00:00:30 Lab 4? OK, well that's good. 6 00:00:30 --> 00:00:35 I won't ask the last question. OK so, well I hope you're 7 00:00:35 --> 00:00:40 having fun with this lab. Lab 4 was designed to be almost 8 00:00:40 --> 00:00:44 like a mini-project. And, it sort of ties together a 9 00:00:44 --> 00:00:48 lot of the content of the entire course. 10 00:00:48 --> 00:00:54 And, it's not unlike the kind of systems that people design in 11 00:00:54 --> 00:00:59 industry, in systems that go into a variety of devices like, 12 00:00:59 --> 00:01:03 say, for example, digital CD players and stuff 13 00:01:03 --> 00:01:10 like that. A lot of mixed signal stuff 14 00:01:10 --> 00:01:14 goes in. OK, so today, 15 00:01:14 --> 00:01:24 I'm going to continue with our discussion of energy and CMOS. 16 00:01:24 --> 00:01:34 CMOS will be a new topic that I will introduce. 17 00:01:34 --> 00:01:37 So, the last lecture, we spent a fair bit of time 18 00:01:37 --> 00:01:41 talking about energy, and how to compute the energy 19 00:01:41 --> 00:01:44 of our inverter. So, let me start from where I 20 00:01:44 --> 00:01:48 left off, and I've given you a couple of extra pages of notes 21 00:01:48 --> 00:01:52 today just to sort of tie it to the previous lecture. 22 00:01:52 --> 00:01:57 Right now, I'm going to start off on page three. 23 00:01:57 --> 00:02:02 So, what we saw last time was an inverter of this sort, 24 00:02:02 --> 00:02:07 Vs, VIN, and we said, let's study the situation where 25 00:02:07 --> 00:02:11 this inverter was driving a load capacitor, C. 26 00:02:11 --> 00:02:15 Where did this load capacitor come from? 27 00:02:15 --> 00:02:19 Well, this inverter could be driving one, or two, 28 00:02:19 --> 00:02:23 or three, or four other larger gates, OK? 29 00:02:23 --> 00:02:29 So, this C is lumped value of the gate capacitances of all of 30 00:02:29 --> 00:02:36 those inverters. This may also include some 31 00:02:36 --> 00:02:44 component due to wiring capacitance and stuff like that. 32 00:02:44 --> 00:02:54 So, for an inverter like this, we showed in the last lecture 33 00:02:54 --> 00:03:02 that the formula for the average power was, 34 00:03:02 --> 00:03:07 so this was a static power independent of frequency, 35 00:03:07 --> 00:03:13 and this was called dynamic power, and it had some bearing, 36 00:03:13 --> 00:03:19 it's related to the frequency at which you clocked your 37 00:03:19 --> 00:03:23 circuit. So, this was related to standby 38 00:03:23 --> 00:03:30 power, and this to dynamic. So, what I also said is that I 39 00:03:30 --> 00:03:38 gave you a bunch of numbers so you could compute the power 40 00:03:38 --> 00:03:44 consumption of a chip that included 10^8 gates, 41 00:03:44 --> 00:03:50 100 million gates, and at a frequency of 1 GHz, 42 00:03:50 --> 00:03:57 and a bunch of other numbers. C was given to be 0.1 43 00:03:57 --> 00:04:02 femtofarads. Femto is 10^-15. 44 00:04:02 --> 00:04:08 So, F was 10^9. VS was 5V, and for these 45 00:04:08 --> 00:04:16 numbers, if you plonk them down in something like this, 46 00:04:16 --> 00:04:25 for 10^8 gates on a chip, the average power would be 10^8 47 00:04:25 --> 00:04:32 times these two. So, this would be five squared, 48 00:04:32 --> 00:04:39 which is 25, divided by twice. 49 00:04:39 --> 00:04:45 RL was given to be 10 kilo-ohms, so, 50 00:04:45 --> 00:04:52 twice, 10^4. And here we had CVS^2. 51 00:04:52 --> 00:05:00 So, C was 10^-16, 0.1 femtofarads. 52 00:05:00 --> 00:05:04 Vs^2 was 25, and F was 10^9. 53 00:05:04 --> 00:05:11 So, if you commence through the numbers here, 54 00:05:11 --> 00:05:20 what you end up getting is something that looks like this, 55 00:05:20 --> 00:05:29 10^8 times this guy here. This is 1.25mW plus this guy 56 00:05:29 --> 00:05:39 ends up being 2.5 microwatts. So, this should come as a bit 57 00:05:39 --> 00:05:43 of a shocker. If I take 1.25mW, 58 00:05:43 --> 00:05:51 and multiply that out by 10^8, this says that each gate 59 00:05:51 --> 00:05:57 suffers a standby power loss of 1.25mW. 60 00:05:57 --> 00:06:01 So times 10^8, I get 125kW, 61 00:06:01 --> 00:06:07 and this guy yields 250W. OK, the 250W is manageable. 62 00:06:07 --> 00:06:11 It's still high, and just so you don't think 63 00:06:11 --> 00:06:14 that this is unreasonable, when the Pentium 4 first came 64 00:06:14 --> 00:06:17 out, it was consuming 170W of power. 65 00:06:17 --> 00:06:20 OK, you should see the heat sinks on there. 66 00:06:20 --> 00:06:24 There's actually a huge heat sink with a fan built into the 67 00:06:24 --> 00:06:28 top of the heat sink. OK, today it's down to more 68 00:06:28 --> 00:06:32 reasonable numbers like 100W and so on, but when it came out it 69 00:06:32 --> 00:06:36 was in this range. So it's high but not 70 00:06:36 --> 00:06:39 unreasonable. But this, of course, 71 00:06:39 --> 00:06:42 is totally wacko. OK, imagine carrying a laptop 72 00:06:42 --> 00:06:45 around, and the sucker is blowing 125kW. 73 00:06:45 --> 00:06:49 That'll be fun. So, clearly there's something 74 00:06:49 --> 00:06:52 wrong here. What this is saying is that 75 00:06:52 --> 00:06:57 this gate here consumes 125kW, there are 10^8 of these on a 76 00:06:57 --> 00:07:00 single chip. OK, so we clearly have to do 77 00:07:00 --> 00:07:04 something about this, otherwise the semiconductor 78 00:07:04 --> 00:07:10 industry would fail. So, anybody have any ideas? 79 00:07:10 --> 00:07:14 What do you think you might do here? 80 00:07:14 --> 00:07:21 What do you think you might do to this inverter to make this 81 00:07:21 --> 00:07:26 look better, to bring it down? What can I do? 82 00:07:26 --> 00:07:28 Anybody? Any ideas? 83 00:07:28 --> 00:07:34 What do you think? Well, the problem is that if I 84 00:07:34 --> 00:07:38 look at this 125kW, well, there's a VS term here 85 00:07:38 --> 00:07:41 and an RL term here. So, I can increase RL. 86 00:07:41 --> 00:07:46 OK, I can make RL four times or eight times as large. 87 00:07:46 --> 00:07:49 That'll bring the power down somewhat. 88 00:07:49 --> 00:07:53 Can anybody think of any problem with increasing RL? 89 00:07:53 --> 00:07:55 If I make RL really, really large, 90 00:07:55 --> 00:08:00 will I run into other problems? Yes? 91 00:08:00 --> 00:08:02 Exactly, the slowdown of the inverter. 92 00:08:02 --> 00:08:07 Remember, the rise time of the inverter depends on how quickly 93 00:08:07 --> 00:08:10 I can charge this capacitor through RL. 94 00:08:10 --> 00:08:14 So, if I make my RL really large, I will consume less 95 00:08:14 --> 00:08:19 standby power from hundreds of kilowatts to merely tens of 96 00:08:19 --> 00:08:22 kilowatts. But my gates will run as slow 97 00:08:22 --> 00:08:25 as molasses. So, clearly that's not a 98 00:08:25 --> 00:08:29 tradeoff I would like to make. So, I can reduce my voltage to 99 00:08:29 --> 00:08:34 maybe a volt. But that just reduces it by a 100 00:08:34 --> 00:08:37 factor of 25, VS squared. 101 00:08:37 --> 00:08:40 So clearly, this is not going to work. 102 00:08:40 --> 00:08:47 I have to somehow do something else, and that will be the topic 103 00:08:47 --> 00:08:51 of today's lecture. Also, I will dwell for a moment 104 00:08:51 --> 00:08:55 on this term. So, if you look at the spec 105 00:08:55 --> 00:09:01 sheet for the IBM's ASIC processor that we handed out, 106 00:09:01 --> 00:09:04 if you recall, we talked about power 107 00:09:04 --> 00:09:11 dissipation of 0.006 microwatts per MHz per gate. 108 00:09:11 --> 00:09:14 OK, now you see where this is coming from. 109 00:09:14 --> 00:09:17 Per MHz, that's because it's a multiple of f, 110 00:09:17 --> 00:09:21 the power. Second is that it's per gate, 111 00:09:21 --> 00:09:25 so this is the power per gate. So, as I have more gates, 112 00:09:25 --> 00:09:30 I just have that much more power dissipation. 113 00:09:30 --> 00:09:34 It also says power supply voltage in the range of 0.7 to 114 00:09:34 --> 00:09:36 1.3 right next to the power expression. 115 00:09:36 --> 00:09:40 So, you can see why they tell you all of that, 116 00:09:40 --> 00:09:43 because both voltage, and the frequency, 117 00:09:43 --> 00:09:47 and the number of gates come into the power of equation. 118 00:09:47 --> 00:09:50 OK, this really simple expression here, 119 00:09:50 --> 00:09:54 it's amazing how close this is to what people use for the 120 00:09:54 --> 00:09:59 dynamic power in chips. OK, so as the next step, 121 00:09:59 --> 00:10:04 what I'd like to do is, this guy, what do we do about 122 00:10:04 --> 00:10:07 that? OK, so we've taught you to 123 00:10:07 --> 00:10:13 build gates in a particular matter, but it's a non-starter. 124 00:10:13 --> 00:10:16 So, how do we get rid of static power? 125 00:10:16 --> 00:10:19 How do we get rid of static power? 126 00:10:19 --> 00:10:24 OK, to do so, let's build up a little bit of 127 00:10:24 --> 00:10:27 intuition. OK, so the intuition goes as 128 00:10:27 --> 00:10:31 follows. So let's say I take my 129 00:10:31 --> 00:10:33 inverter. Let me draw the circuit both on 130 00:10:33 --> 00:10:36 the on state and in the off state. 131 00:10:36 --> 00:10:50 132 00:10:50 --> 00:10:55 So, when VIN is high, when VIN is high, 133 00:10:55 --> 00:11:02 I get the MOSFET turning on and has a resistance, 134 00:11:02 --> 00:11:07 RON, and Vo is the output voltage. 135 00:11:07 --> 00:11:14 Similarly, when VIN is low, so when VIN was high, 136 00:11:14 --> 00:11:20 Vo was low because RON is much less than RL. 137 00:11:20 --> 00:11:27 So, this voltage was low, while here, when VIN is low, 138 00:11:27 --> 00:11:34 the MOSFET is off, and so I have an open circuit 139 00:11:34 --> 00:11:39 out here. And because of that open 140 00:11:39 --> 00:11:43 circuit, the voltage here was going to be high because VS 141 00:11:43 --> 00:11:47 would simply appear there. So let's tailor this and see if 142 00:11:47 --> 00:11:50 we can build up some intuition as to what to do. 143 00:11:50 --> 00:11:53 So, when VIN is low, I don't have any static power 144 00:11:53 --> 00:11:57 being dissipated because I don't have a connection from VS to 145 00:11:57 --> 00:11:59 ground. OK, the current, 146 00:11:59 --> 00:12:03 i, is zero. And, VS simply appears at the 147 00:12:03 --> 00:12:07 output. The reason this is so is have a 148 00:12:07 --> 00:12:09 switch here. So when this is low, 149 00:12:09 --> 00:12:15 the switch opens up and cuts the path from power to ground. 150 00:12:15 --> 00:12:19 This is a nice situation. Here, when VIN was high, 151 00:12:19 --> 00:12:22 there was no switch that turns off. 152 00:12:22 --> 00:12:26 Rather, I get a connection from VS to ground. 153 00:12:26 --> 00:12:30 OK, so think about this situation here. 154 00:12:30 --> 00:12:34 The insight here is, just imagine if I could do the 155 00:12:34 --> 00:12:38 following. Imagine if I could somehow 156 00:12:38 --> 00:12:42 magically elevate RL to be a very, very, very large number, 157 00:12:42 --> 00:12:46 if I could make this so high as to make the power really low 158 00:12:46 --> 00:12:50 only in the situation when the input was high, 159 00:12:50 --> 00:12:51 OK? So, imagine if I could do 160 00:12:51 --> 00:12:57 something like this. Imagine I could open circuit 161 00:12:57 --> 00:13:00 this guy, RON, so when VIN was high, 162 00:13:00 --> 00:13:07 if I could, instead of having an RL here, what if somehow I 163 00:13:07 --> 00:13:11 could make this RL become infinity? 164 00:13:11 --> 00:13:15 OK, so in this case, output VO would be low. 165 00:13:15 --> 00:13:19 OK, I get many benefits by doing this. 166 00:13:19 --> 00:13:25 One benefit is that, look, I have opened this switch 167 00:13:25 --> 00:13:29 here so I don't have any standby current. 168 00:13:29 --> 00:13:35 OK, the standby current is zero. 169 00:13:35 --> 00:13:39 The second benefit is that my output gets dragged down to 170 00:13:39 --> 00:13:41 ground, OK? Out here, my output was VS 171 00:13:41 --> 00:13:45 multiplied by RON divided by the sum of these two. 172 00:13:45 --> 00:13:48 Out here, I have a direct connection to ground, 173 00:13:48 --> 00:13:52 and nothing to the power supply, VS, and so therefore I 174 00:13:52 --> 00:13:56 have a nice, solid low. So the question is that, 175 00:13:56 --> 00:14:01 can I get this situation? OK, that is a key insight. 176 00:14:01 --> 00:14:04 So, imagine that somehow, when this was high, 177 00:14:04 --> 00:14:08 I could get this to open up, much like when this was low, 178 00:14:08 --> 00:14:11 I got this to open up. OK, so think about it. 179 00:14:11 --> 00:14:15 So, the intuition is that what I need instead of a resistor 180 00:14:15 --> 00:14:19 here, what if I have something like the MOSFET that I have 181 00:14:19 --> 00:14:22 here? So, I have a MOSFET here that 182 00:14:22 --> 00:14:25 turned off when VIN was low. OK, what if I did the 183 00:14:25 --> 00:14:30 complementary thing? What if I put in some kind of 184 00:14:30 --> 00:14:35 MOSFET here that would turn off when VIN was high? 185 00:14:35 --> 00:14:41 OK, so, much like the MOSFET turned off when VIN was low down 186 00:14:41 --> 00:14:47 here, imagine if I could find a device that could turn off when 187 00:14:47 --> 00:14:51 VIN was high? OK, this would be on, 188 00:14:51 --> 00:14:56 but this would be off. So the behavior of this device 189 00:14:56 --> 00:15:02 would have to be complementary to this device. 190 00:15:02 --> 00:15:07 So, we need some sort of a switch to introduce this new, 191 00:15:07 --> 00:15:12 little MOSFET device with slightly different properties, 192 00:15:12 --> 00:15:18 let me quickly review for you the properties of the MOSFET 193 00:15:18 --> 00:15:22 that we know about, so our N channel MOSFET, 194 00:15:22 --> 00:15:27 also called the NFET, this is what we've been seeing 195 00:15:27 --> 00:15:31 all this while, is drawn like this. 196 00:15:31 --> 00:15:34 I have a gate; I have a drain; 197 00:15:34 --> 00:15:42 I have a source. And this guy is on when VGS is 198 00:15:42 --> 00:15:52 greater than or equal to VT, OK, and off when VGS is less 199 00:15:52 --> 00:15:57 than VT. You saw this before, 200 00:15:57 --> 00:16:04 OK, nothing new here. So, what I need is a device 201 00:16:04 --> 00:16:09 that behaves in a complementary manner. 202 00:16:09 --> 00:16:13 OK, so the device is a P channel MOSFET. 203 00:16:13 --> 00:16:19 By the way, I must point out, till about 1983-84 until the 204 00:16:19 --> 00:16:24 early '80s, that's exactly pretty much how chips were 205 00:16:24 --> 00:16:29 designed, OK, using an NFET for the switch 206 00:16:29 --> 00:16:34 looking down here, and a variety of different 207 00:16:34 --> 00:16:40 kinds of devices to be used as resistors. 208 00:16:40 --> 00:16:44 OK, that's when technology began moving towards this new 209 00:16:44 --> 00:16:48 kind of technology I'm going to talk about, and that 210 00:16:48 --> 00:16:51 dramatically reducing the power consumed. 211 00:16:51 --> 00:16:55 And, the P channel MOSFET was created, and this guy's called 212 00:16:55 --> 00:16:58 the PFET. It's a complementary device 213 00:16:58 --> 00:17:03 that looks as follows. OK, the difference here is 214 00:17:03 --> 00:17:06 that, to show this is complementary, 215 00:17:06 --> 00:17:09 I'll put a little circle here. It has a gate. 216 00:17:09 --> 00:17:14 Just to make things a little clearer, flip the drain and 217 00:17:14 --> 00:17:17 source terminals, and this guy is on at a 218 00:17:17 --> 00:17:22 distinguished threshold voltage of this with the NFET device, 219 00:17:22 --> 00:17:27 let me put an N here to say that this is the VT for the N 220 00:17:27 --> 00:17:31 channel device. And for this guy, 221 00:17:31 --> 00:17:36 this guy came on when VGS was greater than some voltage. 222 00:17:36 --> 00:17:38 So, VTN could be, for example, 223 00:17:38 --> 00:17:42 one volt. So, VGS was more than one. 224 00:17:42 --> 00:17:44 This turned on. In this case, 225 00:17:44 --> 00:17:49 I wanted this to turn on when VGS is some value which is lower 226 00:17:49 --> 00:17:53 than, or much lower than, the source voltage. 227 00:17:53 --> 00:18:00 OK, so this guy turns on when the gate voltage is higher. 228 00:18:00 --> 00:18:03 This guy should turn on when the gate voltage is 229 00:18:03 --> 00:18:07 significantly lower than the source voltage, 230 00:18:07 --> 00:18:10 just the complementary behavior. 231 00:18:10 --> 00:18:13 OK, so when VGS is less than or equal to VTP. 232 00:18:13 --> 00:18:17 And in this case, the threshold voltage for the 233 00:18:17 --> 00:18:20 PMOS device, say, just as an example, 234 00:18:20 --> 00:18:23 maybe -1V. So this means that if the 235 00:18:23 --> 00:18:25 source is at, say, 5V, OK, 236 00:18:25 --> 00:18:30 then this device would turn on if the gate, for example, 237 00:18:30 --> 00:18:35 using that example was less than 4V. 238 00:18:35 --> 00:18:39 So, this is five. If the gate fell below 4V, 239 00:18:39 --> 00:18:43 this guy would turn on. In this situation, 240 00:18:43 --> 00:18:49 remember, if this was at zero, the gate would have to be 241 00:18:49 --> 00:18:53 greater than 1V to turn on. In this situation, 242 00:18:53 --> 00:18:59 the gate has to be less than 4V if the source was at five to 243 00:18:59 --> 00:19:03 turn on. And, it's off. 244 00:19:03 --> 00:19:06 OK, so this is a complementary device that I postulate that 245 00:19:06 --> 00:19:08 behaves in a complementary manner. 246 00:19:08 --> 00:19:11 So, the gate voltage rises, this guy turns on, 247 00:19:11 --> 00:19:14 and in this situation, when the gate voltage drops 248 00:19:14 --> 00:19:17 below the source voltage, this guy turns on. 249 00:19:17 --> 00:19:20 OK, so when there's a rising guy that turns on in this 250 00:19:20 --> 00:19:24 particular situation when it falls, the gate turns on and 251 00:19:24 --> 00:19:26 shows some resistance. In this case, 252 00:19:26 --> 00:19:29 the resistance would be RON. And to show that it's N 253 00:19:29 --> 00:19:34 channel, let me say N. And in this case, 254 00:19:34 --> 00:19:39 the resistance, when it turns on, 255 00:19:39 --> 00:19:44 would be RONp to represent P channel. 256 00:19:44 --> 00:19:51 OK, so now consider the following circuit for the 257 00:19:51 --> 00:19:56 inverter. So, instead of my resistor, 258 00:19:56 --> 00:20:05 I put a complementary device, OK, and that's it. 259 00:20:05 --> 00:20:09 So all I've done here is replace my resistor with a 260 00:20:09 --> 00:20:14 MOSFET that behaves complementary to the N channel 261 00:20:14 --> 00:20:16 MOSFET. So this is my gate, 262 00:20:16 --> 00:20:19 my drain. This is my source, 263 00:20:19 --> 00:20:22 my gate, my source, and my drain. 264 00:20:22 --> 00:20:27 OK, and this guy is called a pull up, and this guy is called 265 00:20:27 --> 00:20:33 a pull down. OK, and the reason is that this 266 00:20:33 --> 00:20:37 guy pulls the output to ground when it's turned on, 267 00:20:37 --> 00:20:41 while this guy, when switched on, 268 00:20:41 --> 00:20:46 will pull this node up to VS. So, I pull it down or pull it 269 00:20:46 --> 00:20:50 up based on when the VIN is high or low. 270 00:20:50 --> 00:20:54 So, let's look at the two situations. 271 00:20:54 --> 00:20:57 So, let's say, as an example, 272 00:20:57 --> 00:21:00 my VS is 5V, and let's say VIN in one 273 00:21:00 --> 00:21:05 situation being 5V, and another situation being 274 00:21:05 --> 00:21:11 equal to 0V. Let's draw the equivalent 275 00:21:11 --> 00:21:17 circuit in both these cases. So, when VIN is high, 276 00:21:17 --> 00:21:22 I have my usual circuit. When VIN is high, 277 00:21:22 --> 00:21:27 this MOSFET, as before, when VIN is 5V, 278 00:21:27 --> 00:21:35 the N channel MOSFET below is turned on, and so I have an RON 279 00:21:35 --> 00:21:40 resistance here. But remember, 280 00:21:40 --> 00:21:45 VIN is 5, and VS is 5V, then the voltage across the 281 00:21:45 --> 00:21:51 source and the gate of this P channel FET is now equal, 282 00:21:51 --> 00:21:55 five and five. OK, so this one would turn off. 283 00:21:55 --> 00:22:00 And that's the circuit that I get. 284 00:22:00 --> 00:22:05 The output is suitably low. In this situation, 285 00:22:05 --> 00:22:10 if VIN is zero, what happens in this situation? 286 00:22:10 --> 00:22:13 Here's my output. If VIN is 0V, 287 00:22:13 --> 00:22:17 the lower device turns off. This is zero. 288 00:22:17 --> 00:22:21 This is zero. This guy turns off, 289 00:22:21 --> 00:22:26 and that's the situation for the N channel MOSFET. 290 00:22:26 --> 00:22:33 How about this guy here? What happens here? 291 00:22:33 --> 00:22:37 This is at 5. So let me just, 292 00:22:37 --> 00:22:41 this is at 5V. OK, and VIN is at 0V. 293 00:22:41 --> 00:22:47 OK, so therefore, the GS of this is -5V. 294 00:22:47 --> 00:22:52 If this is zero and this is five, G, source, 295 00:22:52 --> 00:22:59 and drain, GS is -5V, and -5V is significantly less 296 00:22:59 --> 00:23:06 than the threshold -1V in our example. 297 00:23:06 --> 00:23:12 So, this one will switch on. And if this one switches on, 298 00:23:12 --> 00:23:17 what I end up getting is RONp out there. 299 00:23:17 --> 00:23:24 So, when this one kicks in, it pulls the output high and VO 300 00:23:24 --> 00:23:28 goes high. So, all I've done is replaced 301 00:23:28 --> 00:23:36 my resistor with a complementary device, which switches off when 302 00:23:36 --> 00:23:41 the input is high, and switches on when the input 303 00:23:41 --> 00:23:46 is low. And the beauty of this is that 304 00:23:46 --> 00:23:50 at no point, assuming all the devices are ideal here, 305 00:23:50 --> 00:23:55 at no point do I have a short circuit between the output, 306 00:23:55 --> 00:23:59 do I have a current path from the output to the ground from 307 00:23:59 --> 00:24:03 the supply to ground, OK, I have this turned off or 308 00:24:03 --> 00:24:09 this turned off. So, this type of logic 309 00:24:09 --> 00:24:18 involving a PMOS transistor here, and the N channel 310 00:24:18 --> 00:24:25 transistor here is called CMOS logic for, OK, 311 00:24:25 --> 00:24:31 it's called complementary MOS logic. 312 00:24:31 --> 00:24:39 That's what CMOS comes from. OK, so I'm sure you've read in 313 00:24:39 --> 00:24:43 a number of places that most digital chips today use CMOS 314 00:24:43 --> 00:24:46 technology. It comes from complementary 315 00:24:46 --> 00:24:51 MOS, and complementary comes from the use of complementary 316 00:24:51 --> 00:24:55 transistors: N channel, P channel, turns on when high, 317 00:24:55 --> 00:24:58 turns off when high, turns off when low, 318 00:24:58 --> 00:25:01 turns on when low. OK, that's exactly 319 00:25:01 --> 00:25:07 complementary to each other. OK, so what you've seen here 320 00:25:07 --> 00:25:13 has been the workhorse of the digital industry for the past 321 00:25:13 --> 00:25:16 two decades, 20 years, CMOS logic. 322 00:25:16 --> 00:25:21 OK, and even the most advanced chip from Intel has an inverter 323 00:25:21 --> 00:25:26 that looks exactly like that. OK, if you count all the 324 00:25:26 --> 00:25:32 inverters in the universe today, I would say a significant 325 00:25:32 --> 00:25:37 fraction of those look exactly like that, no difference, 326 00:25:37 --> 00:25:42 just so simple. So, the key with something like 327 00:25:42 --> 00:25:47 that is there is no path from the power supply to the ground, 328 00:25:47 --> 00:25:51 and so by that model, I did not consume any standby 329 00:25:51 --> 00:25:54 power. OK, my standby power in that 330 00:25:54 --> 00:25:58 idealized model is zero. So, let's compute P. 331 00:25:58 --> 00:26:04 So, what is P dynamic? Let's use the method that we 332 00:26:04 --> 00:26:11 adopted in the last lecture, and draw the equivalent 333 00:26:11 --> 00:26:18 circuit, and compute the power. OK, so I'm going to model the 334 00:26:18 --> 00:26:24 following situation, and assume that I drive a 335 00:26:24 --> 00:26:26 capacitive load, C. 336 00:26:26 --> 00:26:32 OK, and as an input, as I did the last time, 337 00:26:32 --> 00:26:38 I'm going to assume I have some input voltage, 338 00:26:38 --> 00:26:45 VIN, that looks like this. The cycle time, 339 00:26:45 --> 00:26:53 T, and the frequency is 1/t, and let me assume that this is 340 00:26:53 --> 00:26:59 T1, and this is T2. OK, and I'm assuming that T1 341 00:26:59 --> 00:27:09 and T2 are both much larger than the respective time constants. 342 00:27:09 --> 00:27:13 OK, the time constants when, for discharging here, 343 00:27:13 --> 00:27:18 is C RONn, and here the relevant resistance is RONp. 344 00:27:18 --> 00:27:23 The charging time constant is RONp times C. 345 00:27:23 --> 00:27:30 OK, so T1 and T2 are assumed to be much greater than these two. 346 00:27:30 --> 00:27:34 So when you look at this, there's one other benefit 347 00:27:34 --> 00:27:38 besides the power benefit, OK, of using CMOS logic 348 00:27:38 --> 00:27:43 compared to using NMOS. OK, it not only cuts out my 349 00:27:43 --> 00:27:46 standby power, but there is another 350 00:27:46 --> 00:27:51 significant advantage which is almost equal to the power 351 00:27:51 --> 00:27:54 advantage of this kind of CMOS technology. 352 00:27:54 --> 00:28:00 Anybody have any ideas? What's the advantage? 353 00:28:00 --> 00:28:05 What does intuition tell you? Is CMOS going to be faster or 354 00:28:05 --> 00:28:07 slower than NMOS? Why? 355 00:28:07 --> 00:28:11 That's right. The key here is that the NMOS 356 00:28:11 --> 00:28:16 design I showed you earlier was relatively slow because it took 357 00:28:16 --> 00:28:21 me a while to charge up the load capacitor from RL. 358 00:28:21 --> 00:28:24 In this situation, RL will become really, 359 00:28:24 --> 00:28:27 really small; it's RONp. 360 00:28:27 --> 00:28:32 It's roughly the same magnitude as RONm. 361 00:28:32 --> 00:28:35 OK, if so both of these on resistances are more or less 362 00:28:35 --> 00:28:39 equal and small, then the rise time will be of 363 00:28:39 --> 00:28:42 the same order of magnitude as the fall time, 364 00:28:42 --> 00:28:45 which makes this much faster than the NMOS. 365 00:28:45 --> 00:28:49 In NMOS, my time constant was RLC, and RL was pretty large. 366 00:28:49 --> 00:28:53 In this case it's RONp C, and RONp can be made to be very 367 00:28:53 --> 00:28:58 small because when it's switched off, the resistance here is 368 00:28:58 --> 00:29:02 infinity. So, in this situation, 369 00:29:02 --> 00:29:07 if I assume T1 and T2 are much larger than the respective time 370 00:29:07 --> 00:29:12 constants, I can go ahead and draw my equivalent circuit. 371 00:29:12 --> 00:29:16 So, here's VS. So, for charging up, 372 00:29:16 --> 00:29:20 let's say this one is going to a one, or to a high. 373 00:29:20 --> 00:29:24 So, I have VS going through a resistor, RONp, 374 00:29:24 --> 00:29:30 to a capacitor, and this thing is a switch. 375 00:29:30 --> 00:29:34 So I have RONp, an ideal switch, 376 00:29:34 --> 00:29:40 going to a capacitor, C, this is my V out node, 377 00:29:40 --> 00:29:46 OK, so it's VS going through a resistance, RONp, 378 00:29:46 --> 00:29:50 an ideal switch, to a capacitor, 379 00:29:50 --> 00:29:54 C. That's a charging circuit. 380 00:29:54 --> 00:30:00 For discharging, I have C, discharging through 381 00:30:00 --> 00:30:06 an ideal switch with RONn. So, this situation, 382 00:30:06 --> 00:30:12 I have an ideal switch, RONn. 383 00:30:12 --> 00:30:20 OK, so that's the equivalent circuit for something like this. 384 00:30:20 --> 00:30:27 So, in this circuit, during T1, this guy's off, 385 00:30:27 --> 00:30:31 and this guy's on, on during T1, 386 00:30:31 --> 00:30:37 and off otherwise. This guy is on during T2, 387 00:30:37 --> 00:30:41 and off otherwise. OK, so just imagine, 388 00:30:41 --> 00:30:45 this guy switches on, this guy switches off, 389 00:30:45 --> 00:30:49 this guy switches on, this guy switches off, 390 00:30:49 --> 00:30:50 OK? And remember, 391 00:30:50 --> 00:30:56 this is exactly the circuit I had analyzed last time in the 392 00:30:56 --> 00:30:59 last lecture, and the result given by v 393 00:30:59 --> 00:31:03 double asterisk. And that result was simply 394 00:31:03 --> 00:31:10 average power being CVS^2f. That's the exact circuit we 395 00:31:10 --> 00:31:13 used to compute the dynamic power, CVS^2f. 396 00:31:13 --> 00:31:17 OK, so we're done. And how did this come about? 397 00:31:17 --> 00:31:21 This came about because the intuition here is that I'm 398 00:31:21 --> 00:31:26 charging up the capacitor fully, and then I'm discharging the 399 00:31:26 --> 00:31:30 capacitor through this other side, OK, and I'm consuming 400 00:31:30 --> 00:31:35 power, dissipating power, in these two resistances during 401 00:31:35 --> 00:31:39 charge up and during the discharge. 402 00:31:39 --> 00:31:43 Half the power gets consumed during charge up, 403 00:31:43 --> 00:31:49 and half during the discharge. So, I'd like to go back to 404 00:31:49 --> 00:31:54 doing a few numbers here, and taking a look at how, 405 00:31:54 --> 00:31:59 even with this expression, life can get pretty thorny as 406 00:31:59 --> 00:32:04 we go ahead into the next decade. 407 00:32:04 --> 00:32:15 OK, so for our previous example, we assumed that 10^8 408 00:32:15 --> 00:32:22 gates, F=1 GHz, C=0.1 femtofarads, 409 00:32:22 --> 00:32:32 VS was 5V, and I don't need RL anymore. 410 00:32:32 --> 00:32:36 OK, why is it that I don't have any resistance component here? 411 00:32:36 --> 00:32:40 I don't have it here because the power consumed by this 412 00:32:40 --> 00:32:44 circuit is independent of those resistances, provided T1 and T2 413 00:32:44 --> 00:32:48 are long enough, are much longer than the two 414 00:32:48 --> 00:32:50 time constants, RONp C, and RONn C. 415 00:32:50 --> 00:32:53 OK, so I don't have RL in my equation anymore. 416 00:32:53 --> 00:33:00 I don't have any standby power. So, based on this calculation, 417 00:33:00 --> 00:33:08 the calculation I did up there showed that I had 2.5 microwatts 418 00:33:08 --> 00:33:16 per gate, and for 10^8 gates I had 250W for a chip with 10^8 419 00:33:16 --> 00:33:21 gates. So, I'd like to dwell on this, 420 00:33:21 --> 00:33:27 if you can move over to page eight in your notes, 421 00:33:27 --> 00:33:31 here. Let me dwell on this for some 422 00:33:31 --> 00:33:38 time, and pontificate on a few things. 423 00:33:38 --> 00:33:40 First of all, this number, 424 00:33:40 --> 00:33:43 as I said before, is high, but not a disaster. 425 00:33:43 --> 00:33:48 OK, so you can't use this in laptops, but it's quite OK for a 426 00:33:48 --> 00:33:51 desktop or a server, and so on. 427 00:33:51 --> 00:33:55 If you just go and put your ear to a pedestal computer, 428 00:33:55 --> 00:34:00 you'll always hear it making a sound, and that sound is because 429 00:34:00 --> 00:34:07 of a big fan that's inside it. And, if you have a big enough 430 00:34:07 --> 00:34:10 fan, 250W is not such a big deal. 431 00:34:10 --> 00:34:17 But, this is certainly a real problem for mobile devices. 432 00:34:17 --> 00:34:20 For a laptop, this is unthinkable. 433 00:34:20 --> 00:34:24 OK, so we have to deal with this. 434 00:34:24 --> 00:34:30 The second issue is the following, that it's 250W for 435 00:34:30 --> 00:34:34 1GHz. Now, the fastest Pentium 4s 436 00:34:34 --> 00:34:39 that money can by today are, what, how many GHz? 437 00:34:39 --> 00:34:44 What's the fastest Pentium 4 you can buy today? 438 00:34:44 --> 00:34:47 What's that? Does anybody have a 4GHz 439 00:34:47 --> 00:34:51 Pentium 4 here? Oh, darn, you beat me. 440 00:34:51 --> 00:34:53 Anybody have a 3? 3GHz? 441 00:34:53 --> 00:34:57 A couple. So, I have a couple of 3GHz 442 00:34:57 --> 00:35:03 machines, and our lab has a whole ton of them. 443 00:35:03 --> 00:35:06 So, if Intel comes out with 4GHz machines today, 444 00:35:06 --> 00:35:11 they've been going up by about 1GHz roughly every year for the 445 00:35:11 --> 00:35:14 past couple of years. And, within three or four 446 00:35:14 --> 00:35:19 years, you're going to see chips, microprocessors that are 447 00:35:19 --> 00:35:22 in the 5-10GHz range, OK, assuming that all other 448 00:35:22 --> 00:35:26 things stay equal, which of course they're not, 449 00:35:26 --> 00:35:29 but just to give you some insight here, 450 00:35:29 --> 00:35:33 if I clock these guys and build circuits that are ten times 451 00:35:33 --> 00:35:37 faster, I very soon go up to 2.5kW, again as I said, 452 00:35:37 --> 00:35:42 all things being equal which they're not. 453 00:35:42 --> 00:35:46 But just to give you a sense, as I increase my frequency, 454 00:35:46 --> 00:35:49 so does the power consumed by the chip, OK? 455 00:35:49 --> 00:35:52 So, I really have to do something here. 456 00:35:52 --> 00:35:55 So, if I stare at this equation, CVS^2f, 457 00:35:55 --> 00:35:59 I want to increase f because people will buy computers if I 458 00:35:59 --> 00:36:03 have higher frequencies. And, Intel has managed to use 459 00:36:03 --> 00:36:07 its marketing campaigns to pretty much convince consumers 460 00:36:07 --> 00:36:12 that high frequencies are a good thing. 461 00:36:12 --> 00:36:15 OK, and whether they really mean anything or not, 462 00:36:15 --> 00:36:19 that's a different issue. So, we've got this huge power 463 00:36:19 --> 00:36:22 for assuming 5V, OK, so it turns out that 464 00:36:22 --> 00:36:25 microprocessors, as they come out, 465 00:36:25 --> 00:36:29 newer and newer versions run at lower and lower voltages. 466 00:36:29 --> 00:36:33 OK, they invent technologies that use lower and lower 467 00:36:33 --> 00:36:38 voltages, and go from VS 5V to, today, VS on the order of 1.5 468 00:36:38 --> 00:36:44 to 1V, somewhere in that range. So the moment you do that, 469 00:36:44 --> 00:36:47 you get a 25x reduction in power. 470 00:36:47 --> 00:36:51 OK, so in going from 2.5kW, you would now come down to 471 00:36:51 --> 00:36:56 something on the order of 100W, which is, again, 472 00:36:56 --> 00:37:00 much more reasonable, again, all other things being 473 00:37:00 --> 00:37:03 equal. It turns out that the 474 00:37:03 --> 00:37:07 capacitance of devices also changes as you go to smaller and 475 00:37:07 --> 00:37:10 smaller devices. And, 100W is also pretty high, 476 00:37:10 --> 00:37:13 and still not good enough for mobile computers. 477 00:37:13 --> 00:37:16 So, there are many, many other tricks that people 478 00:37:16 --> 00:37:20 use to get even lower powers. One trick is to play games with 479 00:37:20 --> 00:37:22 the clock. OK, what you do is, 480 00:37:22 --> 00:37:26 let's say for example in some computation you are not going to 481 00:37:26 --> 00:37:30 be using your floating point unit. 482 00:37:30 --> 00:37:33 Or let's say I'm going to be using your integer adder unit. 483 00:37:33 --> 00:37:37 OK, so what you can do is you can turn off the clock to those 484 00:37:37 --> 00:37:41 devices so that those devices do not even switch when they're not 485 00:37:41 --> 00:37:43 working. OK, if I turn off the clock to 486 00:37:43 --> 00:37:46 a device, the device isn't even going to switch, 487 00:37:46 --> 00:37:50 it's just going to sit there in limbo without consuming any 488 00:37:50 --> 00:37:52 power. It's equivalent to turning off 489 00:37:52 --> 00:37:55 both transistors. If you turn off both the PMOS 490 00:37:55 --> 00:37:58 and NMOS somehow, OK, it's not consuming any 491 00:37:58 --> 00:38:01 power. And by doing that, 492 00:38:01 --> 00:38:03 you can further cut down the power. 493 00:38:03 --> 00:38:06 So, if you can idle some of your function units, 494 00:38:06 --> 00:38:10 it's called idling a function unit, idle a function unit for, 495 00:38:10 --> 00:38:14 let's say, half the time. OK, you would cut down power by 496 00:38:14 --> 00:38:17 another factor of two. We can idle, 497 00:38:17 --> 00:38:19 then, 75% of the time, come down to 25W. 498 00:38:19 --> 00:38:23 So, those are the classes of tricks that people play. 499 00:38:23 --> 00:38:26 I'm going to stop here and allow the underground guide 500 00:38:26 --> 00:38:30 folks to do the survey. But, suffice it to say that the 501 00:38:30 --> 00:38:34 power discussion that I've gone through with you is a very high 502 00:38:34 --> 00:38:39 level discussion as to the real thing. 503 00:38:39 --> 00:38:41 In real life, what actually happens is that 504 00:38:41 --> 00:38:44 there is a fair amount of standby power even for CMOS 505 00:38:44 --> 00:38:46 logic. It turns out that although I 506 00:38:46 --> 00:38:50 don't have a path from VS to ground for my two transistors, 507 00:38:50 --> 00:38:53 it turns out that there are many leakage currents. 508 00:38:53 --> 00:38:57 OK, currents leak through all kinds of places through the 509 00:38:57 --> 00:38:59 drain of the inverter, and so on and so forth. 510 00:38:59 --> 00:39:03 And so, there is some standby power. 511 00:39:03 --> 00:39:06 So, let me show you a quick demo while, I guess, 512 00:39:06 --> 00:39:09 the review handouts are going around. 513 00:39:09 --> 00:39:13 And this shows the temperature of my CMOS inverter, 514 00:39:13 --> 00:39:17 and as I increase the frequency, you can just watch 515 00:39:17 --> 00:39:21 the temperature go up, and hopefully we'll blow this 516 00:39:21 --> 00:39:24 transistor. So, I'm increasing the 517 00:39:24 --> 00:39:29 frequency as you can see on the side here, and higher frequency 518 00:39:29 --> 00:39:33 implies more power consumption, more temperature, 519 00:39:33 --> 00:39:37 OK, and hopefully you will see some smoke coming out of, 520 00:39:37 --> 00:39:42 OK, I think I blew the inverter. 521 00:39:42 --> 00:39:46 So, the output is gone. So, it's at 110 degrees there, 522 00:39:46 --> 00:39:49 and that blew it. Sometimes we see smoke come 523 00:39:49 --> 00:39:54 out, but I guess today is not one of our lucky days. 524 00:39:54 --> 00:39:58 OK, so let me stop here and have the underground guide folks 525 00:39:58 --> 40:01 go through the reviews.