1 00:00:00 --> 00:00:25 2 00:00:25 --> 00:00:30 All right. Good morning. 3 00:00:30 --> 00:00:35 Let's get started. So the last lecture we showed 4 00:00:35 --> 00:00:40 you how to go digital. The fact that going digital had 5 00:00:40 --> 00:00:46 some key benefits for us. And what we'll do today is go 6 00:00:46 --> 00:00:50 inside the digital gate. 7 00:00:50 --> 00:01:06 8 00:01:06 --> 00:01:11 Let's do a quick review. We began life by observing 9 00:01:11 --> 00:01:14 nature. We said those Maxwell's 10 00:01:14 --> 00:01:19 equations are tough. Let's simplify our lives by 11 00:01:19 --> 00:01:25 discretizing or lumping matter. So we got the lumped circuit 12 00:01:25 --> 00:01:30 abstraction. Then we had this noise problem 13 00:01:30 --> 00:01:35 here. In order to be able to handle 14 00:01:35 --> 00:01:39 that let's do some more discretization, 15 00:01:39 --> 00:01:43 some more lumping. So we said let's discretize 16 00:01:43 --> 00:01:49 values and deal with two levels, a high and a low. 17 00:01:49 --> 00:01:53 That's where the binary voltage levels come up, 18 00:01:53 --> 00:01:59 a high level and a low level. And then we said that in 19 00:01:59 --> 00:02:03 discretizing it we have to make some assumptions. 20 00:02:03 --> 00:02:06 We have to impose some constraints on ourselves. 21 00:02:06 --> 00:02:10 Just as with the lumped matter discipline, we imposed a couple 22 00:02:10 --> 00:02:14 of constraints in going from the continuous matter world to a 23 00:02:14 --> 00:02:18 lumped matter world. Similarly, we have to impose 24 00:02:18 --> 00:02:22 some discipline on ourselves, some constraints on ourselves 25 00:02:22 --> 00:02:26 in going from the continuous value regime to the digital 26 00:02:26 --> 00:02:29 value regime. And that discipline is called 27 00:02:29 --> 00:02:32 the static discipline. 28 00:02:32 --> 00:02:38 29 00:02:38 --> 00:02:44 And what the static discipline says is that if you have senders 30 00:02:44 --> 00:02:50 and receivers in a digital system then they all need to 31 00:02:50 --> 00:02:55 adhere to some standard. If I was a sender I had to 32 00:02:55 --> 00:03:00 adhere to some tough output standards. 33 00:03:00 --> 00:03:05 I had to be sure to shift values that exceeded some high 34 00:03:05 --> 00:03:10 voltage threshold. And if I was sending a low 35 00:03:10 --> 00:03:16 value I had to make sure my values were lower than some 36 00:03:16 --> 00:03:22 output low voltage threshold. Similarly, if I was the 37 00:03:22 --> 00:03:28 receiver then I had to guarantee to recognize as a one all 38 00:03:28 --> 00:03:36 voltages that where above some input high voltage threshold. 39 00:03:36 --> 00:03:40 And similarly I had to guarantee to recognize as a zero 40 00:03:40 --> 00:03:46 voltages that were below some input low voltage threshold. 41 00:03:46 --> 00:03:51 So provided senders and receivers in a system adhere to 42 00:03:51 --> 00:03:55 these voltage levels, to this discipline then they 43 00:03:55 --> 00:04:02 would all very comfortably work correctly in a digital system. 44 00:04:02 --> 00:04:06 Then we also said that once you deal with such values, 45 00:04:06 --> 00:04:10 one you deal with digital values we can now postulate a 46 00:04:10 --> 00:04:15 bunch of digital elements that process these values in a manner 47 00:04:15 --> 00:04:20 very reminiscent of our analog circuits where we get analog 48 00:04:20 --> 00:04:23 signals. And you've already learned how 49 00:04:23 --> 00:04:27 to process analog signals. You've learned about resistor 50 00:04:27 --> 00:04:33 dividers and so on and so forth. You feed in an analog signal 51 00:04:33 --> 00:04:37 and you get an output analog signal as well. 52 00:04:37 --> 00:04:41 Now, here the resistor in the analog domain, 53 00:04:41 --> 00:04:46 elements like resistors and voltage sources were the symbols 54 00:04:46 --> 00:04:51 that you dealt with. Here, in the digital domain, 55 00:04:51 --> 00:04:58 the primitive elements that we will be using are called gates. 56 00:04:58 --> 00:05:02 As one example, this is called the NAND gate. 57 00:05:02 --> 00:05:08 So we looked at the AND gate in the previous lecture. 58 00:05:08 --> 00:05:13 This is an example of another gate called the NAND gate. 59 00:05:13 --> 00:05:18 The NAND gate has the following truth table. 60 00:05:18 --> 00:05:22 Our two inputs A and B and this output C. 61 00:05:22 --> 00:05:26 And the NAND gate works as follows. 62 00:05:26 --> 00:05:31 The output -- In English I can describe its 63 00:05:31 --> 00:05:37 properties as the output is a high at all times when at least 64 00:05:37 --> 00:05:40 one of these inputs is a low value. 65 00:05:40 --> 00:05:45 So it's high whenever at least one input is a low. 66 00:05:45 --> 00:05:48 So it's high here. It's high here. 67 00:05:48 --> 00:05:51 Oops, it's high here, high here. 68 00:05:51 --> 00:05:55 And when, oops. And when both inputs are a high 69 00:05:55 --> 00:06:00 the output is a low. This is a NAND gate. 70 00:06:00 --> 00:06:05 Notice that these are exactly complimentary to the AND gate. 71 00:06:05 --> 00:06:08 The AND gate outputs were 0-0-0-1. 72 00:06:08 --> 00:06:11 And the AND gate symbol looked like this. 73 00:06:11 --> 00:06:15 In general, notice that this little bubble here, 74 00:06:15 --> 00:06:20 it's called a bubble. That bubble implies a negation, 75 00:06:20 --> 00:06:23 an inversion. So we take the AND gate, 76 00:06:23 --> 00:06:28 invert the output and negate the output and you get the NAND 77 00:06:28 --> 00:06:32 gate. So these elements are 78 00:06:32 --> 00:06:37 combinational gates. And in combinational gates they 79 00:06:37 --> 00:06:42 adhere to two properties. One is that they must satisfy 80 00:06:42 --> 00:06:45 the static discipline. 81 00:06:45 --> 00:06:50 82 00:06:50 --> 00:06:52 All the systems, all the elements in our 83 00:06:52 --> 00:06:56 repertoire in the digital domain need to satisfy the static 84 00:06:56 --> 00:06:58 discipline. And the properties of a 85 00:06:58 --> 00:07:03 combinational gate are that its outputs are a function of inputs 86 00:07:03 --> 00:07:04 alone. 87 00:07:04 --> 00:07:13 88 00:07:13 --> 00:07:16 In other words, it doesn't store any state or 89 00:07:16 --> 00:07:18 doesn't store any history inside it. 90 00:07:18 --> 00:07:23 You can figure out its output just by looking at the inputs at 91 00:07:23 --> 00:07:26 that instant. Think of it as a completely 92 00:07:26 --> 00:07:30 transparent entity where its output reflects some function of 93 00:07:30 --> 00:07:34 the inputs at every instant of time. 94 00:07:34 --> 00:07:44 95 00:07:44 --> 00:07:48 So I'll show you an example of a digital circuit. 96 00:07:48 --> 00:07:53 97 00:07:53 --> 00:07:56 So much as I could interconnect resistors and voltage sources 98 00:07:56 --> 00:07:58 and current sources to build analog circuits, 99 00:07:58 --> 00:08:01 I can now build digital circuits using primitive 100 00:08:01 --> 00:08:04 elements such as these. So, for example, 101 00:08:04 --> 00:08:11 I could build a simple circuit that looked like this, 102 00:08:11 --> 00:08:16 two inputs A and B here, I get an output. 103 00:08:16 --> 00:08:23 And I feed that to another NAND gate with another input C. 104 00:08:23 --> 00:08:28 This device is called an inverter. 105 00:08:28 --> 00:08:31 The inverter simply flips the sense of the input. 106 00:08:31 --> 00:08:36 So if C is a 1 the output is a 0, if C is a 0 the output 107 00:08:36 --> 00:08:38 becomes a 1. It's an inverter. 108 00:08:38 --> 00:08:42 It simply inverts its input. Yet another primitive device. 109 00:08:42 --> 00:08:46 And this is my output D. So there are three gates in 110 00:08:46 --> 00:08:50 this design. And I can quickly write down 111 00:08:50 --> 00:08:55 what the output looks like using some very simple Boolean algebra 112 00:08:55 --> 00:08:59 or dealing with Boolean values here. 113 00:08:59 --> 00:09:03 So for AND gate the output is A and B. 114 00:09:03 --> 00:09:07 Remember dot is a short form for and. 115 00:09:07 --> 00:09:12 But there's a negation, inversion, so represent 116 00:09:12 --> 00:09:17 inversions with a bar. So my output is A dot B bar. 117 00:09:17 --> 00:09:22 There is a C here. So this is my output C bar. 118 00:09:22 --> 00:09:30 And this is a NAND gate. So it takes one input A dot B. 119 00:09:30 --> 00:09:36 It takes the second input C bar and ANDs those and inverts them. 120 00:09:36 --> 00:09:40 So that's the output. So there are three gates in 121 00:09:40 --> 00:09:44 this example. So you can think of building 122 00:09:44 --> 00:09:49 very complicated circuits containing large numbers of 123 00:09:49 --> 00:09:53 gates. In fact, the microprocessors 124 00:09:53 --> 00:10:00 that you use in your laptop contain a large number of gates. 125 00:10:00 --> 00:10:08 Can someone guess how many gates are in the Pentium IV, 126 00:10:08 --> 00:10:11 roughly? Approximate, 127 00:10:11 --> 00:10:17 how many? How many gates in a Pentium IV? 128 00:10:17 --> 00:10:21 40 million. 100 million. 129 00:10:21 --> 00:10:32 In the Pentium IV you have on the order of 20 million gates. 130 00:10:32 --> 00:10:35 20 million gates in the Pentium IV. 131 00:10:35 --> 00:10:41 And life begins in 002. Here you learn about onsies and 132 00:10:41 --> 00:10:47 twosies, and in the real world you will be dealing with tens of 133 00:10:47 --> 00:10:52 millions of gates. But this is for the Pentium IV. 134 00:10:52 --> 00:10:58 My research group at Laboratory for Computer Science built a 135 00:10:58 --> 00:11:04 chip called the Raw chip. And this chip has 3 million 136 00:11:04 --> 00:11:07 gates. And so there are several 137 00:11:07 --> 00:11:12 undergraduate students involved in this project in their third 138 00:11:12 --> 00:11:17 year, and they're beginning to deal with millions of gates. 139 00:11:17 --> 00:11:22 So the key thing to remember is that 002 provides the 140 00:11:22 --> 00:11:27 foundations where you make the switch from the analog signal to 141 00:11:27 --> 00:11:32 the digital signal or from continuous matter to lumped 142 00:11:32 --> 00:11:36 matter. And learn about the foundations 143 00:11:36 --> 00:11:40 of these primitive elements. And by the end of this course 144 00:11:40 --> 00:11:43 you will begin dealing with small systems, 145 00:11:43 --> 00:11:48 analog systems that contain on the order of 10 to 20 primitive 146 00:11:48 --> 00:11:51 elements. You will also begin dealing 147 00:11:51 --> 00:11:55 with small digital systems that contain tens of gates. 148 00:11:55 --> 00:11:59 In your final project you will build a mixed signal circuit 149 00:11:59 --> 00:12:03 involving an audio playback system. 150 00:12:03 --> 00:12:06 You will have digital data stored in a memory chip and you 151 00:12:06 --> 00:12:10 will build a circuit to extract that data, filter it and then 152 00:12:10 --> 00:12:14 convert it to the analog domain and then play it on a set of 153 00:12:14 --> 00:12:17 speakers. And that has on the order of 154 00:12:17 --> 00:12:19 about 50 to 100 primitive elements. 155 00:12:19 --> 00:12:23 So by the end of 002 you will have learned to deal with 156 00:12:23 --> 00:12:26 hundreds of elements. And then you will take other 157 00:12:26 --> 00:12:30 courses like 004 and so on where you will then make the leap to 158 00:12:30 --> 00:12:34 learn further abstractions that will take you from subsystems to 159 00:12:34 --> 00:12:39 systems with millions of gates. So the key is to manage the 160 00:12:39 --> 00:12:43 complexity of dealing with millions of gates it's all about 161 00:12:43 --> 00:12:47 abstractions. You have to build abstractions 162 00:12:47 --> 00:12:50 and double abstractions so you can deal with complexity. 163 00:12:50 --> 00:12:54 So the rest of EECS will take you from three gates to 20 164 00:12:54 --> 00:12:58 million gates and software systems that operate on 20 165 00:12:58 --> 00:13:03 million gates or whatever. So there is still a ways to go. 166 00:13:03 --> 00:13:09 Lorenzo, our friend has gone to bring a demonstration that we 167 00:13:09 --> 00:13:14 forgot to bring today. That will show you that little 168 00:13:14 --> 00:13:17 digital circuit in a mock up form. 169 00:13:17 --> 00:13:20 So what's today's lecture about? 170 00:13:20 --> 00:13:27 Today's lecture is going to be about what's inside a gate? 171 00:13:27 --> 00:13:35 172 00:13:35 --> 00:13:38 How to build a gate. Once you build a gate you can 173 00:13:38 --> 00:13:42 then put millions of them into computer systems or analog 174 00:13:42 --> 00:13:44 systems or other sorts of systems. 175 00:13:44 --> 00:13:48 And what we'll do here is understand what's inside this 176 00:13:48 --> 00:13:51 abstraction. This is an abstract element 177 00:13:51 --> 00:13:55 that looks like a little circle and a line with some stuff 178 00:13:55 --> 00:13:59 inside it, with some properties. But someone's got to build 179 00:13:59 --> 00:14:02 that. It doesn't come from nature. 180 00:14:02 --> 00:14:06 You don't go and harvest gates from trees, you got to go build 181 00:14:06 --> 00:14:08 that, and someone has got to do that. 182 00:14:08 --> 00:14:12 So what to learn here is how do we go about building a gate? 183 00:14:12 --> 00:14:15 And here you will see practically how do you deal with 184 00:14:15 --> 00:14:18 voltage thresholds that satisfy a given static discipline? 185 00:14:18 --> 00:14:22 So before I jump into building a gate, let me try to build up 186 00:14:22 --> 00:14:24 some intuition. As is my usual practice, 187 00:14:24 --> 00:14:28 I'd love to get you to build some intuition as to how to 188 00:14:28 --> 00:14:33 build a gate. And then we'll go through the 189 00:14:33 --> 00:14:38 mechanics of doing it. So to build intuition, 190 00:14:38 --> 00:14:44 let me show you an analogous situation in fluids. 191 00:14:44 --> 00:14:48 So let's say I have a cauldron of water. 192 00:14:48 --> 00:14:55 This is like a power supply. And I need to feed this fluid 193 00:14:55 --> 00:15:03 down at some output source. And what I do in the middle is 194 00:15:03 --> 00:15:09 put in a couple of taps, faucets, all right? 195 00:15:09 --> 00:15:16 And so what do these guys do? Under what condition do you 196 00:15:16 --> 00:15:23 have fluid flow out of the tube at the other end? 197 00:15:23 --> 00:15:35 You will have fluid flow if -- So let me call this A and B. 198 00:15:35 --> 00:15:45 If A is on and B is on then C has water. 199 00:15:45 --> 00:16:02 Otherwise, if both A and B are not on then C has no water. 200 00:16:02 --> 00:16:06 So this is already beginning to sound like a AND gate, 201 00:16:06 --> 00:16:11 correct, where you get water only if A and B are both turned 202 00:16:11 --> 00:16:14 on. So we're going to use this 203 00:16:14 --> 00:16:19 insight, a stream of some flow and I put things to obstruct the 204 00:16:19 --> 00:16:22 flow. And when both the obstructions 205 00:16:22 --> 00:16:27 are lifted I get the output. I want to use that intuition to 206 00:16:27 --> 00:16:33 build an AND gate. Similarly, I could build a 207 00:16:33 --> 00:16:42 system that allows me to build the following structure -- 208 00:16:42 --> 00:16:58 209 00:16:58 --> 00:17:01 So in this scenario let me call this -- 210 00:17:01 --> 00:17:07 211 00:17:07 --> 00:17:11 -- the signal of A and B here. And in this situation under 212 00:17:11 --> 00:17:14 what conditions, provided the power supply has 213 00:17:14 --> 00:17:17 water, under what conditions do I get water out? 214 00:17:17 --> 00:17:21 In this situation, it is I get water if A or B are 215 00:17:21 --> 00:17:24 turned on. So I don't need to turn both A 216 00:17:24 --> 00:17:26 and B on. If either one of them is on, 217 00:17:26 --> 00:17:30 I'm going to get fluid flow here. 218 00:17:30 --> 00:17:36 So this will help us build the inside to build the OR gate. 219 00:17:36 --> 00:17:43 So that's an analogy involving items we see in everyday life. 220 00:17:43 --> 00:17:48 Let me now move into the electrical domain. 221 00:17:48 --> 00:17:55 In the electrical domain my analogy would be something like 222 00:17:55 --> 00:17:59 this. Let's say I have a power supply 223 00:17:59 --> 00:18:06 and I have two switches A and B. And I build a little circuit 224 00:18:06 --> 00:18:10 that connects this voltage source across the bulb using a 225 00:18:10 --> 00:18:13 couple of switches. In this case, 226 00:18:13 --> 00:18:17 the bulb is on if both switches A and B are on. 227 00:18:17 --> 00:18:20 My bulb turns on. If I switch either one of them 228 00:18:20 --> 00:18:24 off my bulb turns off. So notice that I can begin 229 00:18:24 --> 00:18:30 implementing things like this if I had this element. 230 00:18:30 --> 00:18:33 I had sources already. I know how to deal with bulbs. 231 00:18:33 --> 00:18:38 I model them as resistors. So I need to do something about 232 00:18:38 --> 00:18:40 this new element called a "switch". 233 00:18:40 --> 00:18:43 So let me build an abstract device. 234 00:18:43 --> 00:18:47 I'll tell you how to do that in real life in a second. 235 00:18:47 --> 00:18:51 So if I had the switch I could build things like this. 236 00:18:51 --> 00:18:55 I could put switches in series in a circuit and get myself 237 00:18:55 --> 00:19:00 something that looks like a AND function. 238 00:19:00 --> 00:19:07 So let me go ahead and build an equivalent circuit for a switch. 239 00:19:07 --> 00:19:13 So the switch has a couple of terminals here and I have a 240 00:19:13 --> 00:19:17 control. Switches have a control and 241 00:19:17 --> 00:19:24 they have a pair of terminals. And the equivalent circuit for 242 00:19:24 --> 00:19:30 this looks like this. This is for my switch. 243 00:19:30 --> 00:19:37 So when control is a 0. Then my switch is open to give 244 00:19:37 --> 00:19:44 me an open circuit in the circuit that I've shown you 245 00:19:44 --> 00:19:48 here. And, by the same token, 246 00:19:48 --> 00:19:53 if my control is a 1 then -- 247 00:19:53 --> 00:20:03 248 00:20:03 --> 00:20:06 -- I have a connection between in and out. 249 00:20:06 --> 00:20:09 And this is a short circuit. So, in other words, 250 00:20:09 --> 00:20:13 if my switch has 0 at its control, I'll talk about how to 251 00:20:13 --> 00:20:17 get that, I have an open circuit, and if it's a 1 then I 252 00:20:17 --> 00:20:21 have a short circuit. This is a switch going on and 253 00:20:21 --> 00:20:23 off. Now, in traditional switches 254 00:20:23 --> 00:20:26 mechanical pressure is my control signal. 255 00:20:26 --> 00:20:32 If I apply mechanical pressure my switch could turn on. 256 00:20:32 --> 00:20:36 And if I take away the mechanical pressure then I could 257 00:20:36 --> 00:20:41 get an off situation. So let's for now imagine that 258 00:20:41 --> 00:20:45 we have a switch. I still haven't told you how I 259 00:20:45 --> 00:20:48 am going to get a switch in real life. 260 00:20:48 --> 00:20:51 Let's imagine you have a switch. 261 00:20:51 --> 00:20:57 It's a three terminal device. There's a control thingamajig 262 00:20:57 --> 00:21:02 coming in. Input and an output. 263 00:21:02 --> 00:21:10 So let's build the following little circuit containing a 264 00:21:10 --> 00:21:15 switch. So what I'm going to do, 265 00:21:15 --> 00:21:23 I will take a resistance RL and plug it in here. 266 00:21:23 --> 00:21:30 267 00:21:30 --> 00:21:33 And connect my power supply like so. 268 00:21:33 --> 00:21:37 So the little circuit that I build has a resistor. 269 00:21:37 --> 00:21:42 And I connect the switch in this pattern and I get a VS. 270 00:21:42 --> 00:21:47 Lorenzo, you can set that up there if you'd like. 271 00:21:47 --> 00:21:49 No problem. So I get a VS here. 272 00:21:49 --> 00:21:54 Now, a couple of lectures ago I told you that 6.002, 273 00:21:54 --> 00:21:58 and for that matter, 004 and many of our other 274 00:21:58 --> 00:22:04 courses deal with combinations of elements. 275 00:22:04 --> 00:22:08 And we often deal with the same kinds of combinations again and 276 00:22:08 --> 00:22:11 again and again. We see the same sorts of 277 00:22:11 --> 00:22:14 patterns happening, and we need to begin to learn 278 00:22:14 --> 00:22:18 to identify these patterns. This is an incredibly common 279 00:22:18 --> 00:22:21 pattern. You'll see this pattern more 280 00:22:21 --> 00:22:24 times in 6.002 than any other pattern, I promise you. 281 00:22:24 --> 00:22:28 A power supply connected to a resistor and connected to a 282 00:22:28 --> 00:22:33 couple of terminals of some interesting device. 283 00:22:33 --> 00:22:36 I promise there will be at least one such pattern on the 284 00:22:36 --> 00:22:39 quiz, for example. These patterns are incredibly 285 00:22:39 --> 00:22:41 common. So let's take a look at the 286 00:22:41 --> 00:22:43 interesting properties of this pattern. 287 00:22:43 --> 00:22:47 Since this pattern occurs so commonly, I am going to create a 288 00:22:47 --> 00:22:50 short form. I have already created a short 289 00:22:50 --> 00:22:52 form which is this ground node here. 290 00:22:52 --> 00:22:56 By putting ground 0 all I'm really saying is that there is a 291 00:22:56 --> 00:23:00 wire connecting these two and that's my ground. 292 00:23:00 --> 00:23:02 So I already have a short form here. 293 00:23:02 --> 00:23:06 My second short form is when I connect a power supply to a 294 00:23:06 --> 00:23:09 node. Then what I'm going to do is 295 00:23:09 --> 00:23:13 come up with yet another short form that looks like this, 296 00:23:13 --> 00:23:16 an up arrow with the voltage written there. 297 00:23:16 --> 00:23:20 This symbol simply says that this node is connected to a 298 00:23:20 --> 00:23:24 power supply with voltage, or a voltage source voltage VS. 299 00:23:24 --> 00:23:29 So I just have come up with a slightly simpler representation 300 00:23:29 --> 00:23:33 for the little pattern that I have. 301 00:23:33 --> 00:23:37 Now let's take a look at the properties of this little 302 00:23:37 --> 00:23:40 system. Let's first look at what 303 00:23:40 --> 00:23:42 happens when C is 0. When C is 0, 304 00:23:42 --> 00:23:47 let me draw the equivalent circuit for this using the open 305 00:23:47 --> 00:23:50 circuit out there. 306 00:23:50 --> 00:24:00 307 00:24:00 --> 00:24:02 That's what I get, OK? 308 00:24:02 --> 00:24:06 So when C is 0, if VS is a high voltage, 309 00:24:06 --> 00:24:11 let's say 5 volts, what do you expect at the 310 00:24:11 --> 00:24:16 output if C is a 0? This voltage VS appears at V 311 00:24:16 --> 00:24:21 out because this is an open circuit here. 312 00:24:21 --> 00:24:29 Remember, RL and this little device form a voltage divider. 313 00:24:29 --> 00:24:34 But since it's an open circuit its resistance is infinity. 314 00:24:34 --> 00:24:40 And so therefore in this resistor divider all the voltage 315 00:24:40 --> 00:24:44 falls across this open circuit. So, in this case, 316 00:24:44 --> 00:24:50 v out is a 1 or a high voltage. But let's take a look at what 317 00:24:50 --> 00:24:54 happens when C is a 1. In this situation, 318 00:24:54 --> 00:24:59 I have my RL, that's what I have. 319 00:24:59 --> 00:25:03 It's a short circuit at the switch and C is a 1. 320 00:25:03 --> 00:25:07 So what's the voltage v out in this case? 321 00:25:07 --> 00:25:12 Not surprisingly, since I've shorted this node to 322 00:25:12 --> 00:25:16 ground the voltage at this point is 0. 323 00:25:16 --> 00:25:23 So if I have low voltage that's corresponding to logical 0s that 324 00:25:23 --> 00:25:29 corresponds to a 0. So I can build a simple truth 325 00:25:29 --> 00:25:34 table for C and use logical symbols here. 326 00:25:34 --> 00:25:42 So when C is a 0 I get a high at the output and when C is 1 I 327 00:25:42 --> 00:25:49 get a low at the output. Have you seen a device that 328 00:25:49 --> 00:25:55 behaves like this so far? That's a little inverter. 329 00:25:55 --> 00:26:02 That's the exact behavior of an inverter. 330 00:26:02 --> 00:26:06 So this thing I've written here is a truth table for an 331 00:26:06 --> 00:26:09 inverter. So notice with just a simple 332 00:26:09 --> 00:26:13 little switch and a resistor, I have managed to build an 333 00:26:13 --> 00:26:15 inverter. Before I go on, 334 00:26:15 --> 00:26:18 I guess we have some things to show you. 335 00:26:18 --> 00:26:23 And let me pause for a couple of seconds and do that. 336 00:26:23 --> 00:26:26 First of all, what I want to show you is the 337 00:26:26 --> 00:26:30 following idea. So as I was preparing for this 338 00:26:30 --> 00:26:34 lecture last night I said, now here I am telling the 6.002 339 00:26:34 --> 00:26:38 gang that you need to learn about analog circuits and 340 00:26:38 --> 00:26:41 resistors and all of that stuff, and you also need to learn 341 00:26:41 --> 00:26:44 about digital systems and all of that stuff. 342 00:26:44 --> 00:26:48 And I said, because these two are very commonplace and often 343 00:26:48 --> 00:26:51 times they occur together. So I said well, 344 00:26:51 --> 00:26:54 if I really believe in my own BS then there should be 345 00:26:54 --> 00:26:57 something around me where I can find both of them 346 00:26:57 --> 00:27:01 instantaneously. So I said let me do the 347 00:27:01 --> 00:27:05 following experiment. Let me close my eyes and reach 348 00:27:05 --> 00:27:09 out and see what I touch. So I closed my eyes, 349 00:27:09 --> 00:27:11 reached out, and guess what? 350 00:27:11 --> 00:27:14 I touched the lonely mouse. The mouse. 351 00:27:14 --> 00:27:17 So I said let me see what is in side the mouse. 352 00:27:17 --> 00:27:21 And if I believe in my BS we should find analog, 353 00:27:21 --> 00:27:25 little components and digital components in there, 354 00:27:25 --> 00:27:28 right? So let's see what is inside the 355 00:27:28 --> 00:27:31 mouse. All right. 356 00:27:31 --> 00:27:34 There we go. Don't try this at home, 357 00:27:34 --> 00:27:40 as with many other things we do in lecture. 358 00:27:40 --> 00:27:52 359 00:27:52 --> 00:27:56 Come on. Show me what I want to see. 360 00:27:56 --> 00:28:00 OK, here we go. Not bad. 361 00:28:00 --> 00:28:06 Let me show you what we have here in this poor shattered 362 00:28:06 --> 00:28:09 mouse. That's my finger, 363 00:28:09 --> 00:28:12 silly. You should recognize this 364 00:28:12 --> 00:28:18 little resistor here. That thing with the little 365 00:28:18 --> 00:28:22 bands, oh, here we go. We'll use this. 366 00:28:22 --> 00:28:27 That's a resistor. And you'll see capacitors in 367 00:28:27 --> 00:28:32 about four weeks. That's a capacitor. 368 00:28:32 --> 00:28:36 And there is a digital IC here. That's a digital IC. 369 00:28:36 --> 00:28:39 That contains a bunch of gates inside it. 370 00:28:39 --> 00:28:42 So this mouse has not made a liar out of me. 371 00:28:42 --> 00:28:47 So what I just showed you was a little device that we use in 372 00:28:47 --> 00:28:51 everyday life that has both analog components and digital 373 00:28:51 --> 00:28:55 components. A large number of devices that 374 00:28:55 --> 00:28:57 we use in daily life are this way. 375 00:28:57 --> 00:29:02 You can do the same thing to your laptop. 376 00:29:02 --> 00:29:06 You could go try it out. And you will find a bunch of 377 00:29:06 --> 00:29:10 analog components and a bunch of digital components. 378 00:29:10 --> 00:29:13 And you really, really need to understand the 379 00:29:13 --> 00:29:17 whole caboodle here. Let me show you a fun little 380 00:29:17 --> 00:29:21 demo involving gates. Now, I want you to be very 381 00:29:21 --> 00:29:23 careful here. Lots of caveats here. 382 00:29:23 --> 00:29:28 If your grandmother asks you how big is a gate don't say this 383 00:29:28 --> 00:29:32 big. This is how big gates used to 384 00:29:32 --> 00:29:35 be, I would say, when they were first invented. 385 00:29:35 --> 00:29:40 When they built gates out of discrete vacuum tubes and so on, 386 00:29:40 --> 00:29:43 this is how big a gate used to be. 387 00:29:43 --> 00:29:46 This is roughly that big. Today in a chip, 388 00:29:46 --> 00:29:49 in a small VLSI, very large scaled integrated 389 00:29:49 --> 00:29:53 circuit in a chip, which is about 1 cm on the 390 00:29:53 --> 00:29:57 side, how many gates do you think I can fit in a thumbnail 391 00:29:57 --> 00:30:01 sized chip? Any guesses? 392 00:30:01 --> 00:30:05 With today's technology, how many gates can I fit on a 393 00:30:05 --> 00:30:07 chip? It has to be more than a 394 00:30:07 --> 00:30:13 million because I just told you that Pentium IV was 20 million 395 00:30:13 --> 00:30:15 and that was a year ago. How many? 396 00:30:15 --> 00:30:20 40 million is a good guess. So on the order of 40 to 80 397 00:30:20 --> 00:30:23 million gates in a 1 square centimeter. 398 00:30:23 --> 00:30:28 Intel just announced that they will be shipping a chip 399 00:30:28 --> 00:30:34 containing 1 billion switches. Remember, this whole thing is a 400 00:30:34 --> 00:30:36 gate, right? Inverter, a resistor and a 401 00:30:36 --> 00:30:39 switch. This thing is a switch. 402 00:30:39 --> 00:30:43 So Intel is going to be shipping something containing a 403 00:30:43 --> 00:30:45 billion of those little elements. 404 00:30:45 --> 00:30:48 Just keep those large numbers in mind. 405 00:30:48 --> 00:30:51 So here is a little circuit that I showed you here, 406 00:30:51 --> 00:30:55 A, B, the NAND gate, the NAND gate at the output and 407 00:30:55 --> 00:30:58 the inverter. So this output A is going to be 408 00:30:58 --> 00:31:04 1 whenever either A or B is off. So the output is a 1 in this 409 00:31:04 --> 00:31:07 case when both A and B are off. I turn A to 1, 410 00:31:07 --> 00:31:11 output is still a 1. So the moment I turn both of 411 00:31:11 --> 00:31:13 these inputs into a 1, these are 1s, 412 00:31:13 --> 00:31:17 the output goes to 0. That's behavior for NAND gate. 413 00:31:17 --> 00:31:21 If I switch any one of the inputs to a 0 the output should 414 00:31:21 --> 00:31:24 go to a 1. Similarly, for the inverter 415 00:31:24 --> 00:31:29 here, when the input is a 0 the output is a 1. 416 00:31:29 --> 00:31:32 And when I switch it so should the output. 417 00:31:32 --> 00:31:35 Now imagine a circuit, a little chip containing 418 00:31:35 --> 00:31:39 billions of these devices. And just imagine all of these 419 00:31:39 --> 00:31:43 1s and 0s flying around. So one simple switch in the 420 00:31:43 --> 00:31:47 input, like a click of a keystroke could actually cause a 421 00:31:47 --> 00:31:51 billion signals in your circuit to be flipping around. 422 00:31:51 --> 00:31:56 And that causes some fun stuff to happen, which we will learn 423 00:31:56 --> 00:32:00 about a few months from now. But for now that's a quick show 424 00:32:00 --> 00:32:05 of a little circuit that looks like that. 425 00:32:05 --> 00:32:12 Let me go back to talking about building other types of gates. 426 00:32:12 --> 00:32:22 427 00:32:22 --> 00:32:25 So that was an inverter. So now you know. 428 00:32:25 --> 00:32:30 You're almost halfway to being able to build a Pentium IV. 429 00:32:30 --> 00:32:35 You've come all the way from nature to gates. 430 00:32:35 --> 00:32:39 And Pentium IV contains 20 million of them so you now know 431 00:32:39 --> 00:32:42 how gates are built. So that's an inverter. 432 00:32:42 --> 00:32:45 Let's look at how we can build other forms of gates. 433 00:32:45 --> 00:32:49 To build another gate let me do this. 434 00:32:49 --> 00:32:59 435 00:32:59 --> 00:33:04 How about this pattern? If I build a pattern like this 436 00:33:04 --> 00:33:11 with A and B coming in here and I put two switches with their 437 00:33:11 --> 00:33:16 inputs in and out, so two switches in series. 438 00:33:16 --> 00:33:22 Let's write down the truth table for what this looks like. 439 00:33:22 --> 00:33:26 Let's see. When A and B are both 0, 440 00:33:26 --> 00:33:31 what should the output be? These are both off so the 441 00:33:31 --> 00:33:34 output is directly VS which is a high. 442 00:33:34 --> 00:33:38 When either of these switches is off 0-1 or 1-0. 443 00:33:38 --> 00:33:42 If either switch is off then this node is cut off from 444 00:33:42 --> 00:33:44 ground. There is no current flowing 445 00:33:44 --> 00:33:47 here. So this entire voltage drops 446 00:33:47 --> 00:33:51 across this infinite resistance here, and so I get 1s at the 447 00:33:51 --> 00:33:55 output as well. If both switches are on what 448 00:33:55 --> 00:33:57 happens? If both A and B are on then I 449 00:33:57 --> 00:34:03 get a short circuit to ground and my output is a 0. 450 00:34:03 --> 00:34:06 So can someone tell me what gate this is? 451 00:34:06 --> 00:34:09 Awesome. We just build a NAND gate. 452 00:34:09 --> 00:34:12 This is unbelievable. Five lectures and you've 453 00:34:12 --> 00:34:18 already come all the way from nature to the primitive building 454 00:34:18 --> 00:34:21 blocks of microprocessors. It's pretty amazing. 455 00:34:21 --> 00:34:25 So what about this one here? 456 00:34:25 --> 00:34:34 457 00:34:34 --> 00:34:38 What's this? I haven't told you this before 458 00:34:38 --> 00:34:45 but if an AND gate becomes a NAND gate, this is kind of an OR 459 00:34:45 --> 00:34:49 arrangement, what should an OR become? 460 00:34:49 --> 00:34:53 NOR. It's all completely logical. 461 00:34:53 --> 00:35:00 So you can go home and practice a truth table for this. 462 00:35:00 --> 00:35:03 A, B and C. I'll just fill in one of the 463 00:35:03 --> 00:35:05 rows. So in this particular 464 00:35:05 --> 00:35:09 situation, if both A and B are 0, if A is 0 and B is 0, 465 00:35:09 --> 00:35:13 both the switches are off, so it's as if this little 466 00:35:13 --> 00:35:17 sucker here is cut off from ground and VS falls across from 467 00:35:17 --> 00:35:22 C to ground here and the output is a 1, so on and so forth. 468 00:35:22 --> 00:35:25 So I can build other interesting forms of gates. 469 00:35:25 --> 00:35:31 So let's say I build something that looks like this. 470 00:35:31 --> 00:35:41 471 00:35:41 --> 00:35:43 I build something like this. 472 00:35:43 --> 00:35:48 473 00:35:48 --> 00:35:53 You can write the truth table for this or you can look at this 474 00:35:53 --> 00:35:57 and write down the function that this one supports. 475 00:35:57 --> 00:36:02 Notice that this output here is going to be a high only when 476 00:36:02 --> 00:36:07 both of these are not connected to ground. 477 00:36:07 --> 00:36:11 And if you stare at it some more the function this one 478 00:36:11 --> 00:36:14 presents, this is my AND function. 479 00:36:14 --> 00:36:19 Suppose this one didn't exist, that would be my AND function. 480 00:36:19 --> 00:36:24 But because this one exists that's in an OR configuration 481 00:36:24 --> 00:36:28 and so I get a C. And so because of that I get 482 00:36:28 --> 00:36:33 something that looks like this. So this is my A dot B, 483 00:36:33 --> 00:36:36 this is my plus because of a parallel here, 484 00:36:36 --> 00:36:40 and ultimately this caused an inversion in this gate. 485 00:36:40 --> 00:36:45 So the primitive pattern has a generic inversion built into the 486 00:36:45 --> 00:36:47 output. That is why they commonly end 487 00:36:47 --> 00:36:52 up building NAND gates and NOR gates and so on as the simplest 488 00:36:52 --> 00:36:54 gates. We don't build AND gates and OR 489 00:36:54 --> 00:36:57 gates. How can I convert this one to 490 00:36:57 --> 00:37:00 an AND gate? Anybody? 491 00:37:00 --> 00:37:04 Put an inverter on the output. So what I can do is take this 492 00:37:04 --> 00:37:07 little sucker here, put an inverter here and I get 493 00:37:07 --> 00:37:10 an AND gate. So the real primitives in 494 00:37:10 --> 00:37:13 circuits tend to be NANDs and NORs. 495 00:37:13 --> 00:37:18 496 00:37:18 --> 00:37:21 OK. So the real practical among you 497 00:37:21 --> 00:37:25 should be saying at this point all right, all right, 498 00:37:25 --> 00:37:28 I buy this, if there existed a switch. 499 00:37:28 --> 00:37:34 I know exactly how to go from nature to building Pentium IVs 500 00:37:34 --> 00:37:39 if there exists a switch. So that the obvious next step 501 00:37:39 --> 00:37:43 for me is to show you a switch, a physical switch device. 502 00:37:43 --> 00:37:47 And to introduce a switch device, let me show you a three 503 00:37:47 --> 00:37:51 terminal element. Remember, the switch has three 504 00:37:51 --> 00:37:55 terminals, an input, output and something called the 505 00:37:55 --> 00:37:58 control, C. So I'm going to introduce a new 506 00:37:58 --> 00:38:03 primitive element called "The MOSFET Device". 507 00:38:03 --> 00:38:08 MOSFET stands for metal-oxide semiconductor field-effect 508 00:38:08 --> 00:38:12 transistor. This is shortened to FET or 509 00:38:12 --> 00:38:16 transistor. Now I'm going to show you that 510 00:38:16 --> 00:38:21 this works like a switch. And before I do that, 511 00:38:21 --> 00:38:27 in fact, let me do that first. Then I'll show you something 512 00:38:27 --> 00:38:30 else. So this device has the 513 00:38:30 --> 00:38:35 following symbol. It has a terminal called a 514 00:38:35 --> 00:38:41 gate, the drain and the source. Gate, drain and source. 515 00:38:41 --> 00:38:46 Three terminals. This is the primitive element 516 00:38:46 --> 00:38:52 that forms virtually every electronic component built 517 00:38:52 --> 00:38:56 today. This is the foundation of the 518 00:38:56 --> 00:39:00 universe. So this little MOSFET device, 519 00:39:00 --> 00:39:06 we can look at how it behaves. I'll show you this thing on the 520 00:39:06 --> 00:39:11 screen in a second, but this guy behaves very much 521 00:39:11 --> 00:39:16 like this device I was postulating earlier. 522 00:39:16 --> 00:39:20 Let's take a look at this device on the scope. 523 00:39:20 --> 00:39:25 To do so let me label some voltages and currents. 524 00:39:25 --> 00:39:30 So let me label this voltage as vDS. 525 00:39:30 --> 00:39:34 Let me label this voltage as vGS between the gate and the 526 00:39:34 --> 00:39:38 source. And let me label the current 527 00:39:38 --> 00:39:41 coming into this node iG. In this device, 528 00:39:41 --> 00:39:45 the physical device that I'm going to show you, 529 00:39:45 --> 00:39:49 the current going into the gate is always 0. 530 00:39:49 --> 00:39:52 So iG is always going to be 0 for 6.002. 531 00:39:52 --> 00:39:58 In real life there is some leakage and so on. 532 00:39:58 --> 00:40:02 But in 6.002 for now we deal with a very simple abstract 533 00:40:02 --> 00:40:06 model, iG is 0. And let me label the current 534 00:40:06 --> 00:40:09 here as iDS. To be correct with the 535 00:40:09 --> 00:40:13 nomenclation, the current into node D should 536 00:40:13 --> 00:40:16 be labeled iD, but because iG is 0 iD flows 537 00:40:16 --> 00:40:21 out through the source as well, so I would simply call it iDS 538 00:40:21 --> 00:40:27 just so that I can show that vDS and iDS are the two voltages and 539 00:40:27 --> 00:40:32 currents that I am going to deal with. 540 00:40:32 --> 00:40:34 So that's my little device here. 541 00:40:34 --> 00:40:38 And notice that the source terminal is common. 542 00:40:38 --> 00:40:42 I use the source both for the control GS and I use the source 543 00:40:42 --> 00:40:47 for the drain as well. So you can view this as input, 544 00:40:47 --> 00:40:50 view this as out, and you can view this, 545 00:40:50 --> 00:40:53 if you like, as the control abstractly. 546 00:40:53 --> 00:40:58 So let me show you a plot of how this behaves. 547 00:40:58 --> 00:41:03 To understand how it behaves, I can draw an equivalent 548 00:41:03 --> 00:41:06 circuit for it. So in this particular 549 00:41:06 --> 00:41:12 situation, if its behavior is characterized by the voltage 550 00:41:12 --> 00:41:16 applied to vGS. Much like the control on the 551 00:41:16 --> 00:41:20 switch, vGS is my control. So if vGS is 0, 552 00:41:20 --> 00:41:24 oh, I'm sorry. If vGS is greater than or equal 553 00:41:24 --> 00:41:31 to some threshold voltage VT -- So vGS, the voltage applied 554 00:41:31 --> 00:41:34 here is greater than some voltage, VT, a threshold 555 00:41:34 --> 00:41:39 voltage, or the pressure of the switch is greater than some 556 00:41:39 --> 00:41:44 threshold pressure then this guy behaves like a short circuit. 557 00:41:44 --> 00:41:47 This is iDS, this is my drain and this is my 558 00:41:47 --> 00:41:50 source. So if the voltage applied 559 00:41:50 --> 00:41:54 between the gate and the source is higher than some threshold 560 00:41:54 --> 00:41:59 then this behaves like a short circuit. 561 00:41:59 --> 00:42:04 Similarly, if the voltage vGS is less than some threshold VT 562 00:42:04 --> 00:42:07 then in that situation -- 563 00:42:07 --> 00:42:13 564 00:42:13 --> 00:42:17 -- I get an open circuit. And when I have an open circuit 565 00:42:17 --> 00:42:21 between D and S then the current iDS is going to be 0. 566 00:42:21 --> 00:42:26 So this is the idealized model. And this idealized model is 567 00:42:26 --> 00:42:30 called "the switch model of the MOSFET". 568 00:42:30 --> 00:42:34 The switch model or the S model of the MOSFET. 569 00:42:34 --> 00:42:39 Well, if you want to see the internals of the MOSFET, 570 00:42:39 --> 00:42:43 I won't cover that in lecture or recitation. 571 00:42:43 --> 00:42:49 You can look at the section, I believe Section 6.7 of the 572 00:42:49 --> 00:42:53 course notes. That has the internal structure 573 00:42:53 --> 00:42:59 of the MOSFET and how you physically construct such a 574 00:42:59 --> 00:43:02 device. So what I can do here is step 575 00:43:02 --> 00:43:06 back and stare at the device for a second or two. 576 00:43:06 --> 00:43:09 And what it says is that if I apply a lot of pressure, 577 00:43:09 --> 00:43:13 if vGS is greater than a threshold VT then I get a short 578 00:43:13 --> 00:43:15 circuit here just like my switch. 579 00:43:15 --> 00:43:18 When in doubt think faucet. If you put pressure on the 580 00:43:18 --> 00:43:21 faucet, think of this as closing, and when I open it, 581 00:43:21 --> 00:43:25 when vGS goes less than VD, less than a threshold, 582 00:43:25 --> 00:43:30 I take off the pressure and then it becomes an open circuit. 583 00:43:30 --> 00:43:34 So I can plot the following. 584 00:43:34 --> 00:43:39 585 00:43:39 --> 00:43:43 Much like I plotted the iV characteristics of two terminal 586 00:43:43 --> 00:43:47 elements, I can plot the iV characteristics of this three 587 00:43:47 --> 00:43:50 terminal element in the following way. 588 00:43:50 --> 00:43:55 I can focus on two terminals and look at vDS and iDS for that 589 00:43:55 --> 00:44:00 terminal pair and draw the curves for how it will behave as 590 00:44:00 --> 00:44:05 I change vGS that I applied. So what I'm going to show you 591 00:44:05 --> 00:44:10 is that if vGS is less than a threshold then this behaves like 592 00:44:10 --> 00:44:13 a open circuit. So no matter what the voltage 593 00:44:13 --> 00:44:17 is the current is 0. Similarly, if vGS greater than 594 00:44:17 --> 00:44:23 equal to some threshold voltage then I get the behavior iV curve 595 00:44:23 --> 00:44:27 of a short circuit where the current can be anything and 596 00:44:27 --> 00:44:33 controlled by external forces like in any short circuit. 597 00:44:33 --> 00:44:35 So let me show you on the screen. 598 00:44:35 --> 00:44:38 Lorenzo has kindly put the graph up already. 599 00:44:38 --> 00:44:41 So I'm showing the iV curve of a switch. 600 00:44:41 --> 00:44:45 Notice that when vGS is greater than VT, greater than a 601 00:44:45 --> 00:44:50 threshold I get the vertical line corresponding to a short 602 00:44:50 --> 00:44:52 circuit. Is it this one? 603 00:44:52 --> 00:44:53 This one. There we go. 604 00:44:53 --> 00:44:58 So what I'm going to do here is I'm going to reduce vGS to below 605 00:44:58 --> 00:45:02 VT. What should you see happening? 606 00:45:02 --> 00:45:05 The curve, from being a short circuit, should hammer down to 607 00:45:05 --> 00:45:09 becoming an open circuit. That's the curve for an open 608 00:45:09 --> 00:45:11 circuit as I drew out there for you. 609 00:45:11 --> 00:45:14 VGS pressure ain't enough. Lots of pressure, 610 00:45:14 --> 00:45:18 boom, it's a short circuit. I really like to think of this 611 00:45:18 --> 00:45:22 pressure analogy if I get confused whenever I look at a 612 00:45:22 --> 00:45:26 MOS transistor and I need to look at vGS and so on I always 613 00:45:26 --> 00:45:30 think vGS is greater than VT. Lots of pressure on the switch 614 00:45:30 --> 00:45:32 it turns on. Just remember that, 615 00:45:32 --> 00:45:35 and then you won't forget this vGS thing here. 616 00:45:35 --> 00:45:37 So that's the behavior of a switch. 617 00:45:37 --> 00:45:40 And so viola, there's our switch. 618 00:45:40 --> 00:45:45 619 00:45:45 --> 00:45:48 So I've given you a three terminal element that is a 620 00:45:48 --> 00:45:51 switch that is controlled like a mechanical switch. 621 00:45:51 --> 00:45:54 So I can build a, if I replace -- 622 00:45:54 --> 00:46:02 623 00:46:02 --> 00:46:07 This was my switch earlier. And what I can do is replace 624 00:46:07 --> 00:46:11 this with my MOSFET and that's what I get. 625 00:46:11 --> 00:46:16 And I won't bother showing you this is your inverter. 626 00:46:16 --> 00:46:22 All of that has replaced the abstract switch with a physical 627 00:46:22 --> 00:46:28 switch which behaves as shown in the graph up there. 628 00:46:28 --> 00:46:35 And so I apply an input here and I take the output here. 629 00:46:35 --> 00:46:42 So as 6.002 you could look at this and say ah-ha, 630 00:46:42 --> 00:46:48 that is an inverter. When you go to 004 what you 631 00:46:48 --> 00:46:57 will do is build this triangle and a circle around it and you 632 00:46:57 --> 00:47:05 will ignore what's inside and just look at that. 633 00:47:05 --> 00:47:08 So in 002 we showed you that the internals look like a 634 00:47:08 --> 00:47:12 pattern with a MOSFET and a resistor, but it's really the 635 00:47:12 --> 00:47:16 abstract inverter looking in from the outside. 636 00:47:16 --> 00:47:20 I'm just going to close the loop inside the digital gate, 637 00:47:20 --> 00:47:24 and this was inside your little inverter with a resistor and a 638 00:47:24 --> 00:47:27 switch. Let me continue with this for a 639 00:47:27 --> 00:47:30 little longer here -- 640 00:47:30 --> 00:47:41 641 00:47:41 --> 00:47:45 -- and do something that we like to do a lot, 642 00:47:45 --> 00:47:50 which is plot what are called input / output curves. 643 00:47:50 --> 00:47:56 So let's say the voltage applied here is v in and let's 644 00:47:56 --> 00:48:00 call this v out. For fun let's plot a v in 645 00:48:00 --> 00:48:07 versus v out for this inverter. So when input is a 0, 646 00:48:07 --> 00:48:11 let's say VT is 1 volt for the inverter. 647 00:48:11 --> 00:48:14 The threshold voltage is 1 volt. 648 00:48:14 --> 00:48:18 The threshold pressure is 1 volt. 649 00:48:18 --> 00:48:23 So when input is a 0, and let's say VS is 5 volts. 650 00:48:23 --> 00:48:30 So when the input is a 0, this guy is turned off. 651 00:48:30 --> 00:48:34 So what's the output? What's the output voltage? 652 00:48:34 --> 00:48:38 If this is turned off, what's the output voltage? 653 00:48:38 --> 00:48:42 It's the supply. The supply directly shows up 654 00:48:42 --> 00:48:45 here. And so as long as the input is 655 00:48:45 --> 00:48:49 0 the output is at 5 volts. And this is true until the 656 00:48:49 --> 00:48:54 input reaches 1 volt. As long as the input is less 657 00:48:54 --> 00:48:58 than 1 volt my output stays high. 658 00:48:58 --> 00:49:03 And then when my input exceeds or hits 1 volt then at that 659 00:49:03 --> 00:49:09 point the switch turns on and the MOSFET turns on and shorts 660 00:49:09 --> 00:49:15 the output to ground in which case boom, this is what I get. 661 00:49:15 --> 00:49:19 And then, no matter how much I increase the input, 662 00:49:19 --> 00:49:25 my switch stays on and the output follows a zero volts at 663 00:49:25 --> 00:49:29 the output. So this is my v in versus v out 664 00:49:29 --> 00:49:36 curve for the inverter. One of the interesting things 665 00:49:36 --> 00:49:42 that we do a lot is see whether this satisfies some voltage 666 00:49:42 --> 00:49:46 threshold. So let's say I have a VOL of 667 00:49:46 --> 00:49:51 0.5 volts, VOH of 4.5, VIL of 0.9 and VIH of 4.1 668 00:49:51 --> 00:49:55 volts. So VOL says in its low value is 669 00:49:55 --> 00:50:01 the output less than 0.5? Yup, output less than 0.5. 670 00:50:01 --> 00:50:03 In its high is it more than 4.5? 671 00:50:03 --> 00:50:08 Yup, it's more than 4.5. Does it recognize all values 672 00:50:08 --> 00:50:10 below VIL as a low input? Yup. 673 00:50:10 --> 00:50:15 So anything below 0.9 or 1 for that matter is viewed as a low. 674 00:50:15 --> 00:50:18 That's good. So these pass. 675 00:50:18 --> 00:50:22 And high, anything above 4.1, is that treated as a high? 676 00:50:22 --> 00:50:25 Yes. So anything above 4.1 is 677 00:50:25 --> 00:50:30 treated as a high and the output goes low. 678 00:50:30 --> 00:50:34 So therefore this inverter that I've designed for you here 679 00:50:34 --> 00:50:39 satisfies the static discipline and this inverter can be used in 680 00:50:39 --> 00:50:44 circuits or other devices that conform to this value here. 681 00:50:44 --> 00:50:48 In your recitation, you will look at a slightly 682 00:50:48 --> 00:50:53 more detailed model of the switch where the switch behaves 683 00:50:53 --> 50:56 like a resistor.