| 1 |
Course overview and mechanics, basics of information |
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| 2 |
Digital abstraction, combinational logic, voltage-based encoding |
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| 3 |
CMOS technology, gate design, timing |
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| 4 |
Canonical forms; synthesis, simplification |
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| 5 |
Sequential logic |
Lab 1 (CMOS) due |
Quiz 1 |
| 6 |
Storage elements, finite state machines |
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| 7 |
Synchronization, metastability |
Lab 2 (Adder) due |
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| 8 |
Pipelining; throughput and latency |
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| 9 |
Case study: multipliers |
Lab 3 (ALU) due |
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| 10 |
Beta instruction set architecture, compilation |
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Quiz 2 |
| 11 |
Machine language programming issues |
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| 12 |
Models of computation, programmable architectures |
Lab 4 (Turing machine) due |
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| 13 |
Stacks and procedures |
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| 14 |
Non-pipelined Beta implementation |
Lab 5 (Assembly language) due |
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| 15 |
Multilevel memories; locality, performance, caches |
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| 16 |
Cache design issues |
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Quiz 3 |
| 17 |
Virtual memory: mapping, protection, contexts |
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| 18 |
Virtual machines: timesharing, OS kernels, supervisor calls |
Lab 6 (Beta) due |
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| 19 |
Devices and interrupt handlers, preemptive interrupts, real-time issues |
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| 20 |
Communication issues: busses, networks, protocols |
Lab 7 (Trap handler) due |
Quiz 4 |
| 21 |
Communicating processes: semaphores, synchronization, atomicity, deadlock |
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| 22 |
Pipelined Beta implementation, bypassing |
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| 23 |
Pipeline issues: delay slots, annulment, exceptions |
Lab 8 (Tiny OS) due |
Quiz 5 |
| 24 |
Parallel processing, shared memory, cache coherence, consistency criteria |
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| 25 |
Wrapup lecture |
Project due |
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