* test vectors for debugging Beta register file circuitry

* allow verification, but not a real checkin
.checkoff "" "Lab #6: regfile" 0

Xregfile clk werf ra2sel rega[4:0] regb[4:0] regc[4:0] wdata[31:0] radata[31:0] rbdata[31:0] regfile

Vclk clk 0 pulse(3.3,0,49.9ns,.1ns,.1ns,49.9ns,100ns)

Wra2sel ra2sel nrz(0,3.3,100n,0n,.1n,.1n)
// see if R31 reads as 0
+ 0 1
// fill up the regfile and read it back
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0
// make sure ra2sel works okay
+ 1 0 1

Wrega rega[4:0] nrz(0,3.3,100n,0n,.1n,.1n)
// see if R31 reads as 0
+ 31 31
// fill up the regfile and read it back
+ 0  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14
+15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+31  0
// make sure ra2sel works okay
+ 5 12 23

Wregb regb[4:0] nrz(0,3.3,100n,0n,.1n,.1n)
// see if R31 reads as 0
+ 31 0
// fill up the regfile and read it back
+ 0  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14
+15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+31 0
// make sure ra2sel works okay
+ 7  9 11

Wregc regc[4:0] nrz(0,3.3,100n,0n,.1n,.1n)
// see if R31 reads as 0
+ 0 31
// fill up the regfile and read it back
+ 0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ 0  0
// make sure ra2sel works okay
+ 8 10 12


Wwerf werf nrz(0,3.3,100n,0n,.1n,.1n)
// see if R31 reads as 0
+ 0 0
// fill up the regfile and read it back
+ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+ 0 0
// make sure ra2sel works okay
+ 0 0 0

Wwdata wdata[31:0] nrz(0,3.3,100n,0n,.1n,.1n)
// see if R31 reads as 0
+ 0 0
// fill up the regfile and read it back
+ 0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+31 31
// make sure ra2sel works okay
+ 0 0 0

.verify radata[31:0] tvpairs()
// see if R31 reads as 0
+   99n 0x0
+  199n 0x0
// fill up the regfile and read it back
// +299n ???  -- not written yet!
+  399n 0
+  499n 1
+  599n 2
+  699n 3
+  799n 4
+  899n 5
+  999n 6
+ 1099n 7
+ 1199n 8
+ 1299n 9
+ 1399n 10
+ 1499n 11
+ 1599n 12
+ 1699n 13
+ 1799n 14
+ 1899n 15
+ 1999n 16
+ 2099n 17
+ 2199n 18
+ 2299n 19
+ 2399n 20
+ 2499n 21
+ 2599n 22
+ 2699n 23
+ 2799n 24
+ 2899n 25
+ 2999n 26
+ 3099n 27
+ 3199n 28
+ 3299n 29
+ 3399n 30
+ 3499n 0
+ 3599n 0
+ 3699n 5
+ 3799n 12
+ 3899n 23

.verify rbdata[31:0] tvpairs()
// see if R31 reads as 0
+ 99n 0x0
+ 199n 0x0
// fill up the regfile and read it back
// +299n ???  -- not written yet!
+  399n 0
+  499n 1
+  599n 2
+  699n 3
+  799n 4
+  899n 5
+  999n 6
+ 1099n 7
+ 1199n 8
+ 1299n 9
+ 1399n 10
+ 1499n 11
+ 1599n 12
+ 1699n 13
+ 1799n 14
+ 1899n 15
+ 1999n 16
+ 2099n 17
+ 2199n 18
+ 2299n 19
+ 2399n 20
+ 2499n 21
+ 2599n 22
+ 2699n 23
+ 2799n 24
+ 2899n 25
+ 2999n 26
+ 3099n 27
+ 3199n 28
+ 3299n 29
+ 3399n 30
+ 3499n 0
+ 3599n 0
+ 3699n 8
+ 3799n 9
+ 3899n 12

* Run the simulation
.tran 3900ns

* Some useful plots... you can plot additional signals by specifying
* the appropriate .plot commands in your main netlist file.

.plot clk
.plot werf
.plot ra2sel
.plot rega[4:0]
.plot regb[4:0]
.plot regc[4:0]
.plot wdata[31:0]
.plot radata[31:0]
.plot rbdata[31:0]