Model { Name "ps10b_2" Version 5.1 SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off SortedOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Mon May 10 21:11:38 2004" Creator "krsanta" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "krsanta" ModifiedDateFormat "%" LastModifiedDate "Tue May 11 13:08:54 2004" ModelVersionFormat "1.%" ConfigurationManager "None" SimParamPage "Solver" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock off BufferReuse on RTWExpressionDepthLimit 5 SimulationMode "normal" Solver "ode45" SolverMode "Auto" StartTime "0.0" StopTime "10.0" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "auto" RelTol "1e-3" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" SignalLoggingName "sigsOut" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ConditionallyExecuteInputs on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on AssertionControl "UseLocalSettings" ProdHWDeviceType "Microprocessor" ProdHWWordLengths "8,16,32,32" RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off TLCAssertion off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Demux Outputs "4" DisplayOption "none" BusSelectionMode off } Block { BlockType Inport Port "1" PortDimensions "-1" ShowAdditionalParam off LatchInput off DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Mux Inputs "4" DisplayOption "none" } Block { BlockType Outport Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType StateSpace A "1" B "1" C "1" D "1" X0 "0" AbsoluteTolerance "auto" Realization "auto" } Block { BlockType Sum IconShape "rectangular" Inputs "++" ShowAdditionalParam off InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType TransferFcn Numerator "[1]" Denominator "[1 2 1]" AbsoluteTolerance "auto" Realization "auto" } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "ps10b_2" Location [211, 517, 1162, 955] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Inport Name "w1" Position [15, 173, 45, 187] } Block { BlockType Inport Name "w2" Position [510, 133, 540, 147] Port "2" } Block { BlockType Demux Name "Demux" Ports [1, 2] Position [160, 91, 165, 129] BackgroundColor "black" ShowName off Outputs "2" } Block { BlockType Demux Name "Demux1" Ports [1, 2] Position [420, 81, 425, 119] BackgroundColor "black" ShowName off Outputs "2" } Block { BlockType Demux Name "Demux2" Ports [1, 2] Position [660, 41, 665, 79] BackgroundColor "black" ShowName off Outputs "2" } Block { BlockType Demux Name "Demux3" Ports [1, 2] Position [845, 91, 850, 129] BackgroundColor "black" ShowName off Outputs "2" } Block { BlockType Mux Name "Mux" Ports [2, 1] Position [265, 171, 270, 209] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType TransferFcn Name "P0" Position [400, 162, 460, 198] Numerator "[1 -2]" Denominator "[1 0 -1]" } Block { BlockType StateSpace Name "State-Space" Position [80, 93, 140, 127] A "-1" C "[1;-1]" D "[0;1]" } Block { BlockType StateSpace Name "State-Space1" Position [340, 83, 400, 117] A "-1" C "[1;-1]" D "[0;1]" } Block { BlockType StateSpace Name "State-Space2" Position [580, 43, 640, 77] A "-1" C "[1;-1]" D "[0;1]" } Block { BlockType StateSpace Name "State-Space3" Position [765, 93, 825, 127] A "-1" C "[1;-1]" D "[0;1]" } Block { BlockType StateSpace Name "State-Space4" Position [295, 163, 355, 197] A "Ak" B "Bk" C "Ck" D "Dk" } Block { BlockType Sum Name "Sum1" Ports [2, 1] Position [695, 170, 715, 190] ShowName off IconShape "round" Inputs "++|" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum2" Ports [2, 1] Position [760, 170, 780, 190] ShowName off IconShape "round" Inputs "|+-" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType TransferFcn Name "W0 " Position [115, 162, 175, 198] Numerator "[20.5]" Denominator "[20 1]" } Block { BlockType TransferFcn Name "W2" Position [615, 122, 675, 158] Numerator "[.1375 .1375]" Denominator "[1 10]" } Block { BlockType Outport Name "y1" Position [195, 88, 225, 102] } Block { BlockType Outport Name "y2" Position [195, 123, 225, 137] Port "2" } Block { BlockType Outport Name "y3" Position [455, 78, 485, 92] Port "3" } Block { BlockType Outport Name "y4" Position [455, 113, 485, 127] Port "4" } Block { BlockType Outport Name "y5" Position [695, 38, 725, 52] Port "5" } Block { BlockType Outport Name "y6" Position [695, 73, 725, 87] Port "6" } Block { BlockType Outport Name "y7" Position [880, 88, 910, 102] Port "7" } Block { BlockType Outport Name "y8" Position [880, 123, 910, 137] Port "8" } Line { SrcBlock "State-Space" SrcPort 1 DstBlock "Demux" DstPort 1 } Line { SrcBlock "w1" SrcPort 1 Points [0, -25] Branch { Points [0, -45] DstBlock "State-Space" DstPort 1 } Branch { Points [0, 25] DstBlock "W0 " DstPort 1 } } Line { SrcBlock "Demux" SrcPort 1 Points [10, 0] DstBlock "y1" DstPort 1 } Line { SrcBlock "Demux" SrcPort 2 Points [5, 0; 0, 10] DstBlock "y2" DstPort 1 } Line { SrcBlock "W0 " SrcPort 1 Points [25, 0] Branch { Points [0, 160; 565, 0] DstBlock "Sum2" DstPort 2 } Branch { DstBlock "Mux" DstPort 1 } } Line { SrcBlock "State-Space1" SrcPort 1 DstBlock "Demux1" DstPort 1 } Line { SrcBlock "Demux1" SrcPort 1 Points [10, 0] DstBlock "y3" DstPort 1 } Line { SrcBlock "Demux1" SrcPort 2 Points [5, 0; 0, 10] DstBlock "y4" DstPort 1 } Line { SrcBlock "State-Space2" SrcPort 1 DstBlock "Demux2" DstPort 1 } Line { SrcBlock "Demux2" SrcPort 1 Points [10, 0] DstBlock "y5" DstPort 1 } Line { SrcBlock "Demux2" SrcPort 2 Points [5, 0; 0, 10] DstBlock "y6" DstPort 1 } Line { SrcBlock "w2" SrcPort 1 Points [15, 0] Branch { Points [5, 0] DstBlock "State-Space2" DstPort 1 } Branch { DstBlock "W2" DstPort 1 } } Line { SrcBlock "W2" SrcPort 1 Points [25, 0] DstBlock "Sum1" DstPort 1 } Line { SrcBlock "P0" SrcPort 1 DstBlock "Sum1" DstPort 2 } Line { SrcBlock "Sum1" SrcPort 1 Points [10, 0] Branch { DstBlock "Sum2" DstPort 1 } Branch { Points [5, 0; 0, 80; -485, 0] DstBlock "Mux" DstPort 2 } } Line { SrcBlock "State-Space3" SrcPort 1 DstBlock "Demux3" DstPort 1 } Line { SrcBlock "Demux3" SrcPort 1 Points [10, 0] DstBlock "y7" DstPort 1 } Line { SrcBlock "Demux3" SrcPort 2 Points [5, 0; 0, 10] DstBlock "y8" DstPort 1 } Line { SrcBlock "Sum2" SrcPort 1 Points [10, 0; 0, -30; -60, 0; 0, -40] DstBlock "State-Space3" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 Points [0, -10] DstBlock "State-Space4" DstPort 1 } Line { SrcBlock "State-Space4" SrcPort 1 Points [0, -5] Branch { Points [0, -40; -35, 0] DstBlock "State-Space1" DstPort 1 } Branch { Points [0, 5] DstBlock "P0" DstPort 1 } } } }