| L1 |
History of Calculation and Computer Architecture (A) |
Self-assessment test (A) |
| L2 |
Influence of Technology and Software on Instruction Sets: Up to the Dawn of IBM 360 (A) |
|
| L3 |
Complex Instruction Set Evolution in the Sixties: Stack and GPR Architectures (A) |
Self-assessment test due (A) |
| T1 |
Self-assessment Test and ISA |
|
| L4 |
Microprogramming (A) |
|
| T2 |
MIPS ISA, Bus-based Implementation, and Microprogramming |
|
| L5 |
Simple Instruction Pipelining (A) |
|
| L6 |
Pipeline Hazards (A) |
|
| T3 |
Microprogramming, Pipelining, and Hazards |
|
| L7 |
Multilevel Memories - Technology (J) |
|
| L8 |
Cache (Memory) Performance Optimization (J) |
|
| Q1 |
ISAs, Microprogramming, Simple Pipelining and Hazards |
|
| L9 |
Virtual Memory Basics (J) |
|
| T4 |
Quiz 1, Caches, and Virtual Memory Basics |
|
| L10 |
Virtual Memory: Part Deux (A) |
|
| L11 |
Complex Pipelining (A) |
|
| Q2 |
Caches, Virtual Memory |
|
| L12 |
Out of Order Execution and Register Renaming (A) |
|
| L13 |
Branch Prediction and Speculative Execution (A) |
|
| T5 |
Quiz 2, Scoreboarding, Register Renaming, and Branch Prediction |
|
| L14 |
Advanced Superscalar Architectures (J) |
|
| L15 |
Microprocessor Evolution: 4004 to Pentium 4 (J) |
|
| Q3 |
Complex Pipelines |
|
| L16 |
Synchronization and Sequential Consistency (A) |
|
| L17 |
Cache Coherence (A) |
|
| L18 |
Cache Coherence (Implementation) (A) |
|
| L19 |
Snoopy Protocols (A) |
|
| T6 |
Sequential Consistency, Synchronization, Cache Coherence Protocols |
|
| L20 |
Relaxed Memory Models (A) |
|
| Q4 |
SMPs, CC, Synch, Memory Models |
|
| L21 |
VLIW/EPIC: Statically Scheduled ILP (J) |
|
| L22 |
Vector Computers (J) |
|
| T7 |
Quiz 4 and VLIW |
|
| L23 |
Multithreaded Processors (J) |
|
| L24 |
Reliable Architectures (J) |
|
| T8 |
Vector Computers, Multithreading and Reliable Architectures |
|
| L25 |
Virtual Machines (J) |
|
| Q5 |
VLIW/Vector/Threads |
|
