|1||RTL Model of a Two-Stage MIPS Processor (PDF)|
|2||ASIC Implementation of a Two-Stage MIPS Processor (PDF)|
|3||Bluespec Model of a Network Linecard (PDF)|
See the calendar for due dates and the syllabus for class policies on turning in labs and collaboration. The SMIPS Processor Specification contains details on the SMIPS ISA which is used in several of the labs.