|Final Completed Project||25%|
Lectures: 3 sessions/ week, 1.5 hours / session
Students should feel comfortable programming and using computers. A rudimentary knowledge of basic logic design (6.004) is assumed. Additional circuit-level (6.002 or 6.374) and architecture-level knowledge (6.823) would be useful but is not essential. As with all project courses the end of term crunch can be a problem, so it would be unwise to take this course with another which also has a significant design project due at the end of the term.
Lectures will be from 1:00 PM to 2:30 PM every Monday, Wednesday, and Friday. Some class sessions are designated as tutorials. In the second half of the term each project team will be expected to meet once per week with the instructors. These meetings will be scheduled during the normal lecture times.
Grades will be based on the labs, one quiz, project milestones, and the final completed project.
|Final Completed Project||25%|
There will be 3 to 5 labs all due before the first quiz. These labs are designed to help you learn the skills you'll need to complete the final project. Some of the labs are probably too long to be done the night before the due date, so plan accordingly. Late labs will not be accepted. See the calendar for details on when labs are due. Feel free to get help from others, but the work you hand in should be your own.
There will be one 90 minute quiz on the day of lecture 15 in class. The quiz will cover all of the material to date. The quiz is closed book. If exceptional circumstances make it impossible to take the quiz at the scheduled time, please contact the course staff before the quiz to see if other arrangements can be made. Requests for make-ups after the quiz has been given are unlikely to be successful. There is no final exam.
Projects will be done in groups of 2 to 3 students, and each team will have one meeting with the instructors each week. Several milestone reports (one to two pages) will be due each Friday following spring break. These milestone reports are (0) Preliminary Project Proposals, (1) Project Proposal, (2) High-level Micro Architecture, (3) Test Strategy, (4) Initial Design, (5) Design Exploration. Final project presentations will take place during the last week of classes. The final report (15 to 20 pages) is due 2 days after project session 13. There are no extensions.
This course is worth 8 Engineering Design Points (EDPs).
The computer lab for this course is open 24 hours a day. The lab access code will be given out in class. If you have forgotten the code then please contact the course staff. The lab contains 20+ high-end workstations donated by Intel.
Students must not discuss a quiz's contents with other students who have not yet taken the quiz. If prior to taking it, you are inadvertently exposed to material in a quiz - by whatever means - you must immediately inform the instructor or a TA. Collaboration amongst students to understand the course material is strongly encouraged.
The TAs and instructors can be reached for questions, comments, etc. via email.
6.884 or 6.823 (but not both) can satisfy one of your TQE requirements for the Systems Group. In future years, 6.884 will replace 6.371 but until then you will need to fill out a petition to use 6.884 as part of your TQE. Visit the Graduate Office to pick up a petition and then have one of the course instructors sign it.