WEBVTT 00:00:00.000 --> 00:00:02.430 The following content is provided under a Creative 00:00:02.430 --> 00:00:03.730 Commons license. 00:00:03.730 --> 00:00:06.030 Your support will help MIT OpenCourseWare 00:00:06.030 --> 00:00:10.060 continue to offer high-quality educational resources for free. 00:00:10.060 --> 00:00:12.690 To make a donation or to view additional materials 00:00:12.690 --> 00:00:16.560 from hundreds of MIT courses, visit MIT OpenCourseWare 00:00:16.560 --> 00:00:17.904 at ocw.mit.edu. 00:00:21.500 --> 00:00:24.770 DUANE BONING: The first problem set is out, 00:00:24.770 --> 00:00:27.890 and I should let you know that Hayden is watching out 00:00:27.890 --> 00:00:33.010 for you, because we actually trimmed off one 00:00:33.010 --> 00:00:36.470 problem from past problem sets. 00:00:36.470 --> 00:00:40.000 So this is a little bit of a revamp from the past, 00:00:40.000 --> 00:00:42.160 and slightly shorter. 00:00:42.160 --> 00:00:47.530 So the trade-off is maybe asking slightly fewer questions, 00:00:47.530 --> 00:00:49.600 but then emphasizing a little bit 00:00:49.600 --> 00:00:57.120 more the discussive responses from you on the problem set. 00:00:57.120 --> 00:00:58.710 As we talked about last time, we'd 00:00:58.710 --> 00:01:02.970 really like a little bit of textual description 00:01:02.970 --> 00:01:07.960 from you about the problem and your thought processes 00:01:07.960 --> 00:01:10.730 on those. 00:01:10.730 --> 00:01:14.600 OK, good-- so let's start with today. 00:01:14.600 --> 00:01:19.802 If you recall, Tuesday was the broad overview, 00:01:19.802 --> 00:01:21.260 a little bit of the outline of what 00:01:21.260 --> 00:01:23.360 we're going to be seeing throughout the course 00:01:23.360 --> 00:01:24.620 of the semester. 00:01:24.620 --> 00:01:28.070 Today I'm going to focus in a little bit on semiconductor 00:01:28.070 --> 00:01:32.390 process technology, but with a real emphasis on variation 00:01:32.390 --> 00:01:34.460 in semiconductor processes. 00:01:34.460 --> 00:01:40.750 And the basic agenda here is give you a very quick-- 00:01:40.750 --> 00:01:44.120 I think it's a four-slide process summary 00:01:44.120 --> 00:01:45.980 of a typical process sequence. 00:01:45.980 --> 00:01:47.680 It's going to be a bit stylized. 00:01:50.810 --> 00:01:53.030 Another reading assignment that is coming, 00:01:53.030 --> 00:01:56.000 but I have not quite issued yet in order 00:01:56.000 --> 00:02:00.110 to give you some room to work on problem set 1, will be chapter 00:02:00.110 --> 00:02:07.280 2 of May and Spanos, which is a fairly nice condensed, but good 00:02:07.280 --> 00:02:11.030 enough depth and detail description of semiconductor 00:02:11.030 --> 00:02:12.690 process technology. 00:02:12.690 --> 00:02:18.660 So it is an excellent 50-page, 30 to-- 00:02:18.660 --> 00:02:22.025 well, I guess chapter 2 is about something like 50 pages-- 00:02:25.080 --> 00:02:28.740 nice introduction to and some details 00:02:28.740 --> 00:02:31.308 on semiconductor processing. 00:02:31.308 --> 00:02:33.600 But what I want to do is set a little bit of a baseline 00:02:33.600 --> 00:02:39.690 to make sure everybody has a course picture of what 00:02:39.690 --> 00:02:41.880 is involved in making integrated circuits, 00:02:41.880 --> 00:02:45.090 since that is going to be one of the processes 00:02:45.090 --> 00:02:47.770 that we use to illustrate lots of things. 00:02:47.770 --> 00:02:51.030 And so what I'm going to talk a little bit about after going-- 00:02:51.030 --> 00:02:53.400 flying through the whole process sequence 00:02:53.400 --> 00:02:54.870 is some of the types of variation 00:02:54.870 --> 00:02:57.930 that arise in microfabrication, with emphasis 00:02:57.930 --> 00:03:00.030 on parametric variation. 00:03:00.030 --> 00:03:03.780 And then we'll talk a little bit about temporal variation-- 00:03:03.780 --> 00:03:07.920 run to run, wafer to wafer, if you will-- 00:03:07.920 --> 00:03:10.260 and then spatial variations. 00:03:10.260 --> 00:03:13.440 And semiconductor processing is an interesting one, 00:03:13.440 --> 00:03:16.860 because there are nesting of replication 00:03:16.860 --> 00:03:21.240 of the products within additional geometric 00:03:21.240 --> 00:03:21.970 structures. 00:03:21.970 --> 00:03:24.180 So we'll talk about that a little bit. 00:03:24.180 --> 00:03:28.650 And then what we'll be doing mixed in with the discussion 00:03:28.650 --> 00:03:31.530 of these types of variation is trying 00:03:31.530 --> 00:03:34.800 to give you a little bit of a preview, some examples drawn 00:03:34.800 --> 00:03:39.360 from both the literature and some of the research 00:03:39.360 --> 00:03:42.145 that my group has been doing over the last 10 years or so. 00:03:42.145 --> 00:03:43.770 We'll try to give you a preview of some 00:03:43.770 --> 00:03:46.110 of the kinds of manufacturing control techniques 00:03:46.110 --> 00:03:48.090 that we'll be diving in much more detail 00:03:48.090 --> 00:03:49.360 throughout the term. 00:03:49.360 --> 00:03:51.390 So we'll see a little bit early on 00:03:51.390 --> 00:03:54.960 about basic statistical analysis, trying to decide, 00:03:54.960 --> 00:03:58.410 is there something varying here or not-- 00:03:58.410 --> 00:04:01.410 basic detection and analysis of that. 00:04:01.410 --> 00:04:03.960 Then we'll talk a little bit about process modeling, 00:04:03.960 --> 00:04:06.150 especially from an empirical point of view, 00:04:06.150 --> 00:04:10.500 and a little bit of the boundary between physical modeling 00:04:10.500 --> 00:04:12.180 and empirical modeling. 00:04:12.180 --> 00:04:14.350 I'll give you a little example of that. 00:04:14.350 --> 00:04:16.620 And then we'll talk about using those kinds of models 00:04:16.620 --> 00:04:20.279 for process optimization and some of the kinds of strategies 00:04:20.279 --> 00:04:23.640 that arise to have robust designs-- 00:04:23.640 --> 00:04:27.480 and then lastly, a very simple example of feedback 00:04:27.480 --> 00:04:32.400 control in a unit process in semiconductor fabrication. 00:04:35.510 --> 00:04:39.890 So the following is from a book. 00:04:39.890 --> 00:04:40.890 It's a little bit dated. 00:04:40.890 --> 00:04:42.810 About 10 years old. 00:04:42.810 --> 00:04:44.460 It's actually an interesting book, 00:04:44.460 --> 00:04:46.410 because it's about statistical case 00:04:46.410 --> 00:04:49.290 studies in industrial process improvement, where 00:04:49.290 --> 00:04:51.450 almost all of the cases are really 00:04:51.450 --> 00:04:54.740 drawn from the semiconductor industry. 00:04:54.740 --> 00:04:57.630 So before they dive into those statistical methods, 00:04:57.630 --> 00:05:00.630 they themselves give a very quick overview 00:05:00.630 --> 00:05:02.950 of the semiconductor fabrication process. 00:05:02.950 --> 00:05:05.490 So I like this example or this-- 00:05:05.490 --> 00:05:11.310 I think there's three or four slides that have a sequence-- 00:05:11.310 --> 00:05:15.330 a little bit because it's fairly simplified and abstracted, 00:05:15.330 --> 00:05:17.170 so we can go through it quickly. 00:05:17.170 --> 00:05:21.480 But the real reason I love this is there are mistakes in it. 00:05:21.480 --> 00:05:25.680 There are errors, things that don't necessarily make 00:05:25.680 --> 00:05:30.540 physical sense or don't quite-- 00:05:30.540 --> 00:05:33.030 well, a lot of this is, of course, 00:05:33.030 --> 00:05:36.300 simplification of the process to get it down to something 00:05:36.300 --> 00:05:38.010 easy, but even in that-- 00:05:38.010 --> 00:05:40.350 with that caveat, there's things that 00:05:40.350 --> 00:05:42.270 are just-- don't quite line up. 00:05:42.270 --> 00:05:47.640 So your challenge is to try to point out to me, 00:05:47.640 --> 00:05:50.280 as we go through it, what can't be right-- 00:05:53.860 --> 00:05:56.310 even if you don't have a lot of semiconductor background. 00:05:56.310 --> 00:05:57.810 So let's see if you can catch these. 00:06:00.485 --> 00:06:02.485 Actually, let's see if I can skip ahead briefly. 00:06:08.670 --> 00:06:10.500 I'm skipping to the end of the sequence. 00:06:10.500 --> 00:06:12.240 This is step 25. 00:06:12.240 --> 00:06:16.290 What we're showing here is the fabrication sequence 00:06:16.290 --> 00:06:19.440 of building up thin films on the surface of the wafer, 00:06:19.440 --> 00:06:23.730 as well as changing the material properties of parts 00:06:23.730 --> 00:06:27.510 of the surface of the wafer, scoped in or zoomed 00:06:27.510 --> 00:06:31.860 in to trying to build a single transistor. 00:06:31.860 --> 00:06:35.280 Now, there are people that build and sell single transistors, 00:06:35.280 --> 00:06:37.680 but really we're talking integrated circuits. 00:06:37.680 --> 00:06:42.390 At the ICC Conference earlier this week, 00:06:42.390 --> 00:06:48.240 Intel announced their 2 billion transistor microprocessor. 00:06:48.240 --> 00:06:50.910 So that's the level of integration 00:06:50.910 --> 00:06:52.110 that's out there now. 00:06:52.110 --> 00:06:54.090 We're going to focus on one. 00:06:54.090 --> 00:06:56.940 Clearly, when we talk a little bit later, 00:06:56.940 --> 00:07:01.800 part of the challenge is to build a product with 2 billion 00:07:01.800 --> 00:07:05.030 of these things and have them all work. 00:07:05.030 --> 00:07:09.580 So this is a wonderful industry in terms 00:07:09.580 --> 00:07:13.330 of exquisite manufacturing control required 00:07:13.330 --> 00:07:18.280 to have all 2 billion things work on your circuit. 00:07:18.280 --> 00:07:20.920 But to get a picture of what's really going on, 00:07:20.920 --> 00:07:23.870 we're going to focus in on a single transistor. 00:07:23.870 --> 00:07:28.390 And there's a picture of it geometrically, 00:07:28.390 --> 00:07:32.530 and over on the right here is a very abstracted picture 00:07:32.530 --> 00:07:36.430 of the function of a single MOSFET transistor. 00:07:36.430 --> 00:07:38.620 And the basic idea is that this can 00:07:38.620 --> 00:07:44.290 act as an electronic switch under the application 00:07:44.290 --> 00:07:48.190 of different voltage conditions so that one 00:07:48.190 --> 00:07:54.210 can control the flow of current in an on/off kind of fashion, 00:07:54.210 --> 00:07:58.150 and therefore perform certain logic functions, 00:07:58.150 --> 00:08:01.140 depending on the presence or absence of voltage 00:08:01.140 --> 00:08:03.420 on components of the structure. 00:08:07.170 --> 00:08:09.510 The real action is, right down here 00:08:09.510 --> 00:08:13.650 in the center of the device, in the center of the transistor, 00:08:13.650 --> 00:08:16.470 you essentially have a source and a drain. 00:08:16.470 --> 00:08:19.500 These are electrically conductive, 00:08:19.500 --> 00:08:22.290 and these little blue things are, in this picture, 00:08:22.290 --> 00:08:24.990 aluminum paths or metal paths-- 00:08:24.990 --> 00:08:28.450 metal connections, if you will-- 00:08:28.450 --> 00:08:33.630 that make contact to the semiconductor-- 00:08:33.630 --> 00:08:38.610 the silicon semiconductor layer underneath. 00:08:38.610 --> 00:08:41.400 These red regions have been very highly doped-- 00:08:41.400 --> 00:08:43.110 and we'll see the process for doing 00:08:43.110 --> 00:08:49.210 that-- that make them also much more metallic in nature. 00:08:49.210 --> 00:08:51.300 They are highly conductive. 00:08:51.300 --> 00:08:54.600 So this is how we get electrical access 00:08:54.600 --> 00:08:56.430 down to the semiconductor. 00:08:56.430 --> 00:09:00.060 The interesting part is the silicon 00:09:00.060 --> 00:09:02.520 that has been only lightly doped-- 00:09:02.520 --> 00:09:05.130 and that's what I think these little dots are meant 00:09:05.130 --> 00:09:11.340 to indicate-- to control the degree at which it will conduct 00:09:11.340 --> 00:09:16.980 under different amounts of potential applied 00:09:16.980 --> 00:09:20.790 to it from the control of a gate. 00:09:20.790 --> 00:09:24.870 This blue-- I guess it's green on this picture-- 00:09:24.870 --> 00:09:27.420 this is the gate electrode. 00:09:27.420 --> 00:09:30.960 And eventually, it's typically made out of polysilicon, 00:09:30.960 --> 00:09:34.290 and eventually contacted also by metal 00:09:34.290 --> 00:09:39.990 so that we can apply positive or negative voltage to the gate. 00:09:39.990 --> 00:09:43.355 And if we apply in a typical NMOS transistor 00:09:43.355 --> 00:09:46.380 enough of a positive voltage, what 00:09:46.380 --> 00:09:49.710 we do is we attract lots and lots of negative charges 00:09:49.710 --> 00:09:53.880 to counteract the positive charges 00:09:53.880 --> 00:09:57.450 we're creating on the surface of the gate. 00:09:57.450 --> 00:09:59.460 We create lots of-- 00:09:59.460 --> 00:10:05.130 or attract or generate an inversion 00:10:05.130 --> 00:10:07.680 with lots and lots of electrons, negative charge 00:10:07.680 --> 00:10:10.050 down here in this very, very thin surface 00:10:10.050 --> 00:10:12.090 layer of the silicon. 00:10:12.090 --> 00:10:15.360 So the semiconducting silicon can 00:10:15.360 --> 00:10:19.710 be made to conduct under certain voltage or bias conditions, 00:10:19.710 --> 00:10:22.770 and now current can flow from the gate-- 00:10:22.770 --> 00:10:25.810 or underneath the gate from the source to the drain. 00:10:25.810 --> 00:10:29.190 So if we apply a positive voltage, we turn the thing on, 00:10:29.190 --> 00:10:32.790 and current can flow. 00:10:32.790 --> 00:10:38.400 Alternatively, if we apply either an opposite voltage, 00:10:38.400 --> 00:10:45.300 or no voltage in a typical MOSFET for logic operations, 00:10:45.300 --> 00:10:47.280 the conductivity of the silicon layer 00:10:47.280 --> 00:10:53.430 will be so low that current is blocked, and the thing is off. 00:10:53.430 --> 00:10:58.170 So the basic idea here is we need to control carefully 00:10:58.170 --> 00:11:02.910 the conditions and properties of the silicon layer, 00:11:02.910 --> 00:11:05.190 and then we need to set up the rest of the geometry 00:11:05.190 --> 00:11:07.950 to be able to have access to the-- 00:11:07.950 --> 00:11:12.630 and form the structures for the source drain and the gate. 00:11:12.630 --> 00:11:15.660 So what we're going to see in this sequence 00:11:15.660 --> 00:11:17.880 is how we start from some raw material, 00:11:17.880 --> 00:11:21.930 build up the thin film layers, and differentiate 00:11:21.930 --> 00:11:24.610 both the geometry and change those properties. 00:11:24.610 --> 00:11:27.270 So in this picture, we're starting out here 00:11:27.270 --> 00:11:31.050 with the silicon in white. 00:11:31.050 --> 00:11:38.310 We add or create a thin layer of silicon dioxide 00:11:38.310 --> 00:11:40.200 in this picture. 00:11:40.200 --> 00:11:42.520 Now, there's lots of different processes-- 00:11:42.520 --> 00:11:45.540 many of these are discussed in more detail in May and Spanos-- 00:11:45.540 --> 00:11:49.920 for creating silicon dioxide. 00:11:49.920 --> 00:11:54.360 One is deposit on the surface. 00:11:54.360 --> 00:12:00.030 The other is to actually, quote, "grow" a silicon dioxide layer. 00:12:00.030 --> 00:12:03.630 And that is, we essentially subject the wafer 00:12:03.630 --> 00:12:12.570 to an oxygen carrying ambient, either O2 or a H2O vapor 00:12:12.570 --> 00:12:14.760 kind of ambient. 00:12:14.760 --> 00:12:19.710 And the oxygen will react with the silicon, forming SiO2, 00:12:19.710 --> 00:12:24.940 and we have a very nice stable silicon dioxide layer. 00:12:24.940 --> 00:12:28.800 It turns out that that simple process 00:12:28.800 --> 00:12:33.840 of being able to grow a very high-quality silicon dioxide 00:12:33.840 --> 00:12:36.780 layer was kind of the crux process 00:12:36.780 --> 00:12:42.870 that enabled integrated circuits in some fashion. 00:12:42.870 --> 00:12:45.750 And we'll talk about it a little bit later, but basically, 00:12:45.750 --> 00:12:47.730 we're going to need insulating layers 00:12:47.730 --> 00:12:50.100 between conducting layers-- 00:12:50.100 --> 00:12:52.560 one conducting layer being the silicon itself. 00:12:52.560 --> 00:12:56.400 The others-- when we build multiple levels of wiring, 00:12:56.400 --> 00:12:58.660 we need insulators between them. 00:12:58.660 --> 00:13:02.280 But in particular, for the formation of that transistor, 00:13:02.280 --> 00:13:05.110 the creation of a very good high-quality, 00:13:05.110 --> 00:13:08.280 very stable, well-controlled oxide 00:13:08.280 --> 00:13:11.370 insulating layer between the gate electrode and the silicon 00:13:11.370 --> 00:13:13.740 electrode was crucial. 00:13:13.740 --> 00:13:20.320 That forms, basically, a metal gate oxide semiconductor, 00:13:20.320 --> 00:13:24.210 or MOS transistor structure. 00:13:24.210 --> 00:13:29.730 The ability to create a MOS capacitor 00:13:29.730 --> 00:13:32.790 and then contact it on the sides, where 00:13:32.790 --> 00:13:38.910 you can invert the silicon layer was a big challenge. 00:13:38.910 --> 00:13:45.370 The first transistors were, in fact, bipolar transistors. 00:13:45.370 --> 00:13:48.970 Shortly after the invention of the bipolar transistor, 00:13:48.970 --> 00:13:51.940 Shockley went off on his own, and also invented 00:13:51.940 --> 00:13:55.230 the MOS transistor. 00:13:55.230 --> 00:14:01.720 In the very early versions, a different semiconductor 00:14:01.720 --> 00:14:03.940 material was used-- 00:14:03.940 --> 00:14:05.530 different element than silicon. 00:14:05.530 --> 00:14:07.505 Anybody know? 00:14:07.505 --> 00:14:09.380 What were the first transistors built out of? 00:14:09.380 --> 00:14:10.255 AUDIENCE: Germanium-- 00:14:10.255 --> 00:14:12.730 DUANE BONING: Germanium-- why aren't 00:14:12.730 --> 00:14:15.720 all of our transistors built out of germanium now? 00:14:15.720 --> 00:14:16.720 We'll come back to that. 00:14:16.720 --> 00:14:18.303 Some of them are starting to be again. 00:14:20.440 --> 00:14:25.890 The problem is, if you oxidize germanium, 00:14:25.890 --> 00:14:29.390 you get an insulating layer. 00:14:29.390 --> 00:14:33.770 The problem is it's extremely soft and unstable. 00:14:33.770 --> 00:14:37.550 And in fact, if you oxidize the surface of germanium, 00:14:37.550 --> 00:14:41.870 you can wipe away the oxide. 00:14:41.870 --> 00:14:46.370 It is not stable and manufacturable. 00:14:46.370 --> 00:14:48.980 And so it was really this ability 00:14:48.980 --> 00:14:55.310 right here to be able to grow a very hard, high-quality silicon 00:14:55.310 --> 00:14:59.300 dioxide that was crucial for being able to build up 00:14:59.300 --> 00:15:01.940 for both the conversion over to silicon 00:15:01.940 --> 00:15:06.120 and for being able to build up complex structures. 00:15:06.120 --> 00:15:11.730 OK, so we've got this thin silicon dioxide layer here 00:15:11.730 --> 00:15:13.200 that has been grown. 00:15:13.200 --> 00:15:15.960 Now what we want to do is start building 00:15:15.960 --> 00:15:17.520 the region where we're actually going 00:15:17.520 --> 00:15:20.425 to have the active device. 00:15:20.425 --> 00:15:22.050 So we're going to go through a sequence 00:15:22.050 --> 00:15:25.140 here that gets repeated again and again this 00:15:25.140 --> 00:15:28.760 is referred to as the photolithographic sequence. 00:15:28.760 --> 00:15:31.890 And so what we start with is depositing 00:15:31.890 --> 00:15:35.710 a thin layer of photoresist, shown in red here, 00:15:35.710 --> 00:15:37.210 this is typically spun on. 00:15:37.210 --> 00:15:42.000 So this is a polymer type of material. 00:15:42.000 --> 00:15:48.150 It's in a solvent so that one can drop the material on, 00:15:48.150 --> 00:15:51.150 and then spin the wafer very rapidly in order 00:15:51.150 --> 00:15:53.730 to get the controlled film thickness that one 00:15:53.730 --> 00:15:56.010 wants for the photoresist. 00:15:56.010 --> 00:16:02.220 And this is-- interacts with light 00:16:02.220 --> 00:16:04.180 in one two different ways. 00:16:04.180 --> 00:16:06.930 You can have positive or negative photoresist. 00:16:06.930 --> 00:16:10.520 What's shown in the next picture is a typical-- 00:16:13.230 --> 00:16:13.910 let's see. 00:16:13.910 --> 00:16:16.230 Is this is one positive or negative? 00:16:16.230 --> 00:16:17.940 This one's a positive photoresist, 00:16:17.940 --> 00:16:28.060 because we're going to basically transform or imprint, if you 00:16:28.060 --> 00:16:32.710 will, the mask layer here in the same fashion 00:16:32.710 --> 00:16:37.060 with the underlying photoresist. 00:16:37.060 --> 00:16:38.710 The basic idea of the photoresist 00:16:38.710 --> 00:16:41.710 is it contains photoactive compounds 00:16:41.710 --> 00:16:45.190 that underexposure to light will change the polymer 00:16:45.190 --> 00:16:48.625 linking of the photoresist. 00:16:48.625 --> 00:16:50.164 Yeah-- question? 00:16:50.164 --> 00:16:53.270 AUDIENCE: But I understand the [INAUDIBLE] sorry. 00:16:53.270 --> 00:16:54.020 DUANE BONING: Yes. 00:16:54.020 --> 00:16:54.530 AUDIENCE: I understand the [INAUDIBLE] 00:16:54.530 --> 00:16:56.915 as the [INAUDIBLE] the black part. 00:16:56.915 --> 00:16:57.860 DUANE BONING: Right. 00:16:57.860 --> 00:17:00.470 AUDIENCE: [INAUDIBLE] black part. 00:17:00.470 --> 00:17:00.970 [INAUDIBLE] 00:17:00.970 --> 00:17:02.130 DUANE BONING: That's exactly right. 00:17:02.130 --> 00:17:03.880 AUDIENCE: --change the chemical structure. 00:17:03.880 --> 00:17:05.359 DUANE BONING: That's right. 00:17:05.359 --> 00:17:11.240 The goal is to take some design, from some CAD system 00:17:11.240 --> 00:17:15.660 or whatever, that enables us to differentiate the surface. 00:17:15.660 --> 00:17:19.500 The design is used to make a physical-- 00:17:19.500 --> 00:17:23.680 well, in most cases, a physical glass plate, if you will, 00:17:23.680 --> 00:17:26.010 that has metal blocking areas-- 00:17:26.010 --> 00:17:30.540 the chromium-- that are intended to block 00:17:30.540 --> 00:17:33.600 the transmission of the light source in some regions, 00:17:33.600 --> 00:17:34.780 and allow it in others. 00:17:34.780 --> 00:17:36.250 So that's exactly right. 00:17:36.250 --> 00:17:38.468 AUDIENCE: [INAUDIBLE] are not exposed. 00:17:38.468 --> 00:17:39.260 DUANE BONING: Yeah. 00:17:39.260 --> 00:17:41.690 So this is actually a cutaway. 00:17:41.690 --> 00:17:43.850 This is going on for-- 00:17:43.850 --> 00:17:47.660 if this is only a couple of microns 00:17:47.660 --> 00:17:50.810 wide, the entire wafer-- 00:17:50.810 --> 00:17:54.920 or the entire chip, depending on how the photolithography-- 00:17:54.920 --> 00:17:56.690 it goes on forever. 00:17:56.690 --> 00:17:58.490 So this is just a cutaway. 00:17:58.490 --> 00:18:01.540 AUDIENCE: No, but I mean the middle is exposed. 00:18:01.540 --> 00:18:02.570 DUANE BONING: Yes, yes. 00:18:02.570 --> 00:18:05.685 AUDIENCE: OK, so we can wash away the exposed part? 00:18:05.685 --> 00:18:06.560 DUANE BONING: Right-- 00:18:06.560 --> 00:18:09.320 AUDIENCE: But it's not solidifying the-- 00:18:09.320 --> 00:18:10.610 DUANE BONING: No. 00:18:10.610 --> 00:18:16.290 OK, so that's the two types of photoresist activity. 00:18:16.290 --> 00:18:18.950 So in this case, with the positive photoresist, what 00:18:18.950 --> 00:18:26.240 happens is the light energy from the exposure system 00:18:26.240 --> 00:18:30.230 will break down some of the polymer chains 00:18:30.230 --> 00:18:33.380 in the-- in these photoactive polymer chains 00:18:33.380 --> 00:18:36.260 in the photoresist, weakening them. 00:18:36.260 --> 00:18:42.470 We then go in and do a develop process, where a chemical 00:18:42.470 --> 00:18:46.820 solvent is used that attacks the weakened polymer chains 00:18:46.820 --> 00:18:48.110 and rinses it away. 00:18:48.110 --> 00:18:51.380 So we have the spin on resist, we 00:18:51.380 --> 00:18:56.630 do the exposure to light through the mask, then we do a develop, 00:18:56.630 --> 00:18:58.250 rinsing away the resist. 00:18:58.250 --> 00:19:03.230 And in the positive case, the pattern on the mask 00:19:03.230 --> 00:19:07.920 is transferred directly, if you will, 00:19:07.920 --> 00:19:10.160 into the pattern of the photoresist. 00:19:10.160 --> 00:19:13.385 There is also, in fact more commonly used, 00:19:13.385 --> 00:19:15.890 a negative photoresist that actually 00:19:15.890 --> 00:19:19.730 works in the opposite way, which is anywhere 00:19:19.730 --> 00:19:22.640 where the light exposes, it actually 00:19:22.640 --> 00:19:27.620 strengthens the chemical bonding of the photoactive compound 00:19:27.620 --> 00:19:32.510 in the polymer, and makes it more resistant to dissolution 00:19:32.510 --> 00:19:34.850 in the developer-- in which case, 00:19:34.850 --> 00:19:37.040 I would rinse away everything that 00:19:37.040 --> 00:19:40.280 did not get exposed and leave the pattern which 00:19:40.280 --> 00:19:42.980 did get exposed. 00:19:42.980 --> 00:19:46.790 So actually, there's some degree of design choice 00:19:46.790 --> 00:19:50.660 in picking a positive and negative photoresist, depending 00:19:50.660 --> 00:19:54.980 on some manufacturing control issues. 00:19:54.980 --> 00:20:02.770 It turns out, if you're developing away material, 00:20:02.770 --> 00:20:05.320 you might, in one case or the other, 00:20:05.320 --> 00:20:09.130 be able to actually overdevelop or overexpose 00:20:09.130 --> 00:20:12.415 slightly and control slightly the line 00:20:12.415 --> 00:20:14.900 width of these features a little bit better 00:20:14.900 --> 00:20:17.445 in one photoresist case than the other, 00:20:17.445 --> 00:20:18.820 depending on what you want to do. 00:20:21.640 --> 00:20:24.610 OK, so so far, this sequence of three steps 00:20:24.610 --> 00:20:28.540 has simply transferred the mask pattern 00:20:28.540 --> 00:20:33.050 into a photoresist pattern, but the photoresist 00:20:33.050 --> 00:20:35.020 itself only temporary. 00:20:35.020 --> 00:20:41.290 Its purpose is to act as a mask to allow us to differentiate 00:20:41.290 --> 00:20:44.230 more aggressive physical transformations 00:20:44.230 --> 00:20:45.970 of the remaining wafer. 00:20:45.970 --> 00:20:48.700 And in particular, in the following case, 00:20:48.700 --> 00:20:52.810 as shown here in step 5, this is saying 00:20:52.810 --> 00:20:58.480 what we want to do now is do another etch of the silicon 00:20:58.480 --> 00:21:03.440 dioxide layer, in this case using 00:21:03.440 --> 00:21:06.290 a plasma-- a gas plasma etch. 00:21:06.290 --> 00:21:10.070 I guess that's what the little lightning storm here is. 00:21:10.070 --> 00:21:20.800 So this is typically done in a very low pressure vacuum 00:21:20.800 --> 00:21:23.020 equipment, where we have some feed gas. 00:21:23.020 --> 00:21:28.990 We apply RF energy to dissociate the species in the gas. 00:21:28.990 --> 00:21:31.690 Many of those species then become very highly chemically 00:21:31.690 --> 00:21:34.540 reactive, and they interact with the surface of the wafer 00:21:34.540 --> 00:21:38.360 and etch away particular species. 00:21:38.360 --> 00:21:42.460 So one would design the plasma process 00:21:42.460 --> 00:21:48.400 to preferentially etch away the silicon dioxide, while not 00:21:48.400 --> 00:21:50.470 attacking, or only very, very slowly 00:21:50.470 --> 00:21:54.080 attacking the protective photoresist layer. 00:21:54.080 --> 00:21:55.930 So what this is allowing us to do 00:21:55.930 --> 00:21:58.270 is essentially vertically etch down 00:21:58.270 --> 00:22:01.450 into the silicon dioxide layer. 00:22:01.450 --> 00:22:04.240 Now, in this picture, what they're trying to do here 00:22:04.240 --> 00:22:10.210 is show that we are partially etching some silicon dioxide 00:22:10.210 --> 00:22:17.290 layer away, apparently leaving a small remaining level or layer 00:22:17.290 --> 00:22:18.590 of silicon dioxide. 00:22:18.590 --> 00:22:21.460 So you can see that shadow down in there? 00:22:21.460 --> 00:22:23.950 What they're trying to show in this case 00:22:23.950 --> 00:22:27.760 is they're leaving this thin silicon dioxide 00:22:27.760 --> 00:22:30.670 layer that is going to be that insulator between the gate 00:22:30.670 --> 00:22:35.650 electrode and the silicon that we talked about 00:22:35.650 --> 00:22:38.570 in the final structure. 00:22:38.570 --> 00:22:42.340 So typically, this might be, oh-- 00:22:42.340 --> 00:22:45.910 what you might have is close to modern technology. 00:22:45.910 --> 00:22:48.560 You might have a 1/2 a micron in the-- 00:22:48.560 --> 00:22:51.220 of silicon dioxide that you want-- 00:22:51.220 --> 00:22:53.590 fairly thick silicon dioxide-- 00:22:53.590 --> 00:22:58.330 out here to act as a very, very big insulating layer separating 00:22:58.330 --> 00:23:02.540 your metal electrodes from other components. 00:23:02.540 --> 00:23:05.170 But this silicon dioxide layer that's 00:23:05.170 --> 00:23:08.710 used between the gate and the semiconductor 00:23:08.710 --> 00:23:12.450 needs to be extremely thin. 00:23:12.450 --> 00:23:14.360 And the reason is the closer I can 00:23:14.360 --> 00:23:17.420 get my two plates of that capacitor, the more control-- 00:23:17.420 --> 00:23:19.010 well, the more capacitance I have, 00:23:19.010 --> 00:23:25.190 but the more control I have all of the silicon surface. 00:23:25.190 --> 00:23:28.490 So the harder I can turn the device on, the more current 00:23:28.490 --> 00:23:32.300 I can flow per unit area, and so on. 00:23:32.300 --> 00:23:35.040 So in this process, apparently we're 00:23:35.040 --> 00:23:38.390 etching from about 1/2 micron-- 00:23:38.390 --> 00:23:41.960 5,000 angstroms-- down to-- 00:23:41.960 --> 00:23:44.240 we might be at 100 angstrom. 00:23:44.240 --> 00:23:50.055 Or below remaining gate oxide layer is, in a modern process, 00:23:50.055 --> 00:23:50.930 really what you want. 00:23:54.500 --> 00:23:57.960 Everybody happy with that? 00:23:57.960 --> 00:24:01.820 AUDIENCE: So what is the tolerance? 00:24:01.820 --> 00:24:05.500 DUANE BONING: Hooray-- how would you do that? 00:24:05.500 --> 00:24:06.680 Yeah. 00:24:06.680 --> 00:24:07.880 What is the tolerance? 00:24:07.880 --> 00:24:10.430 Well, first off, to answer your question, 00:24:10.430 --> 00:24:14.990 you want that to be 100 angstroms, plus or minus-- 00:24:14.990 --> 00:24:18.710 well, in fact, some of the kinds of control that they quote 00:24:18.710 --> 00:24:23.060 are plus or minus 5 angstroms, which 00:24:23.060 --> 00:24:29.210 is less than an atomic layer in some cases. 00:24:29.210 --> 00:24:32.300 What they actually mean is, on average, 00:24:32.300 --> 00:24:34.710 over certain kinds of areas. 00:24:34.710 --> 00:24:38.420 But how would you actually achieve 00:24:38.420 --> 00:24:40.440 that with the manufacturing process? 00:24:43.240 --> 00:24:49.260 How are you going to etch down through 5,000 angstroms 00:24:49.260 --> 00:24:52.860 and stop 1,000 angstroms, or 100 angstroms 00:24:52.860 --> 00:24:54.080 before you hit the silicon? 00:24:57.930 --> 00:25:02.574 Very carefully-- no, the answer is you're not. 00:25:02.574 --> 00:25:03.420 You're not. 00:25:08.550 --> 00:25:11.340 There are some additional reasons 00:25:11.340 --> 00:25:14.760 why one wouldn't want to do it, but at present, we 00:25:14.760 --> 00:25:16.710 don't have the observability to be 00:25:16.710 --> 00:25:20.610 able to know when we're within 100 angstroms. 00:25:20.610 --> 00:25:23.910 Second, there's no way you can be that uniform 00:25:23.910 --> 00:25:25.680 across the whole wafer. 00:25:25.680 --> 00:25:28.140 What if, on one part of the wafer, 00:25:28.140 --> 00:25:32.040 instead of 5,000 angstroms, it was 5,001 angstroms? 00:25:32.040 --> 00:25:37.410 By the time I get down to know etching 4,900 angstroms 00:25:37.410 --> 00:25:40.770 everywhere, that little 1 out of 5,000 00:25:40.770 --> 00:25:42.980 controllability has been trans-- 00:25:42.980 --> 00:25:45.210 or variability, which is not bad. 00:25:45.210 --> 00:25:52.566 That'd be great if I got whatever that percentage is-- 00:25:52.566 --> 00:25:54.120 0.02% or whatever. 00:25:54.120 --> 00:25:55.290 That's amazing. 00:25:55.290 --> 00:25:58.500 But it would magnify by the time I etch down, 00:25:58.500 --> 00:26:01.140 even if I could etch uniformally. 00:26:01.140 --> 00:26:03.850 There's just no way, most importantly, 00:26:03.850 --> 00:26:07.110 to be able to know when you're within 100 angstroms 00:26:07.110 --> 00:26:12.220 and be able to stop controllably at that level. 00:26:12.220 --> 00:26:15.282 So what do you think they really do? 00:26:15.282 --> 00:26:16.740 AUDIENCE: Etch all the way through, 00:26:16.740 --> 00:26:18.210 then grow another layer-- 00:26:18.210 --> 00:26:20.140 DUANE BONING: That's exactly right. 00:26:20.140 --> 00:26:22.350 We can controllably etch all the way 00:26:22.350 --> 00:26:27.300 through using ideas of etch selectivity. 00:26:27.300 --> 00:26:28.920 The same idea I mentioned of-- 00:26:28.920 --> 00:26:31.350 we can form the-- 00:26:31.350 --> 00:26:33.900 or choose an etch chemistry that allows 00:26:33.900 --> 00:26:39.300 us to etch silicon dioxide and not etch photoresist. 00:26:39.300 --> 00:26:44.310 We can also use to etch silicon dioxide but not etch silicon, 00:26:44.310 --> 00:26:47.790 can have very good selectivity so that one 00:26:47.790 --> 00:26:51.210 can stop controllably on the surface of the silicon. 00:26:51.210 --> 00:26:53.310 Now everybody knows exactly where 00:26:53.310 --> 00:26:55.590 they are across every place in the wafer. 00:26:55.590 --> 00:26:59.910 One can even over-etch a little bit. 00:26:59.910 --> 00:27:02.520 You don't even have to try to set up a timed etch. 00:27:02.520 --> 00:27:05.610 If I was etching at 1,000 angstroms a minute 00:27:05.610 --> 00:27:07.440 and I started with 5,000 angstroms, 00:27:07.440 --> 00:27:09.720 I might etch for five minutes. 00:27:09.720 --> 00:27:13.500 But to be sure that I've got the same degree of uniformity 00:27:13.500 --> 00:27:16.710 everywhere, I might add for an extra 10 seconds. 00:27:16.710 --> 00:27:19.410 That way, I'm sure that I'm clearing everywhere across 00:27:19.410 --> 00:27:22.410 the wafer, even if there's spatial non-uniformity 00:27:22.410 --> 00:27:26.460 in my etch, or today's etching's slightly slower than 00:27:26.460 --> 00:27:28.860 yesterday's. 00:27:28.860 --> 00:27:34.960 Then I can go back in and, with different process conditions-- 00:27:34.960 --> 00:27:39.580 lower temperatures, more pure chemicals, 00:27:39.580 --> 00:27:43.270 or slightly different-- primarily different 00:27:43.270 --> 00:27:46.540 temperature, or even using alternative process 00:27:46.540 --> 00:27:54.310 technologies that involve very, very short time oxidations-- 00:27:54.310 --> 00:27:56.890 rapid thermal oxidations-- 00:27:56.890 --> 00:28:01.840 I can now controllably grow up 1,000 angstroms, or 100 00:28:01.840 --> 00:28:03.280 angstroms, or whatever I need. 00:28:05.970 --> 00:28:08.580 So that's the first mistake. 00:28:08.580 --> 00:28:09.720 I remember that one. 00:28:09.720 --> 00:28:12.690 I think there's another one someplace. 00:28:12.690 --> 00:28:14.520 OK. 00:28:14.520 --> 00:28:19.560 So still taking this at face value, 00:28:19.560 --> 00:28:21.410 we had the photolithographic sequence 00:28:21.410 --> 00:28:24.090 imprinted onto the photoresist. 00:28:24.090 --> 00:28:27.660 We used that then to controllability change 00:28:27.660 --> 00:28:30.570 the permanent structure, the silicon dioxide. 00:28:30.570 --> 00:28:33.900 And then we remove using another chemical solvent, 00:28:33.900 --> 00:28:38.040 or in many cases, another plasma etch, a plasma ash 00:28:38.040 --> 00:28:43.260 that removes the temporary photoresist. 00:28:43.260 --> 00:28:44.130 Then we go on. 00:28:44.130 --> 00:28:45.540 We've done that sequence. 00:28:45.540 --> 00:28:50.040 We've now deposited or grown, and then 00:28:50.040 --> 00:28:53.190 spatially differentiated to be able to create 00:28:53.190 --> 00:28:55.960 one level of the structure. 00:28:55.960 --> 00:28:58.440 And now we're going to repeat that kind of idea 00:28:58.440 --> 00:29:01.590 multiple times, and then mix in a few additional transformation 00:29:01.590 --> 00:29:02.430 steps. 00:29:02.430 --> 00:29:05.170 Next step here as we're depositing a-- 00:29:05.170 --> 00:29:08.640 our polysilicon layer. 00:29:08.640 --> 00:29:14.460 Again, this will be fairly highly doped either subsequent 00:29:14.460 --> 00:29:17.430 to the deposition or during the deposition. 00:29:17.430 --> 00:29:22.170 It is a semiconducting layer, but if one dops it-- that is, 00:29:22.170 --> 00:29:26.400 adds elemental impurities of a particular type to play with 00:29:26.400 --> 00:29:28.950 the band structure of the silicon-- 00:29:28.950 --> 00:29:32.580 one can make that behave in a fairly metallic fashion. 00:29:32.580 --> 00:29:35.550 And in the MOS transistor, that polysilicon 00:29:35.550 --> 00:29:42.400 is very highly doped, and is a conductor under all conditions. 00:29:42.400 --> 00:29:45.730 So we've deposited that. 00:29:45.730 --> 00:29:47.490 What geometry do we want? 00:29:47.490 --> 00:29:49.880 We want this thin gate electrode, 00:29:49.880 --> 00:29:51.420 so we're going to do a photoresist-- 00:29:51.420 --> 00:29:54.270 or photolithographic step again to do that-- 00:29:54.270 --> 00:29:58.860 deposit photoresist, expose. 00:29:58.860 --> 00:30:04.830 In this case, here, again, another positive photoresist 00:30:04.830 --> 00:30:07.530 case-- so we're blocking this structure. 00:30:07.530 --> 00:30:15.810 We develop and dissolve away the exposed photoresist, 00:30:15.810 --> 00:30:18.270 and then we're doing a plasma etch again to-- 00:30:21.420 --> 00:30:24.120 plasma etch to form the gate electrode, 00:30:24.120 --> 00:30:29.010 and then remove or ash away the photoresist. 00:30:29.010 --> 00:30:34.810 Now, this structure right here is very, very critical. 00:30:34.810 --> 00:30:38.740 This is the gate electrode. 00:30:38.740 --> 00:30:40.750 Again, the current is going to flow 00:30:40.750 --> 00:30:45.460 in this direction along this length underneath that gate 00:30:45.460 --> 00:30:47.330 electrode in the silicon. 00:30:47.330 --> 00:30:50.110 And this is referred to as the channel length. 00:30:50.110 --> 00:30:52.030 So the channel is the structure that we're 00:30:52.030 --> 00:30:54.370 going to create underneath the silicon. 00:30:54.370 --> 00:30:57.790 And the length of that physical electrode 00:30:57.790 --> 00:31:02.470 is very, very, very critical in determining 00:31:02.470 --> 00:31:04.930 many of the most important characteristics 00:31:04.930 --> 00:31:06.810 of the transistor. 00:31:06.810 --> 00:31:09.690 You can think of it as-- 00:31:09.690 --> 00:31:12.510 and we're actually getting closer in the dimensions 00:31:12.510 --> 00:31:14.130 that we're talking about now-- 00:31:14.130 --> 00:31:17.850 that the time of flight of an electron 00:31:17.850 --> 00:31:20.910 underneath that electrode will depend 00:31:20.910 --> 00:31:26.070 on the width or the length that it needs to transit. 00:31:26.070 --> 00:31:29.100 We're getting close to these velocity 00:31:29.100 --> 00:31:31.530 limited transport regimes. 00:31:31.530 --> 00:31:35.520 And so from one point of view, the ability 00:31:35.520 --> 00:31:38.640 or the speed of the transistor is 00:31:38.640 --> 00:31:41.550 critically dependent on variations in that channel 00:31:41.550 --> 00:31:42.850 length. 00:31:42.850 --> 00:31:46.240 This is often referred to as the CD of-- 00:31:46.240 --> 00:31:50.290 or one of the CDs of the process, critical dimensions 00:31:50.290 --> 00:31:52.390 of the process. 00:31:52.390 --> 00:31:57.160 And in modern technology, in fact, 00:31:57.160 --> 00:32:00.880 that is perhaps the smallest lateral dimension 00:32:00.880 --> 00:32:06.520 that is determinative of the generation of the technology 00:32:06.520 --> 00:32:09.340 and the performance and characteristics 00:32:09.340 --> 00:32:10.700 of the technology. 00:32:10.700 --> 00:32:14.110 So if we talk about a 65-nanometer technology, 00:32:14.110 --> 00:32:17.590 they're talking typically about that channel length, 00:32:17.590 --> 00:32:23.950 that minimum feature size being 65 nanometers. 00:32:23.950 --> 00:32:27.400 In fact, often, tricks are played where, 00:32:27.400 --> 00:32:31.660 photolithographically, using the exposure, that's the dimension 00:32:31.660 --> 00:32:33.340 that they can form. 00:32:33.340 --> 00:32:36.610 But you might actually over-etch and shrink that, 00:32:36.610 --> 00:32:40.255 get that to even a smaller dimension than you could 00:32:40.255 --> 00:32:44.980 photolithographically define in order to boost the speed 00:32:44.980 --> 00:32:48.830 and the controllability of the device. 00:32:48.830 --> 00:32:56.020 So this is very critical lithography step and sequence. 00:32:56.020 --> 00:32:57.670 Going on, the next thing we need to do 00:32:57.670 --> 00:33:00.580 is start to form the source and drain regions. 00:33:00.580 --> 00:33:03.370 We need to differentiate the silicon underneath. 00:33:03.370 --> 00:33:08.770 And what we're going to do here is use another process, an ion 00:33:08.770 --> 00:33:13.260 implantation process, I believe, in this-- 00:33:13.260 --> 00:33:16.920 yes, I think that's what their little picture there is-- 00:33:16.920 --> 00:33:20.100 where we actually implant those [INAUDIBLE] atoms. 00:33:20.100 --> 00:33:27.570 We shoot them with essentially a high-energy electron or ion 00:33:27.570 --> 00:33:31.860 gun into the silicon in a very controlled fashion. 00:33:31.860 --> 00:33:35.250 The guys who are going to Varian here 00:33:35.250 --> 00:33:40.230 in Gloucester, Massachusetts-- 00:33:40.230 --> 00:33:42.450 Varian sells ion implanters. 00:33:42.450 --> 00:33:43.410 That's their business. 00:33:43.410 --> 00:33:44.760 They're-- I don't know-- 00:33:44.760 --> 00:33:47.340 75% or something of the market now. 00:33:47.340 --> 00:33:50.460 They're dominant, and they sell the equipment 00:33:50.460 --> 00:33:54.764 for ion implantation. 00:33:54.764 --> 00:33:57.940 There's also other competing ion implant companies, 00:33:57.940 --> 00:33:59.990 but most of them are also in Massachusetts. 00:33:59.990 --> 00:34:04.720 So Massachusetts is the ion implant capital of the world. 00:34:04.720 --> 00:34:07.060 The basic idea there, again, is we're 00:34:07.060 --> 00:34:13.120 highly doping in a controllable fashion just these regions. 00:34:13.120 --> 00:34:16.940 Those regions we don't want to dope underneath the channel-- 00:34:16.940 --> 00:34:18.489 we want to keep that fairly lightly 00:34:18.489 --> 00:34:21.880 doped so that we can invert it for electrical action. 00:34:21.880 --> 00:34:25.750 And in this case, we're getting something often referred 00:34:25.750 --> 00:34:31.330 to as a self-aligned process, whereby 00:34:31.330 --> 00:34:34.630 we don't have to selectively shoot the ions just in here. 00:34:34.630 --> 00:34:38.260 We can blanket the whole wafer, and use these thick oxide 00:34:38.260 --> 00:34:41.949 and use the polysilicon as the mask itself 00:34:41.949 --> 00:34:46.690 to prevent the ions from reaching the underlying silicon 00:34:46.690 --> 00:34:47.710 regions. 00:34:47.710 --> 00:34:52.060 So instead of having to put down another photoresist layer 00:34:52.060 --> 00:34:56.770 and try to open up just exactly those regions, 00:34:56.770 --> 00:35:00.400 and worry about aligning of the physical mask 00:35:00.400 --> 00:35:03.520 to match up exactly with the existing 00:35:03.520 --> 00:35:06.010 structures on the wafer, we can take 00:35:06.010 --> 00:35:08.290 advantage of the underlying structures 00:35:08.290 --> 00:35:12.770 to achieve that spatial alignment. 00:35:12.770 --> 00:35:13.270 Yeah? 00:35:13.270 --> 00:35:14.937 AUDIENCE: Can you elaborate a little bit 00:35:14.937 --> 00:35:18.260 on the process of placing this photoresist? 00:35:18.260 --> 00:35:22.210 Seems like you're going to have one [INAUDIBLE] put another. 00:35:22.210 --> 00:35:24.340 How do you make sure everything lines up the way 00:35:24.340 --> 00:35:25.510 you need it to? 00:35:25.510 --> 00:35:28.390 DUANE BONING: This is a wonderful manufacturing control 00:35:28.390 --> 00:35:30.520 challenge. 00:35:30.520 --> 00:35:32.395 Overlay and alignment are-- 00:35:35.740 --> 00:35:40.540 almost more so than the physical dimension that can be imaged 00:35:40.540 --> 00:35:43.720 are the manufacturing control problems. 00:35:43.720 --> 00:35:47.110 There's more description in May and Spanos. 00:35:47.110 --> 00:35:54.100 But essentially, over time, the ability to optically 00:35:54.100 --> 00:35:57.910 line up the existing structures-- 00:35:57.910 --> 00:36:01.630 typically, you might actually use alignment marks 00:36:01.630 --> 00:36:05.530 that you build up in parallel to these transistors 00:36:05.530 --> 00:36:07.810 to aid in the optical-- 00:36:07.810 --> 00:36:14.140 automatic optical recognition of spatial locations on the wafer. 00:36:14.140 --> 00:36:16.630 It's a huge challenge to then line that up 00:36:16.630 --> 00:36:24.460 with the physical mask plate, such that you minimize offsets. 00:36:24.460 --> 00:36:27.970 There's also exquisite environmental control 00:36:27.970 --> 00:36:30.440 in the equipment that's used for this. 00:36:30.440 --> 00:36:32.890 Imagine that I don't need to line up just 00:36:32.890 --> 00:36:35.080 for one transistor-- 00:36:35.080 --> 00:36:42.625 I got to make sure across maybe a 1 centimeter squared or 2 00:36:42.625 --> 00:36:46.690 centimeter squared chip that all of my transistors 00:36:46.690 --> 00:36:48.010 are lining up. 00:36:48.010 --> 00:36:49.510 And in fact, in older technologies, 00:36:49.510 --> 00:36:51.510 I had to make sure the whole wafer was lined up, 00:36:51.510 --> 00:36:54.790 because I had a big glass plate that I was using in almost 00:36:54.790 --> 00:36:58.810 a one-for-one transformation, so everything across a whole wafer 00:36:58.810 --> 00:37:00.430 had to be lined up. 00:37:00.430 --> 00:37:04.120 And if the temperature of the glass plate 00:37:04.120 --> 00:37:09.000 and out of the wafer were off by a degree, 00:37:09.000 --> 00:37:13.420 the thermal expansion would upset the alignment, 00:37:13.420 --> 00:37:14.620 for example. 00:37:14.620 --> 00:37:17.520 So over time, you've seen-- 00:37:17.520 --> 00:37:20.340 both to achieve smaller dimension, 00:37:20.340 --> 00:37:23.070 but also to achieve better control-- 00:37:23.070 --> 00:37:26.740 a number of [INAUDIBLE] driver for the evolution 00:37:26.740 --> 00:37:29.490 of the photolithographic equipment. 00:37:29.490 --> 00:37:34.560 One step was photolithographic reduction from, say, a 10 to 1 00:37:34.560 --> 00:37:42.390 or a 5 to 1 glass plate down to a smaller chip or smaller 00:37:42.390 --> 00:37:43.020 wafer. 00:37:43.020 --> 00:37:45.120 The second was chip-to-chip stepping. 00:37:45.120 --> 00:37:47.970 So in fact, the photolithography equipment's 00:37:47.970 --> 00:37:50.850 typically called now a stepper, because it's imaging 00:37:50.850 --> 00:37:54.510 one field, maybe one chip. 00:37:54.510 --> 00:37:57.210 There may be more than one chip in each field, 00:37:57.210 --> 00:38:00.900 but I'm stepping through in order to get the control 00:38:00.900 --> 00:38:03.930 and be able to achieve the alignment on one 00:38:03.930 --> 00:38:05.080 chip at a time. 00:38:05.080 --> 00:38:07.360 And in the most modern equipment, 00:38:07.360 --> 00:38:10.110 in fact, they don't even image the whole chip at one time. 00:38:10.110 --> 00:38:13.410 They're imaging slices of that so 00:38:13.410 --> 00:38:17.820 that they can do all kinds of other on the fly alignment 00:38:17.820 --> 00:38:21.660 control, as well as leveling, because turns out 00:38:21.660 --> 00:38:24.270 the depth of focus is a big constraint. 00:38:24.270 --> 00:38:31.310 And if I have a focal plane mismatch, 00:38:31.310 --> 00:38:33.620 where I'm in focus on the left side of the chip 00:38:33.620 --> 00:38:35.420 and not on the right, then I don't get 00:38:35.420 --> 00:38:37.800 the dimensional control I need. 00:38:37.800 --> 00:38:42.500 So it's really amazing innovations 00:38:42.500 --> 00:38:46.160 that are exactly driven by the manufacturing 00:38:46.160 --> 00:38:48.273 control necessary. 00:38:48.273 --> 00:38:49.940 So there's a little bit more description 00:38:49.940 --> 00:38:55.560 in here talking about some of that equipment as well. 00:38:55.560 --> 00:38:58.460 In fact, I'm not really talking here much 00:38:58.460 --> 00:39:01.130 about the processing equipment. 00:39:01.130 --> 00:39:05.420 I'm trying to get us through at least the process 00:39:05.420 --> 00:39:07.850 sequence, but the equipment itself is fascinating. 00:39:07.850 --> 00:39:09.860 It's really fascinating. 00:39:09.860 --> 00:39:12.980 OK, we're almost there with this device, because now we're 00:39:12.980 --> 00:39:18.510 primarily just repeating these same kinds of structures. 00:39:18.510 --> 00:39:22.010 What we're going to do now is another photolithography step. 00:39:22.010 --> 00:39:27.020 Here, essentially what we want to do with this yellow layer 00:39:27.020 --> 00:39:31.530 is build up an insulating layer. 00:39:31.530 --> 00:39:35.510 So I think a new layer of silicon dioxide is deposited. 00:39:35.510 --> 00:39:37.400 In this case, it's not thermally grown 00:39:37.400 --> 00:39:39.650 through that chemical reaction of oxide. 00:39:39.650 --> 00:39:44.690 And silicon-- because I've already got polysilicon, 00:39:44.690 --> 00:39:46.400 I've got-- 00:39:46.400 --> 00:39:48.900 well, I guess it actually might work in this case. 00:39:48.900 --> 00:39:53.310 I've already got a very thick layer of silicon in this case, 00:39:53.310 --> 00:39:56.720 we use typically a chemical vapor deposition process-- 00:39:56.720 --> 00:39:58.490 again, in vacuum equipment. 00:39:58.490 --> 00:40:03.920 But we decompose silicon dioxide carrying 00:40:03.920 --> 00:40:07.350 molecules in a gas plasma. 00:40:07.350 --> 00:40:11.010 So there will be a more complex molecule typically coming in, 00:40:11.010 --> 00:40:13.170 and we decompose that, and basically, it 00:40:13.170 --> 00:40:16.140 snows on the surface of the wafer 00:40:16.140 --> 00:40:20.760 and builds up a silicon dioxide layer. 00:40:20.760 --> 00:40:22.910 So we deposit that silicon dioxide, 00:40:22.910 --> 00:40:27.600 and what we're going to do is now open up holes within that 00:40:27.600 --> 00:40:29.680 using a photolithography step. 00:40:29.680 --> 00:40:32.280 You can see here's the mask, where we want to open up 00:40:32.280 --> 00:40:35.340 a hole; down, where we'll be able to make contact 00:40:35.340 --> 00:40:40.470 to the gate and make contact to the source and drain. 00:40:40.470 --> 00:40:43.140 So we go through again-- photolithography, 00:40:43.140 --> 00:40:51.670 put our resist down, expose it, develop it, plasma etch-- 00:40:51.670 --> 00:40:54.370 again, controllably etching through the oxide, 00:40:54.370 --> 00:40:57.820 stopping on the silicon layer. 00:40:57.820 --> 00:41:03.650 Remove the photoresist, and now we put down a metal layer. 00:41:03.650 --> 00:41:06.130 Now, typically, what's done for metal layers 00:41:06.130 --> 00:41:09.835 is some form of physical vapor deposition, where-- 00:41:14.530 --> 00:41:18.100 one example is a metal evaporator 00:41:18.100 --> 00:41:22.930 where the wafer will be positioned some distance away 00:41:22.930 --> 00:41:24.820 from a metal source. 00:41:24.820 --> 00:41:29.290 The metal source-- aluminum or other materials-- 00:41:29.290 --> 00:41:36.490 will be heated up, either directly electrically 00:41:36.490 --> 00:41:41.320 or under sputtering kinds of activity, 00:41:41.320 --> 00:41:45.220 such that either individual molecules 00:41:45.220 --> 00:41:49.630 or small agglomerations of molecules become very excited, 00:41:49.630 --> 00:42:01.620 and traject through the vacuum, and build up the layer 00:42:01.620 --> 00:42:04.080 on the surface of the wafer. 00:42:04.080 --> 00:42:06.090 So in this case, this is an older technology. 00:42:06.090 --> 00:42:08.010 They're talking about this being aluminum. 00:42:08.010 --> 00:42:10.188 I'll show you a little bit later that most 00:42:10.188 --> 00:42:12.870 of the most advanced chips are now 00:42:12.870 --> 00:42:17.020 using a copper interconnect, which has other challenges. 00:42:17.020 --> 00:42:20.010 So the basic idea is now, again, we've 00:42:20.010 --> 00:42:22.890 covered the whole surface of the wafer, 00:42:22.890 --> 00:42:26.280 and we selectively go in with a photolithography step 00:42:26.280 --> 00:42:31.170 and remove where we don't want the metal lines protected, 00:42:31.170 --> 00:42:33.720 where I'm not going to want to etch. 00:42:33.720 --> 00:42:36.540 I'm protecting parts of the aluminum, 00:42:36.540 --> 00:42:38.730 and then I do a plasma etch or a chemical 00:42:38.730 --> 00:42:44.660 etch in order to remove the aluminum. 00:42:44.660 --> 00:42:46.790 And then I remove-- 00:42:46.790 --> 00:42:50.840 strip away the photoresist, leaving my structure. 00:42:50.840 --> 00:42:55.910 Now, this is a single level metal, very simple transistor. 00:42:55.910 --> 00:43:03.110 And building up a several billion transistor 00:43:03.110 --> 00:43:06.560 chip, or even a 100 transistor chip, 00:43:06.560 --> 00:43:09.230 we now need to also electrically interconnect 00:43:09.230 --> 00:43:10.790 all of those devices. 00:43:10.790 --> 00:43:14.210 And there's a whole additional sequence of process steps 00:43:14.210 --> 00:43:18.950 that are used to build multiple levels of metal contact, 00:43:18.950 --> 00:43:21.560 but conceptually, they're very similar to those 00:43:21.560 --> 00:43:23.930 that we've seen so far. 00:43:23.930 --> 00:43:26.930 Here I've got access to this individual transistor. 00:43:26.930 --> 00:43:31.700 Clearly, laterally, I can have neighboring transistors 00:43:31.700 --> 00:43:35.810 that I've wired together with the patterned aluminum. 00:43:35.810 --> 00:43:38.240 When you get a certain number of transistors, 00:43:38.240 --> 00:43:42.110 it becomes very hard to have just one level of wiring. 00:43:42.110 --> 00:43:44.120 You need to be able to have a wire that 00:43:44.120 --> 00:43:46.490 goes over another wire, and that's 00:43:46.490 --> 00:43:49.580 where we get to multiple level interconnect structures, 00:43:49.580 --> 00:43:52.670 where one would deposit another layer of silicon 00:43:52.670 --> 00:43:58.760 dioxide or other insulator and then build vertical [INAUDIBLE] 00:43:58.760 --> 00:44:02.540 down from one level to the next to contact multiple streets 00:44:02.540 --> 00:44:08.210 on level 2 with streets on level 1, and so on, up to 6, 00:44:08.210 --> 00:44:12.240 8, or even 10 levels of metal in modern structures. 00:44:12.240 --> 00:44:18.770 AUDIENCE: So [INAUDIBLE] are there 00:44:18.770 --> 00:44:24.722 several transistors above each other or just connectors? 00:44:24.722 --> 00:44:26.180 DUANE BONING: Yeah-- good question. 00:44:26.180 --> 00:44:31.100 Almost all existing semiconductor chips 00:44:31.100 --> 00:44:34.070 are planar processes, meaning all of the transistors 00:44:34.070 --> 00:44:38.090 are in just one plane, just at the surface of the silicon. 00:44:38.090 --> 00:44:40.540 In fact, let me hand this around. 00:44:40.540 --> 00:44:43.100 This just has a copper interconnect 00:44:43.100 --> 00:44:44.750 test pattern on it, so-- 00:44:44.750 --> 00:44:48.590 but this is an 8-inch wafer, and the basic idea 00:44:48.590 --> 00:44:52.640 is we can get that very nicely grown 00:44:52.640 --> 00:44:56.660 silicon layer and control of the surface of the silicon layer. 00:44:56.660 --> 00:44:58.460 It's actually quite difficult to build up 00:44:58.460 --> 00:45:05.190 multiple levels of independent and high-quality silicon 00:45:05.190 --> 00:45:07.110 layers on the wafer. 00:45:07.110 --> 00:45:08.970 There's an awful lot of research-- 00:45:08.970 --> 00:45:16.740 pass that around-- for 3D integrated circuits, 00:45:16.740 --> 00:45:20.190 where one would, in fact, build multiple strata or multiple 00:45:20.190 --> 00:45:23.190 layers of transistors, and then bond the wafers together 00:45:23.190 --> 00:45:26.070 to be able to have in a very compact form factor 00:45:26.070 --> 00:45:30.360 multiple devices in the third dimension. 00:45:30.360 --> 00:45:33.780 You get lots of benefits of smaller footprint. 00:45:33.780 --> 00:45:37.800 At that coarse level of 3D, I would 00:45:37.800 --> 00:45:43.230 say many several memory chip makers are already doing chip 00:45:43.230 --> 00:45:45.390 stacking within one packet. 00:45:45.390 --> 00:45:50.490 So in some of the memory chips, if you were to etch away that-- 00:45:50.490 --> 00:45:54.300 the black packaging casing around one of those chips, 00:45:54.300 --> 00:45:57.840 you might find a stacking. 00:45:57.840 --> 00:46:01.530 But they are not heavily electrically interconnected. 00:46:01.530 --> 00:46:04.810 It's not a fully integrated structure. 00:46:04.810 --> 00:46:06.840 In fact, at the end of the day, they typically 00:46:06.840 --> 00:46:07.860 have bond wires-- 00:46:10.710 --> 00:46:13.890 big macroscopic wires coming in the sides of the chip 00:46:13.890 --> 00:46:17.653 separately at each of the stacking. 00:46:17.653 --> 00:46:18.820 Now, there's other variants. 00:46:18.820 --> 00:46:26.070 So for example, many of the thin film transistor, 00:46:26.070 --> 00:46:30.660 TFT displays will actually have a layer 00:46:30.660 --> 00:46:36.210 of transistors that are a deposited layer of polysilicon, 00:46:36.210 --> 00:46:39.120 not quite the same pure crystalline layer. 00:46:39.120 --> 00:46:42.900 And sometimes those include stacked transistors. 00:46:42.900 --> 00:46:45.030 So there are some technologies. 00:46:45.030 --> 00:46:47.220 They're just not quite the same quality 00:46:47.220 --> 00:46:49.280 or the same high-speed nature. 00:46:52.330 --> 00:46:58.780 OK, anybody detect any other obvious mistakes or errors 00:46:58.780 --> 00:47:01.810 in their pictures? 00:47:01.810 --> 00:47:05.080 Maybe it was just that one, that one inability 00:47:05.080 --> 00:47:09.940 to control of the etch down to a 100 angstroms. 00:47:09.940 --> 00:47:12.340 Now, there's lots of other abstractions in here. 00:47:12.340 --> 00:47:15.040 And one of the other neat things in this picture is it's 00:47:15.040 --> 00:47:15.880 showing-- 00:47:15.880 --> 00:47:18.730 you're building up a fairly complicated geometry 00:47:18.730 --> 00:47:22.150 using controllable processes. 00:47:22.150 --> 00:47:24.280 One of the most important things that you 00:47:24.280 --> 00:47:27.430 have for control of this lateral differentiation 00:47:27.430 --> 00:47:29.410 is photolithography. 00:47:29.410 --> 00:47:32.830 Notice, we were never just depositing directly 00:47:32.830 --> 00:47:34.570 aluminum where we wanted it. 00:47:34.570 --> 00:47:37.090 It's always a-- deposit everywhere, 00:47:37.090 --> 00:47:38.620 because you can do that across-- 00:47:38.620 --> 00:47:41.710 in parallel across the whole surface of the wafer, 00:47:41.710 --> 00:47:45.010 and then have to go back and do a subtractive process 00:47:45.010 --> 00:47:47.800 to typically remove what you want. 00:47:47.800 --> 00:47:52.030 There are very, very few steps where you can selectively 00:47:52.030 --> 00:47:56.840 grow or selectively add material only where you want it. 00:47:56.840 --> 00:48:01.150 So that's an example of a huge constraint 00:48:01.150 --> 00:48:04.610 in semiconductor processing. 00:48:04.610 --> 00:48:06.490 So what I want to do now, with that 00:48:06.490 --> 00:48:09.850 as the overview of the unit process 00:48:09.850 --> 00:48:12.460 and how they all stack up to build 00:48:12.460 --> 00:48:14.290 a more complicated structure-- 00:48:14.290 --> 00:48:16.240 I want to talk a little bit about of 00:48:16.240 --> 00:48:20.260 the input-output picture of semiconductor processing. 00:48:20.260 --> 00:48:24.880 This is very similar to our generic picture that-- 00:48:24.880 --> 00:48:27.430 hopefully you guys have started reading that process control 00:48:27.430 --> 00:48:28.420 overview-- 00:48:28.420 --> 00:48:32.570 where we've got different inputs to the unit process, 00:48:32.570 --> 00:48:35.440 including the raw material, the wafer. 00:48:35.440 --> 00:48:38.260 We've got inputs in terms of the environment 00:48:38.260 --> 00:48:40.210 that we create around the wafer-- 00:48:40.210 --> 00:48:44.680 that vacuum process, the chemical [INAUDIBLE],, 00:48:44.680 --> 00:48:50.590 the gas ambient used in plasma etching; and then 00:48:50.590 --> 00:48:52.930 other control factors on the machine 00:48:52.930 --> 00:48:55.190 or the facility-- things like thermal control 00:48:55.190 --> 00:48:58.120 in photolithography-- to be able to ensure 00:48:58.120 --> 00:49:01.120 that there's not thermal expansion of the components. 00:49:01.120 --> 00:49:04.840 And then we get changes in many of these wafers, many 00:49:04.840 --> 00:49:05.830 of these states. 00:49:05.830 --> 00:49:07.540 Many of these are desirable. 00:49:07.540 --> 00:49:11.410 We saw the change in the wafer state in terms of the geometry, 00:49:11.410 --> 00:49:14.050 as well as things like doping processes 00:49:14.050 --> 00:49:17.800 that change the conductivity of the silicon layers. 00:49:17.800 --> 00:49:19.690 But we also often have the side effects 00:49:19.690 --> 00:49:23.300 changes in the state of the equipment. 00:49:23.300 --> 00:49:25.540 And this turns out to be a big deal in much 00:49:25.540 --> 00:49:27.160 of semiconductor control. 00:49:27.160 --> 00:49:30.790 So for example, every one of those coating processes 00:49:30.790 --> 00:49:32.830 occurs in some kind of a chamber. 00:49:32.830 --> 00:49:34.270 I coat up a film. 00:49:34.270 --> 00:49:36.970 I coat aluminum on the surface of the wafer. 00:49:36.970 --> 00:49:40.570 What do you think happens to the rest of the chamber? 00:49:40.570 --> 00:49:42.370 It gets coated too. 00:49:42.370 --> 00:49:45.310 So over time, you will often get buildup of material 00:49:45.310 --> 00:49:47.050 in the rest of the equipment, and there 00:49:47.050 --> 00:49:50.530 will need to be other steps to go in and clean or reset 00:49:50.530 --> 00:49:52.370 the equipment state. 00:49:52.370 --> 00:49:55.390 So actually, we often are worried 00:49:55.390 --> 00:49:57.455 not only about the product and what's 00:49:57.455 --> 00:49:59.830 happening with the product, but in manufacturing control, 00:49:59.830 --> 00:50:01.330 we're also very worried about what's 00:50:01.330 --> 00:50:03.290 happening with the equipment. 00:50:03.290 --> 00:50:06.850 So what we often don't have control over 00:50:06.850 --> 00:50:08.380 are all these disturbances. 00:50:08.380 --> 00:50:11.710 There may be variations in the process coming 00:50:11.710 --> 00:50:14.320 from lots of different sources. 00:50:14.320 --> 00:50:16.210 Some might be the incoming material. 00:50:16.210 --> 00:50:18.370 In this case, if there's variability 00:50:18.370 --> 00:50:22.270 in the starting wafer, or the wafer as processed up 00:50:22.270 --> 00:50:25.210 to some step, that might interact with the step 00:50:25.210 --> 00:50:29.770 that we're now performing, and limit our ability to control. 00:50:29.770 --> 00:50:32.200 And then similarly, there may be influences 00:50:32.200 --> 00:50:36.280 of variation coming from the machine, or the facility, 00:50:36.280 --> 00:50:38.262 or the wafer environment. 00:50:38.262 --> 00:50:39.970 So what I want to do is talk a little bit 00:50:39.970 --> 00:50:43.630 about some of those different kinds of variations, 00:50:43.630 --> 00:50:45.890 and build on what we've seen here. 00:50:45.890 --> 00:50:50.240 Now, I mentioned this a little bit last time. 00:50:50.240 --> 00:50:53.080 It used to be 10 years ago, 15 years ago, 00:50:53.080 --> 00:50:56.470 if we talked about yield-- 00:50:56.470 --> 00:50:58.600 the percentage of functioning devices 00:50:58.600 --> 00:51:01.180 that came out of semiconductor fab-- 00:51:01.180 --> 00:51:07.965 the main worry limiting yield was particle defects. 00:51:07.965 --> 00:51:10.090 And you can imagine, we're talking about very, very 00:51:10.090 --> 00:51:11.530 small features here. 00:51:11.530 --> 00:51:18.260 And if pieces of extraneous matter were to fall between, 00:51:18.260 --> 00:51:22.240 say, two metal lines that would cause an electrical short-- 00:51:22.240 --> 00:51:23.920 or could cause an electrical short-- 00:51:23.920 --> 00:51:27.510 and now the device does not function. 00:51:27.510 --> 00:51:29.980 It does not function correctly. 00:51:29.980 --> 00:51:33.450 In other cases, the particle-- if it happened 00:51:33.450 --> 00:51:39.930 to appear in the photoresist, it might cause an open 00:51:39.930 --> 00:51:41.160 in one of these lines. 00:51:41.160 --> 00:51:49.710 It might prevent-- or cause me to actually regions 00:51:49.710 --> 00:51:51.070 where I didn't want to. 00:51:51.070 --> 00:51:52.650 So not only can I have shorts-- 00:51:52.650 --> 00:51:54.360 I might have opens between lines. 00:51:54.360 --> 00:51:58.740 And this defect control was the primary source 00:51:58.740 --> 00:52:01.650 of yield loss in the fab. 00:52:04.821 --> 00:52:10.020 That's why, if you go into an IC fab, it's a clean room. 00:52:10.020 --> 00:52:12.720 Everybody's wearing clean room garments. 00:52:12.720 --> 00:52:15.240 There's incredible amounts of airflow 00:52:15.240 --> 00:52:19.320 to filter out and remove all kinds of dust 00:52:19.320 --> 00:52:21.810 particles or other extraneous matter 00:52:21.810 --> 00:52:25.230 down to very, very tiny dimensions. 00:52:25.230 --> 00:52:27.630 That's really the measures that have 00:52:27.630 --> 00:52:29.940 been taken in order to get the cleanliness 00:52:29.940 --> 00:52:32.400 you need in order to-- 00:52:32.400 --> 00:52:35.340 not eliminate, but get those particles down 00:52:35.340 --> 00:52:40.620 to a particle density and down to a presence of size 00:52:40.620 --> 00:52:44.730 that are small enough not to have too big of a yield impact. 00:52:44.730 --> 00:52:49.920 What I mean by size is imagine that little dust particle 00:52:49.920 --> 00:52:55.080 is only a quarter of the width of any of the minimum feature 00:52:55.080 --> 00:52:57.180 sizes on your structure. 00:52:57.180 --> 00:53:01.860 Well, that might mean I lose a quarter of the width of one 00:53:01.860 --> 00:53:04.890 of those metal lines, but at least it still conducts. 00:53:04.890 --> 00:53:07.500 It might have a slightly higher resistance than I expect, 00:53:07.500 --> 00:53:10.320 but functionally, I'm still OK. 00:53:10.320 --> 00:53:13.650 Similarly, if it's too small of a particle 00:53:13.650 --> 00:53:16.990 to bridge between lines, I'm not going to have a short. 00:53:16.990 --> 00:53:19.770 So the idea is to control the particles down 00:53:19.770 --> 00:53:21.090 to a certain feature. 00:53:21.090 --> 00:53:23.880 Now, there are some very interesting manufacturing 00:53:23.880 --> 00:53:26.370 control technologies that are used 00:53:26.370 --> 00:53:31.440 to characterize the presence and density 00:53:31.440 --> 00:53:33.960 of these kinds of particles. 00:53:33.960 --> 00:53:39.210 And what I pictured here is a metal layout, 00:53:39.210 --> 00:53:41.970 a metal patterned structure-- referred to as a nest 00:53:41.970 --> 00:53:42.930 structure-- 00:53:42.930 --> 00:53:50.010 that allows one to build a large number of these snaking lines, 00:53:50.010 --> 00:53:55.440 and electrically connect between these different lines 00:53:55.440 --> 00:54:00.930 in order to test if there is a bridging defect between lines, 00:54:00.930 --> 00:54:03.310 and count the number of those events. 00:54:03.310 --> 00:54:06.090 So you build this structure to spatially sample 00:54:06.090 --> 00:54:08.880 as large an area as you can to try to capture 00:54:08.880 --> 00:54:11.130 some number of these defects. 00:54:11.130 --> 00:54:13.290 And you can also use this structure 00:54:13.290 --> 00:54:16.450 to characterize the size of these defects, 00:54:16.450 --> 00:54:19.090 especially if they're relatively large. 00:54:19.090 --> 00:54:21.900 So for example, if I had a big particle that 00:54:21.900 --> 00:54:26.760 bridged three of these lines, I know, within certain bounds, 00:54:26.760 --> 00:54:32.940 that I've got a particle between some size interval. 00:54:32.940 --> 00:54:34.800 And so that's what's shown over here 00:54:34.800 --> 00:54:38.400 is a defect count as a function of the size, 00:54:38.400 --> 00:54:42.870 in microns, of different particles for these large area 00:54:42.870 --> 00:54:44.760 sampling structures. 00:54:44.760 --> 00:54:48.384 Now, this turns out to be still a-- 00:54:48.384 --> 00:54:50.910 an important part of semiconductor fabrication 00:54:50.910 --> 00:54:53.400 is understanding your defect densities, 00:54:53.400 --> 00:55:00.270 defect counts, understanding what the typical sizes are, 00:55:00.270 --> 00:55:03.810 what levels of the process they come in. 00:55:03.810 --> 00:55:06.510 Are you mostly getting these in aluminum deposition? 00:55:06.510 --> 00:55:09.630 Are you mostly getting these in other etch processes? 00:55:09.630 --> 00:55:12.690 And actually, then feeding that information 00:55:12.690 --> 00:55:18.150 to design for manufacturability to optimize 00:55:18.150 --> 00:55:20.850 the layout of the circuit to minimize 00:55:20.850 --> 00:55:27.510 the likelihood of a particle falling in a bad location. 00:55:27.510 --> 00:55:29.910 And we'll talk about that, I think, somewhere 00:55:29.910 --> 00:55:33.120 near the midpoint or second-- 00:55:33.120 --> 00:55:34.900 last third of the course. 00:55:34.900 --> 00:55:38.340 We'll talk about yield modeling and some of the technologies 00:55:38.340 --> 00:55:43.080 that are used for characterizing, statistically, 00:55:43.080 --> 00:55:48.570 the point defects, particle defects, and some 00:55:48.570 --> 00:55:53.730 of the strategies used for optimizing or minimizing impact 00:55:53.730 --> 00:55:55.110 on circuits. 00:55:55.110 --> 00:55:57.210 But what is becoming much more important-- 00:55:57.210 --> 00:55:59.730 and we mentioned this on Tuesday as well-- 00:55:59.730 --> 00:56:01.680 is parametric control. 00:56:01.680 --> 00:56:04.960 And in some cases, even these defect 00:56:04.960 --> 00:56:07.620 controls turn into parametric control problems 00:56:07.620 --> 00:56:12.210 if what I'm worried about is not so much yes-no functionality, 00:56:12.210 --> 00:56:16.440 but changes in the resistance of lines because 00:56:16.440 --> 00:56:18.150 of the presence of defects. 00:56:18.150 --> 00:56:21.720 And so much more broadly than defects, 00:56:21.720 --> 00:56:26.730 we're much more concerned with continuous parameter 00:56:26.730 --> 00:56:30.750 control of geometry as well as some of these other properties 00:56:30.750 --> 00:56:32.400 that we saw in the sequence. 00:56:32.400 --> 00:56:36.360 So for example, that critical dimension control 00:56:36.360 --> 00:56:42.260 might be the channel length of transistors on my device, 00:56:42.260 --> 00:56:44.300 and inherently, you're going to have 00:56:44.300 --> 00:56:48.260 some statistical distribution on channel length. 00:56:48.260 --> 00:56:51.020 Call that L. 00:56:51.020 --> 00:56:54.360 So for example, if I were-- let me start down here-- 00:56:54.360 --> 00:57:01.240 if I were to sample many nominally identical transistors 00:57:01.240 --> 00:57:03.220 that were laid out exactly the same, 00:57:03.220 --> 00:57:05.470 were assumed to behave exactly the same, 00:57:05.470 --> 00:57:08.200 and I measured some electrical characteristic 00:57:08.200 --> 00:57:10.210 or some geometric characteristic, 00:57:10.210 --> 00:57:12.790 I might get a distribution-- 00:57:12.790 --> 00:57:14.200 drawn here as a Gaussian. 00:57:14.200 --> 00:57:17.500 It's not always, but very often, that's a great model 00:57:17.500 --> 00:57:19.000 and I might have some distribution 00:57:19.000 --> 00:57:21.130 of that across the chip. 00:57:21.130 --> 00:57:24.880 And very often, there are inherent physical limitations 00:57:24.880 --> 00:57:32.150 in the process that give rise to those sources of variation, 00:57:32.150 --> 00:57:35.050 some of which we'll come back to-- might be systematic 00:57:35.050 --> 00:57:36.760 or might be random. 00:57:36.760 --> 00:57:40.540 Now, what's interesting is we have a physical nesting. 00:57:40.540 --> 00:57:42.640 On the wafer, we have many chips. 00:57:42.640 --> 00:57:44.650 Now, if I were to take and measure 00:57:44.650 --> 00:57:47.230 the same transistor on each chip, 00:57:47.230 --> 00:57:49.390 I would also get a distribution. 00:57:49.390 --> 00:57:53.080 I have a chip-to-chip variability in parameters, 00:57:53.080 --> 00:57:56.620 and often that will come because of different physical causes. 00:57:56.620 --> 00:58:00.190 It may be we're doing that photolithographic stepping, 00:58:00.190 --> 00:58:04.360 and every time, I have a little bit different overlay control 00:58:04.360 --> 00:58:06.010 or offset control. 00:58:06.010 --> 00:58:09.190 So the source of this may be-- 00:58:09.190 --> 00:58:14.770 this distribution may be because of wafer level 00:58:14.770 --> 00:58:17.410 or across wafer sources of variation that 00:58:17.410 --> 00:58:20.470 are very different than the sources of physical variation 00:58:20.470 --> 00:58:24.550 of replication of transistors within the chip. 00:58:24.550 --> 00:58:27.640 And we also can have wafer-to-wafer variations. 00:58:27.640 --> 00:58:30.790 Again, if I were to either calculate the average over one 00:58:30.790 --> 00:58:33.160 wafer, or maybe just sample exactly 00:58:33.160 --> 00:58:37.090 the same location on every wafer and stack that up 00:58:37.090 --> 00:58:41.950 across 24 wafers or large numbers of wafers that 00:58:41.950 --> 00:58:47.200 might be in one lot, processed even relatively close in time 00:58:47.200 --> 00:58:50.650 to each other, there's also going to be a deviation. 00:58:50.650 --> 00:58:55.780 And that might arise because of changes in the equipment state 00:58:55.780 --> 00:58:58.390 from one run to the next. 00:58:58.390 --> 00:59:03.310 The first wafer-- it may have a pristine equipment 00:59:03.310 --> 00:59:07.060 with no build-up on the-- of material on the wafer wall. 00:59:07.060 --> 00:59:10.180 The next wafer might see a slightly different process-- 00:59:10.180 --> 00:59:14.830 unintentionally-- than the previous one because of changes 00:59:14.830 --> 00:59:18.040 or degradation in the equipment state over time 00:59:18.040 --> 00:59:19.840 affecting that wafer state. 00:59:19.840 --> 00:59:21.650 That might be an example. 00:59:21.650 --> 00:59:23.560 And then finally, in semiconductor fab, 00:59:23.560 --> 00:59:27.850 we typically are processing a lot of wafers. 00:59:27.850 --> 00:59:30.370 That may be 24 wafers at a time. 00:59:30.370 --> 00:59:32.710 And from one lot to the next, these 00:59:32.710 --> 00:59:36.550 might be processed at substantially different points 00:59:36.550 --> 00:59:37.160 in time. 00:59:37.160 --> 00:59:40.120 And there may be another distribution associated 00:59:40.120 --> 00:59:42.040 with that, and physical sources are 00:59:42.040 --> 00:59:44.110 causes of that variation that are 00:59:44.110 --> 00:59:49.840 different than these other spatial or temporal sources. 00:59:49.840 --> 00:59:52.540 Some companies-- and there's not a lot of them 00:59:52.540 --> 00:59:57.880 these days-- have multiple fabs, so I could continue this up. 00:59:57.880 --> 01:00:01.300 Intel in particular is very famous for making 01:00:01.300 --> 01:00:04.210 the same product in multiple fabs, in multiple states, 01:00:04.210 --> 01:00:07.390 and in fact, multiple countries around the world. 01:00:07.390 --> 01:00:11.315 And they work very, very hard to have matching from one fab 01:00:11.315 --> 01:00:12.940 to the other, in terms of the equipment 01:00:12.940 --> 01:00:16.660 and so on, to minimize fab-to-fab deviations 01:00:16.660 --> 01:00:18.400 or differences in their chips. 01:00:18.400 --> 01:00:21.070 They really don't want people saying, 01:00:21.070 --> 01:00:26.350 I'm only going to buy my Pentium or Itanium 01:00:26.350 --> 01:00:29.380 chip from the Albuquerque fab, because it's 01:00:29.380 --> 01:00:33.720 better than the one from Portland or whatever. 01:00:33.720 --> 01:00:35.560 They really want to minimize that. 01:00:35.560 --> 01:00:39.630 So you've got extensions up the hierarchy as well. 01:00:42.342 --> 01:00:43.800 Now, if we were to actually zoom in 01:00:43.800 --> 01:00:47.130 on one of those distributions, what's also 01:00:47.130 --> 01:00:49.140 going to be very interesting is trying 01:00:49.140 --> 01:00:52.260 to understand what the sources of variation 01:00:52.260 --> 01:00:55.230 are at each of the spatial scales. 01:00:55.230 --> 01:00:58.710 And you might have a fairly complex distribution, say, 01:00:58.710 --> 01:01:00.090 over channel length. 01:01:00.090 --> 01:01:03.570 And what's often very, very much the case, and very interesting 01:01:03.570 --> 01:01:08.010 is that total distribution is the compounded effective 01:01:08.010 --> 01:01:13.930 multiple additional sources that are convolved together. 01:01:13.930 --> 01:01:19.600 And a lot of work will be done in designing test procedures, 01:01:19.600 --> 01:01:22.060 designing process control charts, 01:01:22.060 --> 01:01:25.840 and whatnot to be able to track individual contributors 01:01:25.840 --> 01:01:31.540 and separate them out into the component sources of variation. 01:01:31.540 --> 01:01:34.460 Why do you want to do this? 01:01:34.460 --> 01:01:38.390 If you can identify individual sources, 01:01:38.390 --> 01:01:42.400 that's crucial to being able to go and squeeze them down. 01:01:42.400 --> 01:01:46.090 You got to know what the source is in order to remove it. 01:01:46.090 --> 01:01:49.390 What else is the case often is that some of these 01:01:49.390 --> 01:01:51.790 are not completely random. 01:01:51.790 --> 01:01:54.490 Many of the sources of variation have 01:01:54.490 --> 01:01:57.910 a systematic physical cause. 01:01:57.910 --> 01:02:05.090 And if we understand what is systematic or repeatable 01:02:05.090 --> 01:02:08.180 every time you run this, you might actually 01:02:08.180 --> 01:02:13.040 find that the transistor in the upper right corner of the chip 01:02:13.040 --> 01:02:15.960 is a little bit too wide. 01:02:15.960 --> 01:02:17.940 You might then track that back to 01:02:17.940 --> 01:02:20.490 the photolithographic imperfection that's 01:02:20.490 --> 01:02:21.510 causing that. 01:02:21.510 --> 01:02:25.350 Once you know that, you can compensate and counteract 01:02:25.350 --> 01:02:28.500 that source of variation. 01:02:28.500 --> 01:02:33.443 A lot of the work is trying to break these down. 01:02:33.443 --> 01:02:35.610 So let me give you a little bit more example of some 01:02:35.610 --> 01:02:40.920 of these sources of variation, and the tools and techniques 01:02:40.920 --> 01:02:42.990 that are evolving to handle them. 01:02:46.320 --> 01:02:48.378 Let me zoom into one unit process. 01:02:48.378 --> 01:02:49.920 We've done actually a lot of research 01:02:49.920 --> 01:02:53.670 on chemical mechanical polishing in semiconductor fab. 01:02:53.670 --> 01:03:00.470 And the basic process is you take that wafer, you press it-- 01:03:00.470 --> 01:03:02.270 or you hold it in a wafer carrier 01:03:02.270 --> 01:03:06.890 and press it face down onto a rotating table 01:03:06.890 --> 01:03:11.360 or [INAUDIBLE] to which is affixed an abrasive path. 01:03:11.360 --> 01:03:14.510 You also drip a wet abrasive slurry-- 01:03:14.510 --> 01:03:19.010 so it's a very, very fine particle grit-- 01:03:19.010 --> 01:03:22.190 in a chemically active slurry, and then 01:03:22.190 --> 01:03:28.550 you rotate both the wafer and the pad, or the table. 01:03:28.550 --> 01:03:32.810 And the basic goal of this is to flatten 01:03:32.810 --> 01:03:38.990 the surface of the wafer, if you go back to this picture, 01:03:38.990 --> 01:03:43.610 with even one level of metal, look at all of the topography, 01:03:43.610 --> 01:03:45.950 the differences in heights that are generated, 01:03:45.950 --> 01:03:49.070 because we're etching down, filling in, and so on. 01:03:49.070 --> 01:03:52.760 If one were to try to build multiple levels of metal, 01:03:52.760 --> 01:03:54.380 you have a real problem here. 01:03:54.380 --> 01:03:57.860 You keep building up in some regions where 01:03:57.860 --> 01:04:00.140 you have more metal, and in those regions 01:04:00.140 --> 01:04:04.190 where you don't, you get thinner and thinner by comparison. 01:04:04.190 --> 01:04:10.130 That becomes a huge challenge in terms of other processes, 01:04:10.130 --> 01:04:13.250 like photolithography-- talked about that depth of focus. 01:04:13.250 --> 01:04:18.170 Now I want a pattern or image at the top of one of these levels, 01:04:18.170 --> 01:04:20.900 and I've got also these recessed regions-- 01:04:20.900 --> 01:04:25.400 become very difficult to image, say, a metal 4 layer. 01:04:25.400 --> 01:04:32.315 And so CMP has been created to basically 01:04:32.315 --> 01:04:37.070 abrade away the raised surfaces, get it 01:04:37.070 --> 01:04:41.200 down to a planar surface. 01:04:41.200 --> 01:04:46.330 Now, one of the big problems in CMP 01:04:46.330 --> 01:04:52.490 is the process itself is often not all that stable. 01:04:52.490 --> 01:04:56.540 That polishing pad, that abrasive path-- 01:04:56.540 --> 01:04:58.220 what happens if you use sandpaper 01:04:58.220 --> 01:05:00.110 for a while on a piece of wood? 01:05:00.110 --> 01:05:04.070 Well, you smooth out the grain or whatever 01:05:04.070 --> 01:05:05.330 in the piece of wood. 01:05:05.330 --> 01:05:08.150 What happens to your sandpaper? 01:05:08.150 --> 01:05:10.560 It also wears-- fills in. 01:05:10.560 --> 01:05:12.110 It gets gooky. 01:05:12.110 --> 01:05:14.900 Basically, it changes its state-- 01:05:14.900 --> 01:05:16.850 the process and the equipment changes 01:05:16.850 --> 01:05:19.260 it state over fabrication as well. 01:05:19.260 --> 01:05:21.920 And if you looked at the normalized removal rate 01:05:21.920 --> 01:05:27.890 for a 350-wafer sequence, you will often 01:05:27.890 --> 01:05:31.730 find drift in the removal rate. 01:05:31.730 --> 01:05:34.010 You might start out with a fairly high removal rate, 01:05:34.010 --> 01:05:36.230 and over time, it drifts down. 01:05:36.230 --> 01:05:42.950 This is something like at 20% or 40% kind of drift. 01:05:42.950 --> 01:05:45.320 Similarly, if you looked at the wafer-- 01:05:45.320 --> 01:05:49.460 measured some pattern, some eight-sample point, 01:05:49.460 --> 01:05:52.010 and calculated a non-uniformity metric-- 01:05:52.010 --> 01:05:56.650 maybe its standard deviation of those points-- 01:05:56.650 --> 01:06:00.400 one would find-- maybe you can see 01:06:00.400 --> 01:06:04.360 it-- looks like there's a slight increase in that non-uniformity 01:06:04.360 --> 01:06:05.690 over time. 01:06:05.690 --> 01:06:08.930 The pad is not quite as uniform as well. 01:06:08.930 --> 01:06:13.660 So this is the kind of temporal wafer-to-wafer variation 01:06:13.660 --> 01:06:19.030 that you don't want, and would like to understand it. 01:06:19.030 --> 01:06:21.490 If there's a systematic trend, then maybe there 01:06:21.490 --> 01:06:24.850 are control approaches that can be used to compensate 01:06:24.850 --> 01:06:26.060 or correct for that. 01:06:26.060 --> 01:06:26.815 Yeah? 01:06:26.815 --> 01:06:29.605 AUDIENCE: This polishing seems to be a bad idea to me. 01:06:29.605 --> 01:06:36.550 [INAUDIBLE] a way to getting, like you said, [INAUDIBLE] 01:06:36.550 --> 01:06:37.412 DUANE BONING: Yeah. 01:06:37.412 --> 01:06:39.370 The semiconductor industry really got its start 01:06:39.370 --> 01:06:43.930 about 1960, and for 30 years, it was all 01:06:43.930 --> 01:06:46.630 about defects, those particles. 01:06:46.630 --> 01:06:49.750 Keep them away from the wafer at whatever cost. 01:06:49.750 --> 01:06:54.280 And then primarily, folks from IBM around 1990 01:06:54.280 --> 01:06:57.190 said, yeah, we're going to pour slurries 01:06:57.190 --> 01:07:00.773 with 100-nanometer particles on it, 01:07:00.773 --> 01:07:02.440 and then we're going to rub the heck out 01:07:02.440 --> 01:07:04.240 of the surface of your wafer. 01:07:04.240 --> 01:07:06.640 And everybody thought they were crazy. 01:07:06.640 --> 01:07:15.010 But it turns out that, first off, the control of the process 01:07:15.010 --> 01:07:18.910 can be very good in terms of not a very, very 01:07:18.910 --> 01:07:20.920 fine abrading of the surface. 01:07:20.920 --> 01:07:22.480 So you're not gouging out. 01:07:22.480 --> 01:07:27.010 You're really doing almost nanometer-by-nanometer scale 01:07:27.010 --> 01:07:28.240 abrasion. 01:07:28.240 --> 01:07:30.260 But then you still have all those particles. 01:07:30.260 --> 01:07:34.900 So a lot of the work was very, very effective post-polish 01:07:34.900 --> 01:07:39.460 cleaning processes that involve chemical baths, 01:07:39.460 --> 01:07:43.300 that involve brush cleaning, in fact, 01:07:43.300 --> 01:07:47.170 that involve hydroponic agitation to levitate 01:07:47.170 --> 01:07:51.820 the particles off of the surface of the wafer in a clean bath-- 01:07:51.820 --> 01:08:00.350 that they actually found no appreciable defect-oriented 01:08:00.350 --> 01:08:04.250 yield loss, once you did those extreme measures 01:08:04.250 --> 01:08:05.720 to clean up the wafer. 01:08:05.720 --> 01:08:08.720 And in fact, the irony ended up being 01:08:08.720 --> 01:08:15.080 that the CMP processed, by planarizing, actually 01:08:15.080 --> 01:08:17.689 improved the defectivity. 01:08:17.689 --> 01:08:23.000 Because many of these particles might be present in layer 3, 01:08:23.000 --> 01:08:27.500 you've got a lump, but it didn't destroy the action of level 3. 01:08:27.500 --> 01:08:30.859 But if it's sticking up, by the time you go in to level 4 01:08:30.859 --> 01:08:33.350 and you do a metalization over that, 01:08:33.350 --> 01:08:35.270 well, now you've got a problem. 01:08:35.270 --> 01:08:39.680 And the CMP process, which would go in and flatten or planarize 01:08:39.680 --> 01:08:42.979 between levels, would actually chop the heads off 01:08:42.979 --> 01:08:46.310 of these defects and reduce their impact 01:08:46.310 --> 01:08:47.890 for subsequent levels. 01:08:50.569 --> 01:08:55.010 But it is a fascinating story of the adoption of CMP, 01:08:55.010 --> 01:09:01.790 because it was so counterintuitive of a process, 01:09:01.790 --> 01:09:03.649 exactly as you said. 01:09:03.649 --> 01:09:09.080 So we'll come back at the end or later to control strategies, 01:09:09.080 --> 01:09:10.819 for dealing with this-- 01:09:10.819 --> 01:09:11.750 of the course. 01:09:11.750 --> 01:09:14.000 Basically, this kind of a drift-- 01:09:14.000 --> 01:09:16.640 you could start to think, well, I can measure this, 01:09:16.640 --> 01:09:19.580 and maybe what I would like to do on subsequent runs-- 01:09:19.580 --> 01:09:22.430 if my removal rate has drifted down, 01:09:22.430 --> 01:09:24.350 I'd like a strategy where I polish 01:09:24.350 --> 01:09:26.899 a little bit longer or I press a little bit harder-- 01:09:26.899 --> 01:09:29.220 these sorts of things. 01:09:29.220 --> 01:09:31.771 AUDIENCE: So you only do this polishing at the very end? 01:09:31.771 --> 01:09:32.479 DUANE BONING: No. 01:09:32.479 --> 01:09:33.635 You do it at each level-- 01:09:33.635 --> 01:09:34.593 AUDIENCE: At each level 01:09:34.593 --> 01:09:37.850 DUANE BONING: --each metal level, as well as 01:09:37.850 --> 01:09:39.950 in some other places. 01:09:39.950 --> 01:09:45.710 So it's actually used repeatedly in multilevel interconnect. 01:09:45.710 --> 01:09:48.080 Here's an example of a little test chip 01:09:48.080 --> 01:09:51.500 to try to characterize some of those spatial variations, 01:09:51.500 --> 01:09:54.380 and decompose them that we talked about. 01:09:54.380 --> 01:10:01.210 This is a chip design that has a few thousand ring oscillators. 01:10:01.210 --> 01:10:06.560 A ring oscillator is a chain of an odd number of inverters, 01:10:06.560 --> 01:10:09.590 each of which does a logic zero to one or one 01:10:09.590 --> 01:10:11.900 to zero computation. 01:10:11.900 --> 01:10:14.840 And if you organize those in a ring fashion, 01:10:14.840 --> 01:10:17.300 it oscillates at some high frequency 01:10:17.300 --> 01:10:20.420 that indicates the speed of the individual transistors 01:10:20.420 --> 01:10:21.630 in that structure. 01:10:21.630 --> 01:10:25.610 So a ring oscillator is a wonderful stand-in electronic 01:10:25.610 --> 01:10:30.170 circuit telling you a lot about the speed of your technology. 01:10:30.170 --> 01:10:34.460 What we did is built a tiled architecture, 01:10:34.460 --> 01:10:38.090 where we've got thousands of these structures; replicated 01:10:38.090 --> 01:10:41.720 spatially, so now we can measure multiple instances 01:10:41.720 --> 01:10:44.270 and see if there's a spatial pattern; 01:10:44.270 --> 01:10:45.800 well as we can also play with some 01:10:45.800 --> 01:10:50.120 of the design parameters of each of those ring oscillators. 01:10:50.120 --> 01:10:52.010 And in particular, we can do things 01:10:52.010 --> 01:10:55.280 like take that silicon gate electrode 01:10:55.280 --> 01:10:57.830 and split it into three of them. 01:10:57.830 --> 01:11:01.220 We can play with the spacing between those electrodes. 01:11:01.220 --> 01:11:04.940 We can orient those [INAUDIBLE] vertically 01:11:04.940 --> 01:11:07.940 or horizontally on the layout. 01:11:07.940 --> 01:11:11.270 We can also look at the effective nearby structures. 01:11:11.270 --> 01:11:15.440 For example, how dense per unit area 01:11:15.440 --> 01:11:21.110 do you have transistors or polysilicon gate electrodes? 01:11:21.110 --> 01:11:24.170 Would that have an effect on the ring oscillator? 01:11:24.170 --> 01:11:26.135 And now, if you go out and build this, 01:11:26.135 --> 01:11:28.970 this is a wonderful kind of data, 01:11:28.970 --> 01:11:32.720 where you can aggregate or map out 01:11:32.720 --> 01:11:35.420 the data at these different spatial scales 01:11:35.420 --> 01:11:37.290 to look for trends. 01:11:37.290 --> 01:11:40.970 So for example, if we look at the wafer scale variation 01:11:40.970 --> 01:11:42.930 in the ring oscillator speed, we've 01:11:42.930 --> 01:11:45.800 got something like 30 chips in the upper half of one 01:11:45.800 --> 01:11:46.970 of these wafers. 01:11:46.970 --> 01:11:48.800 And mapped out here and the color 01:11:48.800 --> 01:11:54.900 is the average ring oscillator speed from high to low. 01:11:54.900 --> 01:12:01.110 And you can see a spatial trend from one side of the wafer 01:12:01.110 --> 01:12:01.710 to the other. 01:12:01.710 --> 01:12:04.860 This is telling us there is a wafer level non-uniformity, 01:12:04.860 --> 01:12:08.970 and in fact, that across wafer variation is about 9% 01:12:08.970 --> 01:12:12.400 in speed of these devices. 01:12:12.400 --> 01:12:14.070 You can also then start to look-- 01:12:14.070 --> 01:12:15.870 I guess that's the same thing-- 01:12:15.870 --> 01:12:17.850 you can also start to look and say, 01:12:17.850 --> 01:12:22.200 depending on how you designed the transistor, 01:12:22.200 --> 01:12:26.910 what kind of offsets do you get in the frequency 01:12:26.910 --> 01:12:29.700 and what kind of variation do you 01:12:29.700 --> 01:12:35.500 get in the speed of the devices? 01:12:35.500 --> 01:12:39.510 And what's interesting here is that many of these ring 01:12:39.510 --> 01:12:42.360 oscillator designs are-- from the circuit designer 01:12:42.360 --> 01:12:45.780 perspective, they think of them as identical. 01:12:45.780 --> 01:12:49.170 But in fabrication, because of neighborhood 01:12:49.170 --> 01:12:53.340 or nearby structures, in fact, there are slight deviations. 01:12:53.340 --> 01:12:55.380 So nominally identical transistors 01:12:55.380 --> 01:13:00.360 may, in fact, have substantial systematic, highly repeatable 01:13:00.360 --> 01:13:01.500 effects. 01:13:01.500 --> 01:13:05.400 And if the manufacturing line can capture and characterize 01:13:05.400 --> 01:13:10.190 those, and send that information to design, 01:13:10.190 --> 01:13:12.260 design can compensate. 01:13:12.260 --> 01:13:14.090 So this is another theme. 01:13:14.090 --> 01:13:18.410 This design and manufacturing link can be very important. 01:13:18.410 --> 01:13:24.950 We can also map out identical transistors 01:13:24.950 --> 01:13:26.960 within one of these chips. 01:13:26.960 --> 01:13:31.850 And here again, you can see a top-to-bottom variation 01:13:31.850 --> 01:13:34.260 in the ring oscillator speed. 01:13:34.260 --> 01:13:37.250 And in this case, that within each individual chip 01:13:37.250 --> 01:13:41.585 is about 4% in this particular case, 01:13:41.585 --> 01:13:42.710 which is quite interesting. 01:13:42.710 --> 01:13:47.240 Notice we said there's 9% across the whole wafer. 01:13:47.240 --> 01:13:51.170 I might have 10 chips lined up in a line across the wafer. 01:13:51.170 --> 01:13:53.660 If I were to say, from center to edge, 01:13:53.660 --> 01:13:55.310 I have a systematic trend-- 01:13:55.310 --> 01:13:57.500 or from one edge of the way for the other, 01:13:57.500 --> 01:14:02.300 the systematic trend of about 10%, and I 01:14:02.300 --> 01:14:06.390 map that down to 1/10, because I've 01:14:06.390 --> 01:14:09.270 got 10 ships, that would be about a 1% variation, 01:14:09.270 --> 01:14:12.120 you might expect, because of wafer level sources 01:14:12.120 --> 01:14:13.680 on each chip. 01:14:13.680 --> 01:14:17.770 But what we find is something like 4% That's telling us 01:14:17.770 --> 01:14:21.790 there's a different source of physical variation at work 01:14:21.790 --> 01:14:24.160 within each of the chips. 01:14:24.160 --> 01:14:26.920 And then you can also look for other systematic effects-- 01:14:26.920 --> 01:14:33.200 things like the proximity of one [INAUDIBLE] to another 01:14:33.200 --> 01:14:36.240 can have photolithographic effects. 01:14:36.240 --> 01:14:39.350 And in particular, that can result in an offset, 01:14:39.350 --> 01:14:42.860 depending on whether I have 1 micron, or 2 micron, 01:14:42.860 --> 01:14:46.130 or 2x, or 3x spacing between the devices. 01:14:46.130 --> 01:14:49.610 But in this case, the variation across many, many replicates 01:14:49.610 --> 01:14:52.700 of each of those is about the same. 01:14:52.700 --> 01:14:54.500 An interesting effect is, if we take 01:14:54.500 --> 01:14:58.940 that same [INAUDIBLE] that single gate electrode and split 01:14:58.940 --> 01:15:02.690 it up into two, or split it up into three, 01:15:02.690 --> 01:15:05.990 and then look at the effect on ring oscillator speed 01:15:05.990 --> 01:15:11.450 offset and variance, what do you think we're going to see? 01:15:11.450 --> 01:15:13.220 We didn't know, so you may not know. 01:15:15.520 --> 01:15:16.020 Yeah? 01:15:16.020 --> 01:15:19.805 AUDIENCE: Probably see four variations 01:15:19.805 --> 01:15:23.792 in the [INAUDIBLE] one because there are more edges. 01:15:23.792 --> 01:15:25.500 DUANE BONING: Right, you have more edges. 01:15:25.500 --> 01:15:26.660 And that's exactly. 01:15:26.660 --> 01:15:31.250 If we look at the sigma with one finger, two finger, or four 01:15:31.250 --> 01:15:36.740 finger, we found a proportional increase in the variance, 01:15:36.740 --> 01:15:41.090 with more opportunities for variation by the fingering. 01:15:41.090 --> 01:15:46.040 So that was an interesting implication for some design 01:15:46.040 --> 01:15:49.070 kinds of effects. 01:15:49.070 --> 01:15:53.000 OK, so that's an example where design of experiments 01:15:53.000 --> 01:15:55.010 could be used to come up with test structures, 01:15:55.010 --> 01:15:56.810 and characterize, and split out some 01:15:56.810 --> 01:15:59.190 of these sources of variation. 01:15:59.190 --> 01:16:02.620 Now, I'm not going to go into the full detail 01:16:02.620 --> 01:16:03.650 on these slides. 01:16:03.650 --> 01:16:06.070 I put more slides in here than I needed 01:16:06.070 --> 01:16:08.320 because this is a current area of my research 01:16:08.320 --> 01:16:09.770 and I get really excited about it. 01:16:09.770 --> 01:16:11.770 But it helps explain a little bit 01:16:11.770 --> 01:16:15.520 this multilevel interconnect. 01:16:15.520 --> 01:16:18.520 I'll cover the first one very briefly. 01:16:18.520 --> 01:16:20.560 There's two sequences that I didn't 01:16:20.560 --> 01:16:24.400 talked about in the earlier flow, because it's 01:16:24.400 --> 01:16:25.990 a 10-year-old process. 01:16:25.990 --> 01:16:29.380 Modern integrated circuits-- especially 01:16:29.380 --> 01:16:31.930 for microprocessor logic, and now even memory-- 01:16:31.930 --> 01:16:34.000 are using copper interconnect. 01:16:34.000 --> 01:16:37.390 Copper conducts better than aluminum. 01:16:37.390 --> 01:16:39.430 You get speed improvements. 01:16:39.430 --> 01:16:41.480 You get reliability improvements. 01:16:41.480 --> 01:16:43.360 It's a big drive to move to copper. 01:16:43.360 --> 01:16:46.220 But it's a little bit more complicated of a process. 01:16:46.220 --> 01:16:51.310 The basic process is different than an aluminum, 01:16:51.310 --> 01:16:54.880 because we do not have an effective plasma etch 01:16:54.880 --> 01:16:56.650 process for the removal-- 01:16:56.650 --> 01:16:58.990 selective removal of copper. 01:16:58.990 --> 01:17:01.640 It's just a bad process in that way. 01:17:01.640 --> 01:17:06.040 So instead, what we have to do is go through the following 01:17:06.040 --> 01:17:06.700 sequence. 01:17:06.700 --> 01:17:11.110 We go to photolithographically etch in our insulating layer 01:17:11.110 --> 01:17:15.880 where we want, ultimately, the copper line to reside. 01:17:15.880 --> 01:17:19.480 Then we fill in copper everywhere. 01:17:19.480 --> 01:17:23.270 We happen to do that using an electroplating process, 01:17:23.270 --> 01:17:25.940 and that electroplating process results 01:17:25.940 --> 01:17:29.720 in nice filling of features of different sizes, 01:17:29.720 --> 01:17:31.460 but it also overfills. 01:17:31.460 --> 01:17:35.000 And even more problematic is it overfills to different amounts 01:17:35.000 --> 01:17:38.570 or different thicknesses depending on the feature size 01:17:38.570 --> 01:17:39.860 that we filled up. 01:17:39.860 --> 01:17:42.470 So you get this very complicated topography. 01:17:42.470 --> 01:17:45.920 Now, I described CMP as wonderful for flattening 01:17:45.920 --> 01:17:48.330 and removing and abrading away topography. 01:17:48.330 --> 01:17:52.430 So the second step is using CMP to remove 01:17:52.430 --> 01:17:54.890 all this excess copper. 01:17:54.890 --> 01:17:57.290 And it will polish away. 01:17:57.290 --> 01:18:00.380 And ideally, you would like to stop exactly 01:18:00.380 --> 01:18:04.040 on the surface of the oxide and have your nice remaining copper 01:18:04.040 --> 01:18:06.530 lines where you wanted them. 01:18:06.530 --> 01:18:11.240 But it also has a geometric imperfection arising from 01:18:11.240 --> 01:18:15.800 over-polish, where big fat wide lines-- 01:18:15.800 --> 01:18:18.950 the polishing pad-- that polyurethane pad-- actually 01:18:18.950 --> 01:18:23.120 digs down in and over-polishes certain features. 01:18:23.120 --> 01:18:25.440 And in regions where you've got a lot of copper 01:18:25.440 --> 01:18:27.950 and very little hard supporting oxide, 01:18:27.950 --> 01:18:31.990 it actually erodes down in appreciably. 01:18:31.990 --> 01:18:34.090 So these are some systematic effects. 01:18:34.090 --> 01:18:36.250 They are manufacturing limitations, 01:18:36.250 --> 01:18:39.890 and one would like to model and characterize those. 01:18:39.890 --> 01:18:42.250 And in fact, that's what this waiver was for. 01:18:42.250 --> 01:18:46.570 What we came up with was a test structure methodology where 01:18:46.570 --> 01:18:50.680 you would put lots of features of different sizes on a wafer, 01:18:50.680 --> 01:18:55.160 run it through the process, measure the results-- 01:18:55.160 --> 01:18:59.290 so this is a measurement of the electroplated profile 01:18:59.290 --> 01:19:02.320 for different feature sizes, like those little lines 01:19:02.320 --> 01:19:06.310 and spaces between the lines of quarter micron, quarter micron, 01:19:06.310 --> 01:19:09.910 versus say 100 micron and 100 micron lines. 01:19:09.910 --> 01:19:13.090 And then you could measure the surface topography 01:19:13.090 --> 01:19:17.890 and see how much overinflating or how much underfill you might 01:19:17.890 --> 01:19:21.290 have in each of those regions. 01:19:21.290 --> 01:19:24.200 Now, this is kind of a neat example for something 01:19:24.200 --> 01:19:27.290 that we'll be learning about later in the term, which 01:19:27.290 --> 01:19:29.570 is empirical modeling. 01:19:29.570 --> 01:19:33.650 This is an empirical process, where we run the wafer through, 01:19:33.650 --> 01:19:36.230 we take measurements, and then we developed 01:19:36.230 --> 01:19:39.620 in our first-level model response 01:19:39.620 --> 01:19:42.710 surface models that are basically 01:19:42.710 --> 01:19:47.580 power models as a function of line width and line space. 01:19:47.580 --> 01:19:50.570 So you can empirically fit a model 01:19:50.570 --> 01:19:53.840 that describes how much overplating height 01:19:53.840 --> 01:19:56.420 or what the step height might be. 01:19:56.420 --> 01:20:01.130 And then one can use that to characterize step height 01:20:01.130 --> 01:20:04.640 or the amount of bulge as a function of line width and line 01:20:04.640 --> 01:20:07.760 space, and give some feedback to the designers 01:20:07.760 --> 01:20:11.340 saying, hey, if you design in these ranges. 01:20:11.340 --> 01:20:13.460 This is what's actually going to happen, 01:20:13.460 --> 01:20:16.320 as opposed to what you thought was going to happen. 01:20:16.320 --> 01:20:19.820 And so that's a little response-- surface model 01:20:19.820 --> 01:20:20.930 kind of example. 01:20:20.930 --> 01:20:22.910 And then one can also build those perhaps 01:20:22.910 --> 01:20:27.410 into design tools that could predict for a whole chip-- 01:20:27.410 --> 01:20:28.910 maybe a product chip-- 01:20:28.910 --> 01:20:33.500 what the electroplated process thickness would be 01:20:33.500 --> 01:20:36.050 or what the CMP process would be. 01:20:36.050 --> 01:20:37.070 I'm going to skip these. 01:20:37.070 --> 01:20:40.280 This is essentially doing the same thing for CMP, 01:20:40.280 --> 01:20:44.240 but the idea here is this linkage, again, between design 01:20:44.240 --> 01:20:49.640 and manufacture, where the manufacturing fab can 01:20:49.640 --> 01:20:53.540 characterize what the actual amount of dishing or erosion 01:20:53.540 --> 01:20:57.200 is going to be for very complicated product chips. 01:20:57.200 --> 01:21:01.550 And that information could get fed back to the designer 01:21:01.550 --> 01:21:05.180 so that they actually know, in this location, 01:21:05.180 --> 01:21:11.665 my final copper wire is going to be this thick, not this thick. 01:21:11.665 --> 01:21:13.040 And that could be very important, 01:21:13.040 --> 01:21:16.220 because the thickness of a copper wire 01:21:16.220 --> 01:21:21.250 determines its electrical resistance. 01:21:21.250 --> 01:21:24.220 It even affects the coupling capacitance 01:21:24.220 --> 01:21:25.570 between to neighbor wires. 01:21:25.570 --> 01:21:28.030 So those key electrical parameters-- 01:21:28.030 --> 01:21:32.140 resistance, capacitance-- that determine interconnect speed 01:21:32.140 --> 01:21:36.310 depend on that critically. 01:21:36.310 --> 01:21:41.710 So that linkage with robust design can be very important. 01:21:41.710 --> 01:21:43.480 One can also use those kinds of models 01:21:43.480 --> 01:21:47.020 to play with process parameters, and empirically, 01:21:47.020 --> 01:21:49.270 as a function of the process conditions, 01:21:49.270 --> 01:21:53.110 minimize these systematic sources of variation. 01:21:53.110 --> 01:21:57.490 And one approach that is dominant in a number 01:21:57.490 --> 01:22:02.650 of industries is a capturing of these dependencies on design 01:22:02.650 --> 01:22:05.320 features, like line width or line space, 01:22:05.320 --> 01:22:08.530 and what is a good region to be operating 01:22:08.530 --> 01:22:12.010 in in these ideas of design rules. 01:22:12.010 --> 01:22:13.510 And so in fact, this is some work 01:22:13.510 --> 01:22:18.010 from LSI Logic looking at the copper interconnect space 01:22:18.010 --> 01:22:22.450 and saying, OK, what region, what limits, 01:22:22.450 --> 01:22:26.410 what combinations of line width and line space can you have, 01:22:26.410 --> 01:22:28.510 and where are the boundaries because 01:22:28.510 --> 01:22:30.830 of some of these different physical effects? 01:22:30.830 --> 01:22:32.920 So for example, photolithography says 01:22:32.920 --> 01:22:37.180 I can't patent smaller than certain dimensions. 01:22:37.180 --> 01:22:39.890 Dishing limits, that dishing down into wide features, 01:22:39.890 --> 01:22:42.970 says I can't have features wider than 10 microns. 01:22:42.970 --> 01:22:44.690 I'll dish them too much. 01:22:44.690 --> 01:22:46.450 So this is another way of coupling 01:22:46.450 --> 01:22:49.370 between design and manufacture. 01:22:49.370 --> 01:22:51.200 And then the last thing I've already 01:22:51.200 --> 01:22:55.850 alluded to, but coming back to the CMP problem, 01:22:55.850 --> 01:22:57.070 we also can develop-- 01:22:57.070 --> 01:23:02.050 and we'll talk about response surface or empirical models 01:23:02.050 --> 01:23:06.250 that say, OK, here's what the removal rate is, 01:23:06.250 --> 01:23:10.480 or the non-uniformity is as a function of some of the process 01:23:10.480 --> 01:23:13.180 conditions, like the speed of rotation, 01:23:13.180 --> 01:23:16.390 or the pressure or downforce of rotation. 01:23:16.390 --> 01:23:20.300 And once you have a basic control model-- 01:23:20.300 --> 01:23:22.610 for example, the normalized removal rate 01:23:22.610 --> 01:23:25.160 is a function of downforce and speed-- 01:23:25.160 --> 01:23:28.940 I've got some input-output empirical relationship between 01:23:28.940 --> 01:23:29.660 these-- 01:23:29.660 --> 01:23:35.270 I can now use this in a run-by-run control kind 01:23:35.270 --> 01:23:39.050 of feedback situation, where I make a measurement on every 01:23:39.050 --> 01:23:40.520 wafer that comes out-- 01:23:40.520 --> 01:23:43.070 what the average removal rate was-- 01:23:43.070 --> 01:23:46.310 use that together with this empirical model, 01:23:46.310 --> 01:23:50.030 perhaps do a model update to track the changing state 01:23:50.030 --> 01:23:54.290 of the equipment and pad as-- it also gets perturb from run 01:23:54.290 --> 01:23:55.160 to run-- 01:23:55.160 --> 01:23:58.400 use that do model to say, for the next wafer, 01:23:58.400 --> 01:24:00.560 change the recipe slightly. 01:24:00.560 --> 01:24:02.870 Polish a little bit longer or press a little bit 01:24:02.870 --> 01:24:06.680 harder to compensate for that known 01:24:06.680 --> 01:24:09.540 characterized variation source. 01:24:09.540 --> 01:24:11.250 And so this is just an example. 01:24:11.250 --> 01:24:14.690 You can imagine that, using these simplified models, 01:24:14.690 --> 01:24:17.660 one can have some compensation strategy that 01:24:17.660 --> 01:24:20.990 brings the removal rate back up to target. 01:24:20.990 --> 01:24:23.900 And so we'll talk about that in the latter part of the term 01:24:23.900 --> 01:24:24.720 as well. 01:24:24.720 --> 01:24:27.770 These are just examples showing, for different numbers 01:24:27.770 --> 01:24:29.960 of wafers, you have to actually change 01:24:29.960 --> 01:24:33.440 the speed or the pressure, downforce, 01:24:33.440 --> 01:24:36.870 but you can get very good control of the output. 01:24:36.870 --> 01:24:40.790 So to wrap up for today, this was a whirlwind tour 01:24:40.790 --> 01:24:43.290 through the semiconductor fabrication process, 01:24:43.290 --> 01:24:46.340 and I hope you have a feel for the myriad different kinds 01:24:46.340 --> 01:24:50.060 of variations that are out there, and a glimpse forward 01:24:50.060 --> 01:24:51.840 to some of the techniques that we're 01:24:51.840 --> 01:24:55.670 going to be developing through the term to deal with this. 01:24:55.670 --> 01:24:59.060 So we'll see you on Tuesday. 01:24:59.060 --> 01:25:02.870 Dave will be giving that lecture and talking 01:25:02.870 --> 01:25:05.360 about the rest of the processes out there 01:25:05.360 --> 01:25:07.582 in the world besides semiconductor fabrication, 01:25:07.582 --> 01:25:09.290 and building up some intuition that we'll 01:25:09.290 --> 01:25:12.650 use in those processes. 01:25:12.650 --> 01:25:16.450 So get started on the problem set as well.