WEBVTT 00:00:11.000 --> 00:00:14.000 All right. Let's get started. 00:00:14.000 --> 00:00:20.000 I guess this watch is a couple minutes fast. 00:00:20.000 --> 00:00:27.000 First a quick announcement. In case you have forgotten, 00:00:27.000 --> 00:00:34.000 your lab notebooks are due tomorrow with the post-lab 00:00:34.000 --> 00:00:41.000 exercises for the first lab. OK, so I am going to continue 00:00:41.000 --> 00:00:45.000 with amplifiers today. And to just give you a sense of 00:00:45.000 --> 00:00:49.000 where we headed, we have this five lecture 00:00:49.000 --> 00:00:53.000 sequence covering different aspects of amplifiers with 00:00:53.000 --> 00:00:59.000 dependent sources and showed how we could build an amplifier with 00:00:59.000 --> 00:01:04.000 it on Tuesday. Today I am going to show you a 00:01:04.000 --> 00:01:08.000 real device that implements a dependent source. 00:01:08.000 --> 00:01:14.000 And then next Tuesday we will talk about analysis of an 00:01:14.000 --> 00:01:17.000 amplifier. Wednesday is our quiz. 00:01:17.000 --> 00:01:23.000 Thursday and the Tuesday after that we then talk about small 00:01:23.000 --> 00:01:30.000 signal analysis and small signal use of the amplifier. 00:01:30.000 --> 00:01:39.000 Today we will talk about the MOSFET amplifier. 00:01:46.000 --> 00:01:49.000 So let's start with a quick review. 00:01:49.000 --> 00:01:54.000 And in the last lecture, I showed you that I could build 00:01:54.000 --> 00:01:59.000 a amplifier using a dependent source. 00:02:05.000 --> 00:02:09.000 And a dependent source worked as follows. 00:02:09.000 --> 00:02:16.000 Let's say I had a circuit and I connected a dependent source 00:02:16.000 --> 00:02:21.000 into the circuit. Let's say in this example I 00:02:21.000 --> 00:02:28.000 have a current source. So this is some circuit. 00:02:28.000 --> 00:02:33.000 And the current i is a function of some parameter in the 00:02:33.000 --> 00:02:36.000 circuit. That's why this is a dependent 00:02:36.000 --> 00:02:40.000 source. This is a dependent current 00:02:40.000 --> 00:02:43.000 source. So it could be that I have some 00:02:43.000 --> 00:02:46.000 element inside. And I measure, 00:02:46.000 --> 00:02:51.000 I sample the voltage across the element or between any two 00:02:51.000 --> 00:02:56.000 points in the circuit. And, in this little example 00:02:56.000 --> 00:03:03.000 here, this current could be dependent on that voltage. 00:03:03.000 --> 00:03:07.000 So notice that although I showed you the two terminals of 00:03:07.000 --> 00:03:10.000 the dependent source that carried a current, 00:03:10.000 --> 00:03:15.000 there is another implicit port, another implicit terminal 00:03:15.000 --> 00:03:17.000 there. And that terminal there is 00:03:17.000 --> 00:03:22.000 called the "control port" of the dependent source at which I 00:03:22.000 --> 00:03:26.000 apply a voltage or current that will control the value of the 00:03:26.000 --> 00:03:31.000 current source. As a quick aside. 00:03:38.000 --> 00:03:42.000 There is a small glitch with the tools in your tool chest. 00:03:42.000 --> 00:03:46.000 We talked about the superposition technique where 00:03:46.000 --> 00:03:50.000 you were taught to turn on one source at a time, 00:03:50.000 --> 00:03:56.000 for a linear circuit one source at a time, and then sum up the 00:03:56.000 --> 00:04:01.000 responses to all the sources acting one at a time. 00:04:01.000 --> 00:04:04.000 Well, what do you do about dependent sources? 00:04:04.000 --> 00:04:09.000 A dependent source is a source. And we have to modify the 00:04:09.000 --> 00:04:12.000 superposition statement just a little bit. 00:04:12.000 --> 00:04:17.000 And for details you can look at Section 3.5.1 of your course 00:04:17.000 --> 00:04:21.000 notes on the details and some examples on how to do this. 00:04:21.000 --> 00:04:24.000 So the approach is very simple, actually. 00:04:24.000 --> 00:04:27.000 The approach is, for the purpose of 00:04:27.000 --> 00:04:30.000 superposition, to not treat your dependent 00:04:30.000 --> 00:04:36.000 source as sources that you turn on and turn off. 00:04:36.000 --> 00:04:39.000 So what you do is when you do superposition with dependent 00:04:39.000 --> 00:04:43.000 sources simply leave all your dependent sources in the 00:04:43.000 --> 00:04:46.000 circuit. Just leave them in there and 00:04:46.000 --> 00:04:49.000 turn on and off only your independent sources. 00:04:49.000 --> 00:04:52.000 So look at the response of the circuit by turning on your 00:04:52.000 --> 00:04:56.000 independent sources one at a time and summing up the 00:04:56.000 --> 00:05:00.000 responses. And your dependent sources stay 00:05:00.000 --> 00:05:05.000 within the circuit and simply analyze them as you do anything 00:05:05.000 --> 00:05:07.000 else. So essentially what it says is 00:05:07.000 --> 00:05:12.000 that just be a little cautious when you have dependent sources, 00:05:12.000 --> 00:05:16.000 but the basic method applies almost without any change. 00:05:16.000 --> 00:05:22.000 The readings for today's lecture are Section 7.3 to 7.6. 00:05:27.000 --> 00:05:32.000 So since we are going to build up on the dependent source 00:05:32.000 --> 00:05:39.000 amplifier, let me start with a quick review of that amplifier. 00:05:39.000 --> 00:05:43.000 We built our amplifier as follows. 00:05:54.000 --> 00:05:58.000 We connected our dependent source in the following manner. 00:05:58.000 --> 00:06:02.000 And the current through the dependent source in the example 00:06:02.000 --> 00:06:06.000 we took was related to an input voltage vI. 00:06:12.000 --> 00:06:16.000 So some voltage vI. And so these two were the 00:06:16.000 --> 00:06:21.000 control port of the dependent source and a vI was applied 00:06:21.000 --> 00:06:24.000 there. And I showed you a simple 00:06:24.000 --> 00:06:30.000 amplifier built with a dependent source that behaved in this 00:06:30.000 --> 00:06:34.000 manner. And again I will keep reminding 00:06:34.000 --> 00:06:38.000 you, just remember that the dependent source is actually 00:06:38.000 --> 00:06:41.000 this box here, the control port and the output 00:06:41.000 --> 00:06:43.000 port. And commonly we don't 00:06:43.000 --> 00:06:48.000 explicitly show the control port for those dependent sources for 00:06:48.000 --> 00:06:52.000 which the control port does not have any other affect on the 00:06:52.000 --> 00:06:58.000 circuit, like it doesn't draw any current or things like that. 00:06:58.000 --> 00:07:04.000 So in this particular example we said that this behaved in the 00:07:04.000 --> 00:07:11.000 following manner for vI greater than or equal to 1 volt and iD 00:07:11.000 --> 00:07:14.000 was zero otherwise. 00:07:19.000 --> 00:07:26.000 So we can analyze the circuit to figure out what vO is going 00:07:26.000 --> 00:07:31.000 to look like. And a simple application of KVL 00:07:31.000 --> 00:07:33.000 at this loop here, again, you know, 00:07:33.000 --> 00:07:37.000 when I say this loop here, I am pointing at something 00:07:37.000 --> 00:07:40.000 here. That is the VS source that is 00:07:40.000 --> 00:07:42.000 implicitly across these two nodes. 00:07:42.000 --> 00:07:46.000 Again, this is a shorthand notation where this little up 00:07:46.000 --> 00:07:51.000 arrow here implies that I have a voltage source connected between 00:07:51.000 --> 00:07:55.000 these two terminals here. And so there is a loop here 00:07:55.000 --> 00:08:00.000 that involves VS. So Vo is simply VS minus the 00:08:00.000 --> 00:08:05.000 drop across this resistor. So it's VS minus the drop 00:08:05.000 --> 00:08:08.000 across this resistor gives me vO. 00:08:08.000 --> 00:08:13.000 And the drop across the resistor is simply iD RL. 00:08:13.000 --> 00:08:17.000 iD is the current here and that's the drop across the 00:08:17.000 --> 00:08:21.000 resistor. And I could get the explicit 00:08:21.000 --> 00:08:27.000 relationship of vO versus vI by substituting for iD as vI minus 00:08:27.000 --> 00:08:32.000 one all squared. So vO relates to vI in the 00:08:32.000 --> 00:08:35.000 following manner. Nothing new so far. 00:08:35.000 --> 00:08:41.000 I have pretty much reviewed what we did the last time. 00:08:41.000 --> 00:08:46.000 Here is where we take our next step forward with some new 00:08:46.000 --> 00:08:50.000 material. Up to now I have talked as a 00:08:50.000 --> 00:08:55.000 theoretician would where I said just imagine that you had 00:08:55.000 --> 00:09:00.000 spherical cow or something like that. 00:09:00.000 --> 00:09:03.000 Here I just asked you to imagine this ideal dependent 00:09:03.000 --> 00:09:07.000 source, control port and an output port, and it behaved in 00:09:07.000 --> 00:09:10.000 this manner. So as a next step what I would 00:09:10.000 --> 00:09:14.000 like to do is show you a practical dependent source which 00:09:14.000 --> 00:09:17.000 turns out to be a little bit more complicated than this 00:09:17.000 --> 00:09:22.000 idealized dependent source that I showed you in many dimensions. 00:09:22.000 --> 00:09:25.000 Real life tends to impose a bunch of practical constraints 00:09:25.000 --> 00:09:30.000 on you, and we will look at those in a second. 00:09:30.000 --> 00:09:37.000 If I could find a dependent source that looked like this -- 00:09:52.000 --> 00:10:00.000 We had a control port A prime and output port B prime. 00:10:00.000 --> 00:10:05.000 And I looked at some examples where the current through the 00:10:05.000 --> 00:10:10.000 dependent current source was some function of the input 00:10:10.000 --> 00:10:13.000 voltage. This is a "voltage controlled 00:10:13.000 --> 00:10:17.000 current source". What I am going to do is talk 00:10:17.000 --> 00:10:22.000 about a device that can give me this behavior or some close 00:10:22.000 --> 00:10:27.000 approximation to it. It turns out that under certain 00:10:27.000 --> 00:10:32.000 conditions the MOSFET that you have already looked at behaves 00:10:32.000 --> 00:10:38.000 in this manner. The MOSFET that you've seen 00:10:38.000 --> 00:10:44.000 sort of behaves like this. And let me show you under what 00:10:44.000 --> 00:10:49.000 conditions the MOSFET behaves in that manner. 00:10:49.000 --> 00:10:52.000 Let me create some room for myself. 00:10:52.000 --> 00:11:00.000 Notice that I need a control port, needed an output port. 00:11:00.000 --> 00:11:04.000 And I am going to view my MOSFET in a slightly different 00:11:04.000 --> 00:11:07.000 manner than you have seen before. 00:11:07.000 --> 00:11:09.000 I draw these two terminals here. 00:11:09.000 --> 00:11:12.000 And this was a three terminal MOSFET. 00:11:12.000 --> 00:11:16.000 This was my drain, my gate and my source terminal. 00:11:16.000 --> 00:11:21.000 It was a three terminal device, but what I do is I view the 00:11:21.000 --> 00:11:25.000 MOSFET slightly differently. I will just use this terminal 00:11:25.000 --> 00:11:31.000 to be common across both the gate and the drain. 00:11:31.000 --> 00:11:34.000 And so this voltage here is vGS. 00:11:34.000 --> 00:11:39.000 I am just using the source port, the source terminal along 00:11:39.000 --> 00:11:42.000 with the gate as a terminal pair. 00:11:42.000 --> 00:11:48.000 I am using the same source along with the drain as another 00:11:48.000 --> 00:11:52.000 terminal pair. So I have a vDS out there and I 00:11:52.000 --> 00:11:58.000 have some current iDS that flows out here. 00:11:58.000 --> 00:12:03.000 Notice that when I view the MOSFET in this manner I have 00:12:03.000 --> 00:12:09.000 accomplished my first step, which is I seem to have a box 00:12:09.000 --> 00:12:13.000 which has a port here and a port here. 00:12:13.000 --> 00:12:18.000 And I also explained to you that a MOSFET behaves in a 00:12:18.000 --> 00:12:22.000 particular manner. For one, the output port 00:12:22.000 --> 00:12:30.000 behaved as an open circuit under certain conditions when -- 00:12:30.000 --> 00:12:33.000 This was vGS, G, drain and source. 00:12:33.000 --> 00:12:39.000 When vGS was less than a threshold voltage VT this MOSFET 00:12:39.000 --> 00:12:44.000 had an equivalent circuit that looked like this. 00:12:44.000 --> 00:12:50.000 So when vGS was less than some threshold voltage VT then there 00:12:50.000 --> 00:12:56.000 was an open circuit between the drain and the source. 00:12:56.000 --> 00:13:02.000 And you saw this before. So far nothing new here. 00:13:02.000 --> 00:13:08.000 However, when vGS is greater than or equal to VT -- 00:13:15.000 --> 00:13:19.000 vGS was greater than VT. The MOSFET behavior we looked 00:13:19.000 --> 00:13:23.000 at earlier showed that this behaved either like a short 00:13:23.000 --> 00:13:29.000 circuit in the simplest form or in a slightly more detailed form 00:13:29.000 --> 00:13:34.000 it behaved like a resistor. We call that the SR model of 00:13:34.000 --> 00:13:37.000 the MOSFET. So when vGS was greater than VT 00:13:37.000 --> 00:13:42.000 we said that a simple way to approximate MOSFET behavior was 00:13:42.000 --> 00:13:46.000 to view this as a resistor connected between the drain and 00:13:46.000 --> 00:13:49.000 the source. That was our SR model use of 00:13:49.000 --> 00:13:52.000 the MOSFET. It turns out that we kind of 00:13:52.000 --> 00:13:55.000 lied. We were sort of looking at the 00:13:55.000 --> 00:14:00.000 MOSFET in a really funny way. And I shone the light on the 00:14:00.000 --> 00:14:03.000 MOSFET in a really, really clever way. 00:14:03.000 --> 00:14:06.000 Well, I shouldn't say clever. A really, really tricky way. 00:14:06.000 --> 00:14:10.000 And tricked you into believing that it was just a resistor. 00:14:10.000 --> 00:14:13.000 And we constrained how you use the MOSFET. 00:14:13.000 --> 00:14:16.000 So that behavior was indeed a resistive behavior. 00:14:16.000 --> 00:14:20.000 But it turns out that in real life the behavior of the MOSFET 00:14:20.000 --> 00:14:23.000 between the drain and the source terminals is much more 00:14:23.000 --> 00:14:26.000 complicated than the limited form in which you saw it. 00:14:26.000 --> 00:14:30.000 So today what I am going to do is take the wraps off the 00:14:30.000 --> 00:14:34.000 complete MOSFET and show you its full behavior in all its gory 00:14:34.000 --> 00:14:38.000 glory. And I will spend a bit of time 00:14:38.000 --> 00:14:44.000 on that to clearly emphasize under what conditions the MOSFET 00:14:44.000 --> 00:14:49.000 behaves like a resistor, as you saw when you did digital 00:14:49.000 --> 00:14:54.000 circuits, or behaves differently in other domains of use. 00:14:54.000 --> 00:15:00.000 Let me pause for a second and leave this space blank here. 00:15:00.000 --> 00:15:02.000 And let's do some investigations. 00:15:09.000 --> 00:15:13.000 Let me leave this here. I won't draw in anything yet. 00:15:13.000 --> 00:15:17.000 You will figure out what it looks like yourselves under 00:15:17.000 --> 00:15:21.000 certain conditions. What I will do next is apply 00:15:21.000 --> 00:15:25.000 some voltages on a MOSFET and observe the current versus vDS 00:15:25.000 --> 00:15:31.000 behavior and plot that on a scope and take a look at it. 00:15:31.000 --> 00:15:33.000 What I am going to do -- 00:15:40.000 --> 00:15:45.000 -- is figure out what iDS looks like for -- 00:15:51.000 --> 00:15:57.000 Remember iG into the gate for 6.002 is always going to be 00:15:57.000 --> 00:16:00.000 zero. In much more detailed analyses 00:16:00.000 --> 00:16:02.000 of the MOSFET, in future courses you may see 00:16:02.000 --> 00:16:07.000 slightly more complex behavior. But as far as we are concerned 00:16:07.000 --> 00:16:09.000 it is an open circuit looking into the gate. 00:16:09.000 --> 00:16:13.000 So I am going to apply a vGS across the MOSFET, 00:16:13.000 --> 00:16:16.000 apply a vDS across the MOSFET and plot iDS versus vDS. 00:16:16.000 --> 00:16:19.000 First let me show you what you already know. 00:16:19.000 --> 00:16:22.000 What you already know -- 00:16:30.000 --> 00:16:33.000 This is vDS. I will just keep doing as much 00:16:33.000 --> 00:16:36.000 as I can of what you already know. 00:16:36.000 --> 00:16:40.000 And then when I do some new stuff I will tell you 00:16:40.000 --> 00:16:43.000 explicitly. You've seen this before. 00:16:43.000 --> 00:16:49.000 The MOSFET behaves like an open circuit when vGS less than VT. 00:16:49.000 --> 00:16:53.000 That is when vG is less than a threshold voltage VT, 00:16:53.000 --> 00:16:59.000 I have zero current flowing through the MOSFET. 00:16:59.000 --> 00:17:03.000 And when vGS was greater than VT then the S model of the 00:17:03.000 --> 00:17:07.000 MOSFET the switch model simply said that look, 00:17:07.000 --> 00:17:10.000 we can model the D2S as a short circuit. 00:17:10.000 --> 00:17:14.000 You saw this in your labs and you saw that it was a very, 00:17:14.000 --> 00:17:19.000 very small resistance between the drain and the source and it 00:17:19.000 --> 00:17:22.000 kind of looked like a short circuit. 00:17:22.000 --> 00:17:25.000 But then we said well, that's not quite it. 00:17:25.000 --> 00:17:32.000 There is some resistance. And so we said a slightly more 00:17:32.000 --> 00:17:38.000 accurate model would have this line droop a little bit to imply 00:17:38.000 --> 00:17:44.000 that there was some resistance R_on between the drain and the 00:17:44.000 --> 00:17:49.000 source, so vDS iDS. So this was when vGS less than 00:17:49.000 --> 00:17:52.000 VT and vGS greater than or equal to VT. 00:17:52.000 --> 00:17:58.000 I have some resistance. And that showed me a straight 00:17:58.000 --> 00:18:05.000 line kind of like behavior. And I showed you that behavior. 00:18:05.000 --> 00:18:13.000 So far absolutely nothing new. Now what I have plotted there 00:18:13.000 --> 00:18:19.000 for you is that behavior. Up here notice that this is the 00:18:19.000 --> 00:18:27.000 vDS axis, this is the iDS axis. I am plotting iDS versus vDS. 00:18:27.000 --> 00:18:32.000 And when vGS -- The gate voltage is more than a 00:18:32.000 --> 00:18:36.000 threshold, notice that I see what looks like something more 00:18:36.000 --> 00:18:40.000 or less like a straight line. And this is a straight line 00:18:40.000 --> 00:18:43.000 with some slope, more or less a straight line 00:18:43.000 --> 00:18:47.000 implying resistive behavior. And we also had some fun and 00:18:47.000 --> 00:18:49.000 games here. We said hey, 00:18:49.000 --> 00:18:51.000 what if I turn vGS off? Boom. 00:18:51.000 --> 00:18:55.000 That would be my iDS of zero implying that the MOSFET behaved 00:18:55.000 --> 00:19:01.000 like an open circuit between the drain and the source. 00:19:01.000 --> 00:19:05.000 I applied a positive vGS more than VT and it began to look 00:19:05.000 --> 00:19:08.000 like a resistor. Open circuit, 00:19:08.000 --> 00:19:10.000 resistor, open circuit, resistor, OK? 00:19:10.000 --> 00:19:15.000 Up until now nothing new. So you shouldn't have learned 00:19:15.000 --> 00:19:19.000 anything at all that is new until now in today's lecture. 00:19:19.000 --> 00:19:22.000 Now watch. What I am going to do is, 00:19:22.000 --> 00:19:27.000 as I said, I kind of lied all this time and I just showed you 00:19:27.000 --> 00:19:32.000 this behavior. And what I have been doing all 00:19:32.000 --> 00:19:36.000 along is very carefully using a very small value of vDS. 00:19:36.000 --> 00:19:39.000 Notice it's a small values of vDS. 00:19:39.000 --> 00:19:43.000 I haven't told you what it looks like as vDS increases. 00:19:43.000 --> 00:19:46.000 Well, let's go try it out. We have a scope here. 00:19:46.000 --> 00:19:50.000 We have the MOSFET here. Now, I am not sure what is 00:19:50.000 --> 00:19:54.000 going to happen now. You may see smoke or have an 00:19:54.000 --> 00:20:00.000 explosion, who knows what? But look up there for a second. 00:20:00.000 --> 00:20:08.000 I am just going to increase vDS and you can figure out what 00:20:08.000 --> 00:20:14.000 happens for yourselves. I increase vDS. 00:20:14.000 --> 00:20:20.000 Whoa, what a liar. Agarwal is a liar. 00:20:20.000 --> 00:20:25.000 I have been kind of tricking you. 00:20:25.000 --> 00:20:33.000 I have been putting -- Covering up all this part here 00:20:33.000 --> 00:20:39.000 and showing you just this region of the curve for small values of 00:20:39.000 --> 00:20:43.000 vDS. But as I increase vDS this is 00:20:43.000 --> 00:20:49.000 nothing that looks even close to that of resistive behavior. 00:20:49.000 --> 00:20:54.000 So what's happening here? What's happening is that as I 00:20:54.000 --> 00:21:01.000 increase my vDS the iDS curve tails off and saturates at some 00:21:01.000 --> 00:21:06.000 value of current. Notice it saturates at some 00:21:06.000 --> 00:21:10.000 value of current. And so I am going to look at 00:21:10.000 --> 00:21:15.000 this region of behavior. Notice that what we have looked 00:21:15.000 --> 00:21:19.000 at so far was the behavior for small vDS. 00:21:19.000 --> 00:21:24.000 It kind of looks resistive. But when I pump up the vDS, 00:21:24.000 --> 00:21:29.000 really whack this node really hard with a much larger vDS the 00:21:29.000 --> 00:21:33.000 guy says, oh, I give up. 00:21:33.000 --> 00:21:38.000 And the current saturates out and flattens out and holds the 00:21:38.000 --> 00:21:43.000 value steady at some value. So what's that behavior look 00:21:43.000 --> 00:21:46.000 like? What is my horizontal line 00:21:46.000 --> 00:21:49.000 above the X axis in terms of V I elements? 00:21:49.000 --> 00:21:53.000 What is that behavior like? Current source, 00:21:53.000 --> 00:21:57.000 exactly. So this is current source like 00:21:57.000 --> 00:22:02.000 behavior. And so let me start by drawing 00:22:02.000 --> 00:22:08.000 you a little model and explaining it in more detail. 00:22:08.000 --> 00:22:14.000 What happens is that under certain conditions, 00:22:14.000 --> 00:22:19.000 and the conditions are the following, when vDS, 00:22:19.000 --> 00:22:26.000 that is my drain to source voltage is greater than or equal 00:22:26.000 --> 00:22:32.000 to vGS minus VT. When my drain voltage goes 00:22:32.000 --> 00:22:36.000 above vGS minus VT, so if vGS is 3 volts and if VT 00:22:36.000 --> 00:22:39.000 is 1 volt, then if vDS goes above 2 volts, 00:22:39.000 --> 00:22:45.000 if I am hammering the drain of the MOSFET with a higher voltage 00:22:45.000 --> 00:22:50.000 then this guy says I give up, can't show you nice restive 00:22:50.000 --> 00:22:54.000 behavior, and the current saturates out and it doesn't 00:22:54.000 --> 00:23:00.000 allow you draw any more current than a maximum value. 00:23:00.000 --> 00:23:02.000 And that's the current source behavior. 00:23:02.000 --> 00:23:04.000 This one behaves like a current source. 00:23:04.000 --> 00:23:09.000 And the current iDS is given by the following expression. 00:23:23.000 --> 00:23:29.000 The current is given by iDS is equal to a constant K divide by 00:23:29.000 --> 00:23:35.000 two times (vGS-VT) all squared. Kind of reminiscent of the 00:23:35.000 --> 00:23:38.000 carefully chosen dependent source example, 00:23:38.000 --> 00:23:44.000 just that this one here is VT. This model, which applies when 00:23:44.000 --> 00:23:48.000 vGS is greater than VT, the MOSFET has to be on and the 00:23:48.000 --> 00:23:54.000 drain to source voltage in the MOSFET must be larger than some 00:23:54.000 --> 00:23:59.000 value, and that value is vGS minus VT then this guy begins to 00:23:59.000 --> 00:24:06.000 behave like a current source. This model of the MOSFET is 00:24:06.000 --> 00:24:11.000 called the "switch current source model". 00:24:17.000 --> 00:24:21.000 So in the region of the MOSFET characteristics where vGS is 00:24:21.000 --> 00:24:25.000 greater than VT and the drain to source voltage is larger than 00:24:25.000 --> 00:24:27.000 vGS minus VT, the MOSFET behaved like a 00:24:27.000 --> 00:24:32.000 current source between its drain and source terminals. 00:24:32.000 --> 00:24:35.000 And in that part we model the MOSFET as a current source. 00:24:35.000 --> 00:24:40.000 And so not surprisingly that part of the model is called the 00:24:40.000 --> 00:24:43.000 SCS model in contrast with the SR model where we had a 00:24:43.000 --> 00:24:45.000 resistor. Again, remember, 00:24:45.000 --> 00:24:48.000 this is not meant to be conflicting. 00:24:48.000 --> 00:24:51.000 It is not like gee, how can the MOSFET look like a 00:24:51.000 --> 00:24:55.000 resistor, and then suddenly what happens it becomes a current 00:24:55.000 --> 00:24:58.000 source. Well, the two regions are 00:24:58.000 --> 00:25:03.000 different. It is not that it is behaving 00:25:03.000 --> 00:25:08.000 as a current source for the same parameters, no. 00:25:08.000 --> 00:25:14.000 When vDS is less than this right-hand side it does behave 00:25:14.000 --> 00:25:18.000 resistive. The SR model applies. 00:25:18.000 --> 00:25:24.000 But increase vDS beyond a point, the current saturates and 00:25:24.000 --> 00:25:30.000 the SCS applies like so. So let's draw. 00:25:30.000 --> 00:25:36.000 The SCS behavior can be drawn here vDS and iDS. 00:25:36.000 --> 00:25:43.000 As I mentioned to you, for small values of vDS, 00:25:43.000 --> 00:25:50.000 let's say I pick some value of vGS, let's say vGS3, 00:25:50.000 --> 00:25:56.000 some value vGS, it is going to look like a 00:25:56.000 --> 00:26:05.000 resistor until vDS becomes equal to vGS3 minus VT. 00:26:05.000 --> 00:26:12.000 And after that it saturates out and begins to look like a 00:26:12.000 --> 00:26:17.000 current source. And this point is where vDS 00:26:17.000 --> 00:26:25.000 becomes equal to vGS minus VT. And this way is when this equal 00:26:25.000 --> 00:26:32.000 sign becomes a greater than sign, vDS becomes larger then I 00:26:32.000 --> 00:26:38.000 move into this part of the curve. 00:26:38.000 --> 00:26:44.000 Similarly, for various other values of vGS it will look like 00:26:44.000 --> 00:26:46.000 this -- 00:26:52.000 --> 00:26:54.000 -- and so on. And it behaved like an open 00:26:54.000 --> 00:26:57.000 circuit as before when vGS less than VT. 00:26:57.000 --> 00:27:01.000 When vGS less than VT it is still behaving like an open 00:27:01.000 --> 00:27:05.000 circuit. And so as I increase my vGS, 00:27:05.000 --> 00:27:10.000 provided I keep my vDS greater than vGS minus VT, 00:27:10.000 --> 00:27:13.000 I get current source like behavior. 00:27:13.000 --> 00:27:17.000 And notice that this is increasing vGS. 00:27:17.000 --> 00:27:22.000 I have purposely drawn these curves at greater distances from 00:27:22.000 --> 00:27:28.000 each other to imply that it is a nonlinear relationship in that 00:27:28.000 --> 00:27:33.000 if I increase vGS by some amount, the increase in vDS is 00:27:33.000 --> 00:27:41.000 related to the square of vGS. It is vGS minus VT all squared. 00:27:41.000 --> 00:27:46.000 So I get a family of curves of that look like this. 00:27:46.000 --> 00:27:52.000 And this is in the region of operation where vDS equals vGS 00:27:52.000 --> 00:27:56.000 minus VT. And this applies in this regime 00:27:56.000 --> 00:28:01.000 where vDS less than vGS minus VT. 00:28:01.000 --> 00:28:06.000 This region of operation is called, as you might expect, 00:28:06.000 --> 00:28:09.000 the "saturation region". 00:28:14.000 --> 00:28:19.000 We say the MOSFET has been hammered, the MOSFET has been 00:28:19.000 --> 00:28:23.000 walloped, the MOSFET is in saturation. 00:28:23.000 --> 00:28:27.000 So the MOSFET is in saturation. This region, 00:28:27.000 --> 00:28:32.000 corresponding to this, is called the triode region. 00:28:37.000 --> 00:28:40.000 This is really very simple. All we are doing is saying that 00:28:40.000 --> 00:28:43.000 when vDS is increased beyond a certain limit, 00:28:43.000 --> 00:28:47.000 given my vGS minus VT, the MOSFET begins to behave 00:28:47.000 --> 00:28:50.000 like a current source. It cannot draw any more 00:28:50.000 --> 00:28:52.000 current. It limits the current to a 00:28:52.000 --> 00:28:54.000 given value like a current source. 00:28:54.000 --> 00:28:58.000 But on the left-hand side of this it behaves in a resistive 00:28:58.000 --> 00:29:01.000 manner. So what I would like to do is 00:29:01.000 --> 00:29:02.000 -- 00:29:08.000 --> 00:29:11.000 What I will do is, we've plotted for you, 00:29:11.000 --> 00:29:14.000 for the MOSFET, all its characteristics in its 00:29:14.000 --> 00:29:20.000 full glory for a whole bunch of values of vGS and a whole bunch 00:29:20.000 --> 00:29:23.000 of values of vDS. And let me stare at those 00:29:23.000 --> 00:29:27.000 curves with you for a few seconds and walk you through 00:29:27.000 --> 00:29:31.000 them. So what do I have here? 00:29:31.000 --> 00:29:35.000 One of these curves corresponds to a given value of vGS. 00:29:35.000 --> 00:29:39.000 This may be vGS equals 2 volts. This is vDS, 00:29:39.000 --> 00:29:43.000 the drain to source voltage, and this is the current. 00:29:43.000 --> 00:29:48.000 So focus on this curve for now. In the beginning I hid the 00:29:48.000 --> 00:29:53.000 right-hand side behavior from you and showed you just the 00:29:53.000 --> 00:29:58.000 resistive behavior out here. When I increase vDS to be much 00:29:58.000 --> 00:30:02.000 larger the curve saturated and I got the saturation region 00:30:02.000 --> 00:30:08.000 operation of the MOSFET. And notice as I increase my 00:30:08.000 --> 00:30:13.000 value of vGS the saturation current also increases according 00:30:13.000 --> 00:30:19.000 to a square law behavior. So these are the entire curves 00:30:19.000 --> 00:30:22.000 of the MOSFET. Finally the truth comes out. 00:30:22.000 --> 00:30:27.000 And notice that when vDS is less than vGS minus VT, 00:30:27.000 --> 00:30:32.000 I have more or less resistive behavior. 00:30:32.000 --> 00:30:38.000 But when vDS is greater than vGS minus VT I get current 00:30:38.000 --> 00:30:43.000 source like behavior. So one question you may ask is 00:30:43.000 --> 00:30:47.000 when do I use one model or the other? 00:30:47.000 --> 00:30:54.000 When do I use the SR model and when do I use the SCS model? 00:30:54.000 --> 00:31:00.000 If you want to do a real detailed analysis then you can 00:31:00.000 --> 00:31:07.000 use the SR model when vDS is less than vGS minus VT. 00:31:07.000 --> 00:31:12.000 And you would use this model when vDS is greater than or 00:31:12.000 --> 00:31:16.000 equal to vGS minus VT. That is simple enough. 00:31:16.000 --> 00:31:21.000 In 6.002, to eliminate confusion we constrain how we 00:31:21.000 --> 00:31:26.000 look at things a little bit more stringently. 00:31:26.000 --> 00:31:31.000 And what we do is that for our entire digital analysis, 00:31:31.000 --> 00:31:38.000 for the entire digital world we focus on the SR model. 00:31:38.000 --> 00:31:41.000 And I will tell you why in a second. 00:31:41.000 --> 00:31:46.000 So for all digital circuits, invertors, look at power of 00:31:46.000 --> 00:31:50.000 invertors, look at delay, a bunch of other things, 00:31:50.000 --> 00:31:54.000 we will be using the SR model in 6.002. 00:31:54.000 --> 00:31:57.000 And I will tell you why in a second. 00:31:57.000 --> 00:32:02.000 And for analog -- That is for amplifier designs 00:32:02.000 --> 00:32:06.000 and situations like that, we will be operating the MOSFET 00:32:06.000 --> 00:32:10.000 in a saturation region. And I will talk about that in a 00:32:10.000 --> 00:32:13.000 second. What I am saying here is that 00:32:13.000 --> 00:32:17.000 in 6.002, when we do analog designs, we are going to 00:32:17.000 --> 00:32:21.000 discipline ourselves to using the MOSFET only in this region. 00:32:21.000 --> 00:32:26.000 We are going to constrain ourselves to play in only this 00:32:26.000 --> 00:32:31.000 region of the playground where vDS is quite large. 00:32:31.000 --> 00:32:33.000 Why? Because I am asking you to. 00:32:33.000 --> 00:32:37.000 I am saying let's play in that part of the playground and keep 00:32:37.000 --> 00:32:40.000 your vDS high. And so the MOSFET is going to 00:32:40.000 --> 00:32:45.000 be operating somewhere in here. So we can apply just the SCS 00:32:45.000 --> 00:32:49.000 model, just the current source behavior in that region. 00:32:49.000 --> 00:32:53.000 There is another important reason, which I will get to in a 00:32:53.000 --> 00:32:56.000 second. And for digital designs we will 00:32:56.000 --> 00:33:01.000 simply use the SR model. And it turns out that this is 00:33:01.000 --> 00:33:06.000 realistic because in the digital designs that you have you seen 00:33:06.000 --> 00:33:10.000 and will be seeing in this course, the pull down MOSFET is 00:33:10.000 --> 00:33:13.000 on, or when these pull down MOSFETs are on, 00:33:13.000 --> 00:33:17.000 the output voltage is pulled down close to ground. 00:33:17.000 --> 00:33:19.000 So vDS is very, very small. 00:33:19.000 --> 00:33:22.000 So it does make sense that this model apply. 00:33:22.000 --> 00:33:27.000 And when we talk about amplifiers, I am asking you to 00:33:27.000 --> 00:33:31.000 follow this discipline. I will tell you why in a 00:33:31.000 --> 00:33:33.000 second. I am saying analog designs 00:33:33.000 --> 00:33:37.000 follow this discipline that I call the saturation discipline. 00:33:37.000 --> 00:33:41.000 It says simply operate the MOSFET operating in saturation 00:33:41.000 --> 00:33:44.000 as a current source. We will look at an amplifier in 00:33:44.000 --> 00:33:47.000 a second, and I will tell you why. 00:33:54.000 --> 00:34:01.000 Now let's do a MOSFET amplifier. 00:34:01.000 --> 00:34:06.000 Remember my amplifier had an input port and an output port. 00:34:06.000 --> 00:34:12.000 And in general in our use we are going to have a common 00:34:12.000 --> 00:34:15.000 ground. And we have a VS and a ground 00:34:15.000 --> 00:34:19.000 here as well. That is the power port of the 00:34:19.000 --> 00:34:23.000 amplifier. The input port and the output 00:34:23.000 --> 00:34:25.000 port. 00:34:30.000 --> 00:34:39.000 And let me redraw the circuit putting a MOSFET in place of the 00:34:39.000 --> 00:34:44.000 current source, RL, VS, vO, drain, 00:34:44.000 --> 00:34:47.000 gate, source, vI. 00:34:47.000 --> 00:34:54.000 So my input is vI. Again, the MOSFET output is vO. 00:34:54.000 --> 00:35:02.000 And I have a resistor RL. Hey, we've seen that before. 00:35:02.000 --> 00:35:05.000 It turns out this is not surprising. 00:35:05.000 --> 00:35:09.000 You've seen this before. This was our primitive inverter 00:35:09.000 --> 00:35:12.000 circuit. So what's different here? 00:35:12.000 --> 00:35:15.000 We showed you the circuit as an inverter. 00:35:15.000 --> 00:35:20.000 What's different here is that when we look at MOSFET behavior 00:35:20.000 --> 00:35:24.000 as a current source, this behaves like an amplifier. 00:35:24.000 --> 00:35:28.000 In other words, when vDS is greater than some 00:35:28.000 --> 00:35:33.000 value then this behaves like a current source. 00:35:33.000 --> 00:35:35.000 When vDS is small, in other words, 00:35:35.000 --> 00:35:38.000 in the digital design when vDS was small here, 00:35:38.000 --> 00:35:43.000 because when the MOSFET was on it pulled the voltage down to 00:35:43.000 --> 00:35:46.000 ground, we could view this behavior as a resistor. 00:35:46.000 --> 00:35:50.000 And exactly the same thing, it is an amplifier. 00:35:50.000 --> 00:35:54.000 And with digital designs, I was driving it with 5 volts 00:35:54.000 --> 00:35:58.000 and 0 volts and that was it, rail to rail. 00:35:58.000 --> 00:36:01.000 As an amplifier, what I am doing now is looking 00:36:01.000 --> 00:36:05.000 at a small region of its behavior when vDS is greater 00:36:05.000 --> 00:36:08.000 than vGS minus VT. What I am saying is that for 00:36:08.000 --> 00:36:12.000 amplification let's follow the saturation discipline. 00:36:12.000 --> 00:36:16.000 And the reason is that when this behaves like a current 00:36:16.000 --> 00:36:20.000 source, what I have shown you is that if this behaves like a 00:36:20.000 --> 00:36:25.000 current source I have shown you that this expression up here 00:36:25.000 --> 00:36:30.000 gives you amplification. In last lecture we plotted a 00:36:30.000 --> 00:36:34.000 bunch of values for vO versus vI, and we saw that we were 00:36:34.000 --> 00:36:37.000 getting amplification. For a small change in vI, 00:36:37.000 --> 00:36:41.000 I was getting a larger change in vO, and that was when I had 00:36:41.000 --> 00:36:44.000 the equation for a current source in there. 00:36:44.000 --> 00:36:49.000 And so we know for a fact that if I can operate this as a 00:36:49.000 --> 00:36:52.000 current source, with a reasonable choice of 00:36:52.000 --> 00:36:56.000 values here, I am going to be able to get amplification. 00:36:56.000 --> 00:37:00.000 What I haven't told you is if this is operated in the linear 00:37:00.000 --> 00:37:05.000 region, in fact, you do not get amplification. 00:37:05.000 --> 00:37:09.000 I won't cover that, but you can check that out in 00:37:09.000 --> 00:37:13.000 your course notes as a discussion or you can try it out 00:37:13.000 --> 00:37:17.000 for yourself. Replace this with the SR model 00:37:17.000 --> 00:37:22.000 for small vDS and you can show yourselves that you don't get 00:37:22.000 --> 00:37:25.000 any amplification. In order to get the 00:37:25.000 --> 00:37:30.000 amplification we are telling ourselves let's focus on this 00:37:30.000 --> 00:37:36.000 part of the playground where vDS is greater than or equal to vGS 00:37:36.000 --> 00:37:40.000 minus VT. And for vGS greater than or 00:37:40.000 --> 00:37:44.000 equal to VT. So when vGS is greater than VT 00:37:44.000 --> 00:37:48.000 the MOSFET is on. Further, when vDS is large, 00:37:48.000 --> 00:37:53.000 larger than vGS minus VT this behaves like a current source. 00:37:53.000 --> 00:37:58.000 So we have now created a small playground for ourselves where 00:37:58.000 --> 00:38:05.000 we can build lots of fun little amplifiers and other circuits. 00:38:05.000 --> 00:38:09.000 And provided our circuits follow the saturation discipline 00:38:09.000 --> 00:38:13.000 where for the MOSFET or MOSFETs in the circuit these expressions 00:38:13.000 --> 00:38:17.000 are true then the MOSFETs are going to be in saturation, 00:38:17.000 --> 00:38:21.000 the current source model applies, and I will be indeed 00:38:21.000 --> 00:38:25.000 getting saturation. In future courses you may 00:38:25.000 --> 00:38:29.000 actually see the MOSFET used in other regimes of operation for a 00:38:29.000 --> 00:38:34.000 variety of reasons. But in 6.002 when we talk about 00:38:34.000 --> 00:38:38.000 amplifiers and so on we will be adopting the saturation 00:38:38.000 --> 00:38:41.000 discipline. And your homework problems and 00:38:41.000 --> 00:38:45.000 so on will state that. Assume that the MOSFETs are in 00:38:45.000 --> 00:38:48.000 saturation. What that means is that you can 00:38:48.000 --> 00:38:52.000 begin to model them as a current source and simply analyze their 00:38:52.000 --> 00:38:55.000 behavior accordingly. One minor nit. 00:38:55.000 --> 00:39:00.000 Note that vDS for the MOSFET is the same as vO. 00:39:00.000 --> 00:39:04.000 And vGS for the MOSFET is the same as vI. 00:39:04.000 --> 00:39:10.000 So if you see me jumping back and forth using vOs and vIs or 00:39:10.000 --> 00:39:15.000 vDSs and vGSs they are the same thing in this circuit. 00:39:15.000 --> 00:39:21.000 If you are dealing with circuits with many MOSFETs then 00:39:21.000 --> 00:39:28.000 you will have vDS1s and vGS1s and so on and so forth. 00:39:28.000 --> 00:39:34.000 But for this simple circuit, vO and vDS are the same, 00:39:34.000 --> 00:39:41.000 vI and vGS are the same. So we could go ahead and 00:39:41.000 --> 00:39:47.000 analyze that circuit. What I do to analyze the 00:39:47.000 --> 00:39:54.000 circuit, I am telling you this. I am telling you that the 00:39:54.000 --> 00:40:00.000 MOSFET is behaving in saturation. 00:40:00.000 --> 00:40:03.000 I am telling you this. We have disciplined ourselves 00:40:03.000 --> 00:40:07.000 to say that in that circuit the MOSFET is in saturation. 00:40:07.000 --> 00:40:11.000 As soon as we tell you that we can then go ahead and analyze 00:40:11.000 --> 00:40:13.000 that circuit. And to analyze that circuit 00:40:13.000 --> 00:40:17.000 what you will do is simply replace the MOSFET with its 00:40:17.000 --> 00:40:20.000 equivalent model, and that looks like this. 00:40:20.000 --> 00:40:23.000 Since you have been told that it is in saturation, 00:40:23.000 --> 00:40:28.000 we can replace the MOSFET with its current source model. 00:40:36.000 --> 00:40:45.000 And the current iDS for the MOSFET is given by K/2(vI-VT)^2. 00:40:45.000 --> 00:40:54.000 And it is always good to write the constraints under which you 00:40:54.000 --> 00:41:02.000 are implicitly working close by. So the constraints are one, 00:41:02.000 --> 00:41:09.000 vGS is greater than or equal to VT, vDS is greater than or equal 00:41:09.000 --> 00:41:14.000 to vGS minus VT. These constraints immediately 00:41:14.000 --> 00:41:20.000 follow from a statement of the type we are operating under the 00:41:20.000 --> 00:41:26.000 saturation discipline or the MOSFET is in saturation. 00:41:26.000 --> 00:41:32.000 Let me just mark this equation as A, and we will refer to it 00:41:32.000 --> 00:41:34.000 again. 00:41:45.000 --> 00:41:49.000 So with this new little circuit with the MOSFET working as a 00:41:49.000 --> 00:41:53.000 current source, let's go ahead and analyze our 00:41:53.000 --> 00:41:56.000 amplifier. Notice that to analyze the 00:41:56.000 --> 00:42:01.000 circuit I have a current source. It's a dependent current source 00:42:01.000 --> 00:42:07.000 where the current depends on the square of the input. 00:42:07.000 --> 00:42:12.000 So I want to go and analyze it. This is a nonlinear circuit. 00:42:12.000 --> 00:42:17.000 So I can apply any one of the methods that we talked about 00:42:17.000 --> 00:42:20.000 last week for nonlinear circuits. 00:42:20.000 --> 00:42:26.000 To analyze it I will go ahead and use the analytical method. 00:42:26.000 --> 00:42:31.000 And my goal will be to obtain vO versus vI. 00:42:31.000 --> 00:42:33.000 Again, remember where are we here? 00:42:33.000 --> 00:42:37.000 The MOSFET circuit operating in saturation so I can replace this 00:42:37.000 --> 00:42:40.000 with a current source. It is nonlinear. 00:42:40.000 --> 00:42:44.000 And so I can apply one of the two methods, the analytical 00:42:44.000 --> 00:42:49.000 method or the graphical method. Let's do both and start with 00:42:49.000 --> 00:42:52.000 the analytical method. The analytical method simply 00:42:52.000 --> 00:42:55.000 says go forth, apply the node method and 00:42:55.000 --> 00:42:56.000 solve. Simple stuff. 00:42:56.000 --> 00:43:00.000 Let's go ahead and do that. Node method. 00:43:00.000 --> 00:43:04.000 I have a single node here that is of interest. 00:43:04.000 --> 00:43:07.000 I know the voltage vI at this node. 00:43:07.000 --> 00:43:09.000 I know the voltage VS at this node. 00:43:09.000 --> 00:43:12.000 So the only unknown is here at vO. 00:43:12.000 --> 00:43:17.000 So I will go ahead and do that. Let me go ahead and equate the 00:43:17.000 --> 00:43:19.000 currents into the node to be zero. 00:43:19.000 --> 00:43:23.000 So the currents out of the node here are iDS. 00:43:23.000 --> 00:43:27.000 And that was equal the current into that same node. 00:43:27.000 --> 00:43:32.000 So iDS must equal VS minus vO divided by RL. 00:43:32.000 --> 00:43:39.000 iDS=VS-vO/RL. For later reference, 00:43:39.000 --> 00:43:46.000 let me call that B. Simplifying, 00:43:46.000 --> 00:43:55.000 what I can do is, we know that iDS is given by 00:43:55.000 --> 00:44:03.000 K/2(vI-VT)^2. So I replace iDS with this 00:44:03.000 --> 00:44:08.000 expression and I multiply that by RL. 00:44:08.000 --> 00:44:15.000 So I get K/2(vI-VT)RL. So iDS gets multiplied by RL 00:44:15.000 --> 00:44:22.000 and I get vO on this side and VS remains out here. 00:44:22.000 --> 00:44:30.000 All I have done is multiplied both sides by RL. 00:44:30.000 --> 00:44:33.000 So it is RL iDS, taken RL iDS to this side, 00:44:33.000 --> 00:44:37.000 that is here, I get the minus sign, 00:44:37.000 --> 00:44:40.000 and VS stays here, vO comes here. 00:44:40.000 --> 00:44:45.000 So that is my final expression. Remember this is true under 00:44:45.000 --> 00:44:50.000 certain conditions. I will keep hammering that home 00:44:50.000 --> 00:44:55.000 because some of the most common errors made by people is in 00:44:55.000 --> 00:45:02.000 forgetting the constraints under which this was obtained. 00:45:02.000 --> 00:45:08.000 And the constraint under which this was obtained is the 00:45:08.000 --> 00:45:14.000 saturation discipline. And that was true when vGS for 00:45:14.000 --> 00:45:21.000 a MOSFET was greater than or equal to VT and vDS for a MOSFET 00:45:21.000 --> 00:45:26.000 was greater than or equal to vGS minus VT. 00:45:26.000 --> 00:45:33.000 I also know that for vGS less than VT, vO=VS. 00:45:33.000 --> 00:45:38.000 So when vGS is less than VT then this one turns off. 00:45:38.000 --> 00:45:44.000 That's why it is the SCS model, switch current source model. 00:45:44.000 --> 00:45:50.000 When vGS is less than zero it turns off and VS directly 00:45:50.000 --> 00:45:54.000 appears at vO. I would like to stare at this 00:45:54.000 --> 00:46:00.000 constraint with you for a second, vDS greater than or 00:46:00.000 --> 00:46:08.000 equal to vGS minus VT here. And vDS is simply vO. 00:46:08.000 --> 00:46:17.000 I want to rewrite this constraint in terms of iDS. 00:46:17.000 --> 00:46:26.000 It will come in handy. So iDS is K/2(vI-VT)^2. 00:46:26.000 --> 00:46:34.000 This is vI-VT. So vI-VT is simply square root 00:46:34.000 --> 00:46:39.000 of 2iDS/K. In other words, 00:46:39.000 --> 00:46:45.000 I can write iDS less than or equal to K/2vO^2. 00:46:45.000 --> 00:46:53.000 So this constraint expressed in terms of iDS is simply iDS less 00:46:53.000 --> 00:46:57.000 than or equal to K/2vO^2. 00:47:05.000 --> 00:47:10.000 So all I've done here is analyzed this nonlinear circuit. 00:47:10.000 --> 00:47:15.000 I can also analyze it using the graphical method. 00:47:15.000 --> 00:47:20.000 And in order to do that, for my nonlinear circuit, 00:47:20.000 --> 00:47:24.000 in order to do that, all I have to do is plot. 00:47:24.000 --> 00:47:29.000 Let's have iDS here and vDS here. 00:47:29.000 --> 00:47:36.000 And as we did with a nonlinear expo dweeb, what I do is I plot 00:47:36.000 --> 00:47:41.000 the device characteristics iDS versus vDS. 00:47:41.000 --> 00:47:48.000 The device characteristics under saturation look like this, 00:47:48.000 --> 00:47:53.000 so vGS increasing. iDS versus vDS has a bunch of 00:47:53.000 --> 00:48:02.000 curves that look like current sources of increasing values. 00:48:02.000 --> 00:48:06.000 That simply reflects equation A. 00:48:06.000 --> 00:48:15.000 And then I superimpose on top of that the expression that 00:48:15.000 --> 00:48:22.000 comes up due to equation B which is iDS equals, 00:48:22.000 --> 00:48:32.000 let me write that down here, iDS equals VS/RL - vO/RL. 00:48:32.000 --> 00:48:35.000 That's B. And let me plot that. 00:48:35.000 --> 00:48:43.000 That is a straight line relationship between iDS and vO. 00:48:43.000 --> 00:48:47.000 And so when vO is zero iDS is VS/RL. 00:48:47.000 --> 00:48:52.000 And when iDS is zero vO equals VS. 00:48:52.000 --> 00:48:56.000 Remember, vO and vDS are the same. 00:48:56.000 --> 00:49:03.000 So this is what I get. This is the straight line 00:49:03.000 --> 00:49:07.000 corresponding to equation B here. 00:49:13.000 --> 00:49:17.000 And, as before, we just find the point where 00:49:17.000 --> 00:49:21.000 the two intersect. Let's say I am given some value 00:49:21.000 --> 00:49:25.000 of vGS. And let's say I am given some 00:49:25.000 --> 00:49:29.000 known value of vDS. So for that I can go ahead and 00:49:29.000 --> 00:49:36.000 find out the corresponding value of iDS from this graph. 00:49:36.000 --> 00:49:40.000 Just as I told you when we did the expo dweeb stuff, 00:49:40.000 --> 00:49:43.000 this line here is called a load line. 00:49:43.000 --> 00:49:47.000 You will be seeing that again and again and again where we 00:49:47.000 --> 00:49:52.000 have the equation corresponding to the one shown here, 00:49:52.000 --> 00:49:57.000 the equation written for the output loop superimposed on the 00:49:57.000 --> 00:50:02.000 device characteristics. That's called a load line. 00:50:02.000 --> 00:50:06.000 So I can get this point corresponding to the operating 00:50:06.000 --> 00:50:11.000 point of the MOSFET for this iDS, vDS and vGS by using the 00:50:11.000 --> 00:50:14.000 graphical method. In the next lecture we are 00:50:14.000 --> 00:50:18.000 going to look at, given a device of this sort, 00:50:18.000 --> 00:50:23.000 how do we figure out the boundaries of valid operation so 00:50:23.000 --> 00:50:26.000 that the MOSFET stays in saturation?