WEBVTT 00:00:00.000 --> 00:00:05.000 All right, let's get moving. Good morning. 00:00:05.000 --> 00:00:13.000 Let me take a quick poll. So, how many of you have 00:00:13.000 --> 00:00:17.000 completed Lab 4. Completed Lab 4? 00:00:17.000 --> 00:00:24.000 Wow, that's great. So, how many people have begun 00:00:24.000 --> 00:00:30.000 Lab 4? OK, well that's good. 00:00:30.000 --> 00:00:35.000 I won't ask the last question. OK so, well I hope you're 00:00:35.000 --> 00:00:40.000 having fun with this lab. Lab 4 was designed to be almost 00:00:40.000 --> 00:00:44.000 like a mini-project. And, it sort of ties together a 00:00:44.000 --> 00:00:48.000 lot of the content of the entire course. 00:00:48.000 --> 00:00:54.000 And, it's not unlike the kind of systems that people design in 00:00:54.000 --> 00:00:59.000 industry, in systems that go into a variety of devices like, 00:00:59.000 --> 00:01:03.000 say, for example, digital CD players and stuff 00:01:03.000 --> 00:01:10.000 like that. A lot of mixed signal stuff 00:01:10.000 --> 00:01:14.000 goes in. OK, so today, 00:01:14.000 --> 00:01:24.000 I'm going to continue with our discussion of energy and CMOS. 00:01:24.000 --> 00:01:34.000 CMOS will be a new topic that I will introduce. 00:01:34.000 --> 00:01:37.000 So, the last lecture, we spent a fair bit of time 00:01:37.000 --> 00:01:41.000 talking about energy, and how to compute the energy 00:01:41.000 --> 00:01:44.000 of our inverter. So, let me start from where I 00:01:44.000 --> 00:01:48.000 left off, and I've given you a couple of extra pages of notes 00:01:48.000 --> 00:01:52.000 today just to sort of tie it to the previous lecture. 00:01:52.000 --> 00:01:57.000 Right now, I'm going to start off on page three. 00:01:57.000 --> 00:02:02.000 So, what we saw last time was an inverter of this sort, 00:02:02.000 --> 00:02:07.000 Vs, VIN, and we said, let's study the situation where 00:02:07.000 --> 00:02:11.000 this inverter was driving a load capacitor, C. 00:02:11.000 --> 00:02:15.000 Where did this load capacitor come from? 00:02:15.000 --> 00:02:19.000 Well, this inverter could be driving one, or two, 00:02:19.000 --> 00:02:23.000 or three, or four other larger gates, OK? 00:02:23.000 --> 00:02:29.000 So, this C is lumped value of the gate capacitances of all of 00:02:29.000 --> 00:02:36.000 those inverters. This may also include some 00:02:36.000 --> 00:02:44.000 component due to wiring capacitance and stuff like that. 00:02:44.000 --> 00:02:54.000 So, for an inverter like this, we showed in the last lecture 00:02:54.000 --> 00:03:02.000 that the formula for the average power was, 00:03:02.000 --> 00:03:07.000 so this was a static power independent of frequency, 00:03:07.000 --> 00:03:13.000 and this was called dynamic power, and it had some bearing, 00:03:13.000 --> 00:03:19.000 it's related to the frequency at which you clocked your 00:03:19.000 --> 00:03:23.000 circuit. So, this was related to standby 00:03:23.000 --> 00:03:30.000 power, and this to dynamic. So, what I also said is that I 00:03:30.000 --> 00:03:38.000 gave you a bunch of numbers so you could compute the power 00:03:38.000 --> 00:03:44.000 consumption of a chip that included 10^8 gates, 00:03:44.000 --> 00:03:50.000 100 million gates, and at a frequency of 1 GHz, 00:03:50.000 --> 00:03:57.000 and a bunch of other numbers. C was given to be 0.1 00:03:57.000 --> 00:04:02.000 femtofarads. Femto is 10^-15. 00:04:02.000 --> 00:04:08.000 So, F was 10^9. VS was 5V, and for these 00:04:08.000 --> 00:04:16.000 numbers, if you plonk them down in something like this, 00:04:16.000 --> 00:04:25.000 for 10^8 gates on a chip, the average power would be 10^8 00:04:25.000 --> 00:04:32.000 times these two. So, this would be five squared, 00:04:32.000 --> 00:04:39.000 which is 25, divided by twice. 00:04:39.000 --> 00:04:45.000 RL was given to be 10 kilo-ohms, so, 00:04:45.000 --> 00:04:52.000 twice, 10^4. And here we had CVS^2. 00:04:52.000 --> 00:05:00.000 So, C was 10^-16, 0.1 femtofarads. 00:05:00.000 --> 00:05:04.000 Vs^2 was 25, and F was 10^9. 00:05:04.000 --> 00:05:11.000 So, if you commence through the numbers here, 00:05:11.000 --> 00:05:20.000 what you end up getting is something that looks like this, 00:05:20.000 --> 00:05:29.000 10^8 times this guy here. This is 1.25mW plus this guy 00:05:29.000 --> 00:05:39.000 ends up being 2.5 microwatts. So, this should come as a bit 00:05:39.000 --> 00:05:43.000 of a shocker. If I take 1.25mW, 00:05:43.000 --> 00:05:51.000 and multiply that out by 10^8, this says that each gate 00:05:51.000 --> 00:05:57.000 suffers a standby power loss of 1.25mW. 00:05:57.000 --> 00:06:01.000 So times 10^8, I get 125kW, 00:06:01.000 --> 00:06:07.000 and this guy yields 250W. OK, the 250W is manageable. 00:06:07.000 --> 00:06:11.000 It's still high, and just so you don't think 00:06:11.000 --> 00:06:14.000 that this is unreasonable, when the Pentium 4 first came 00:06:14.000 --> 00:06:17.000 out, it was consuming 170W of power. 00:06:17.000 --> 00:06:20.000 OK, you should see the heat sinks on there. 00:06:20.000 --> 00:06:24.000 There's actually a huge heat sink with a fan built into the 00:06:24.000 --> 00:06:28.000 top of the heat sink. OK, today it's down to more 00:06:28.000 --> 00:06:32.000 reasonable numbers like 100W and so on, but when it came out it 00:06:32.000 --> 00:06:36.000 was in this range. So it's high but not 00:06:36.000 --> 00:06:39.000 unreasonable. But this, of course, 00:06:39.000 --> 00:06:42.000 is totally wacko. OK, imagine carrying a laptop 00:06:42.000 --> 00:06:45.000 around, and the sucker is blowing 125kW. 00:06:45.000 --> 00:06:49.000 That'll be fun. So, clearly there's something 00:06:49.000 --> 00:06:52.000 wrong here. What this is saying is that 00:06:52.000 --> 00:06:57.000 this gate here consumes 125kW, there are 10^8 of these on a 00:06:57.000 --> 00:07:00.000 single chip. OK, so we clearly have to do 00:07:00.000 --> 00:07:04.000 something about this, otherwise the semiconductor 00:07:04.000 --> 00:07:10.000 industry would fail. So, anybody have any ideas? 00:07:10.000 --> 00:07:14.000 What do you think you might do here? 00:07:14.000 --> 00:07:21.000 What do you think you might do to this inverter to make this 00:07:21.000 --> 00:07:26.000 look better, to bring it down? What can I do? 00:07:26.000 --> 00:07:28.000 Anybody? Any ideas? 00:07:28.000 --> 00:07:34.000 What do you think? Well, the problem is that if I 00:07:34.000 --> 00:07:38.000 look at this 125kW, well, there's a VS term here 00:07:38.000 --> 00:07:41.000 and an RL term here. So, I can increase RL. 00:07:41.000 --> 00:07:46.000 OK, I can make RL four times or eight times as large. 00:07:46.000 --> 00:07:49.000 That'll bring the power down somewhat. 00:07:49.000 --> 00:07:53.000 Can anybody think of any problem with increasing RL? 00:07:53.000 --> 00:07:55.000 If I make RL really, really large, 00:07:55.000 --> 00:08:00.000 will I run into other problems? Yes? 00:08:00.000 --> 00:08:02.000 Exactly, the slowdown of the inverter. 00:08:02.000 --> 00:08:07.000 Remember, the rise time of the inverter depends on how quickly 00:08:07.000 --> 00:08:10.000 I can charge this capacitor through RL. 00:08:10.000 --> 00:08:14.000 So, if I make my RL really large, I will consume less 00:08:14.000 --> 00:08:19.000 standby power from hundreds of kilowatts to merely tens of 00:08:19.000 --> 00:08:22.000 kilowatts. But my gates will run as slow 00:08:22.000 --> 00:08:25.000 as molasses. So, clearly that's not a 00:08:25.000 --> 00:08:29.000 tradeoff I would like to make. So, I can reduce my voltage to 00:08:29.000 --> 00:08:34.000 maybe a volt. But that just reduces it by a 00:08:34.000 --> 00:08:37.000 factor of 25, VS squared. 00:08:37.000 --> 00:08:40.000 So clearly, this is not going to work. 00:08:40.000 --> 00:08:47.000 I have to somehow do something else, and that will be the topic 00:08:47.000 --> 00:08:51.000 of today's lecture. Also, I will dwell for a moment 00:08:51.000 --> 00:08:55.000 on this term. So, if you look at the spec 00:08:55.000 --> 00:09:01.000 sheet for the IBM's ASIC processor that we handed out, 00:09:01.000 --> 00:09:04.000 if you recall, we talked about power 00:09:04.000 --> 00:09:11.000 dissipation of 0.006 microwatts per MHz per gate. 00:09:11.000 --> 00:09:14.000 OK, now you see where this is coming from. 00:09:14.000 --> 00:09:17.000 Per MHz, that's because it's a multiple of f, 00:09:17.000 --> 00:09:21.000 the power. Second is that it's per gate, 00:09:21.000 --> 00:09:25.000 so this is the power per gate. So, as I have more gates, 00:09:25.000 --> 00:09:30.000 I just have that much more power dissipation. 00:09:30.000 --> 00:09:34.000 It also says power supply voltage in the range of 0.7 to 00:09:34.000 --> 00:09:36.000 1.3 right next to the power expression. 00:09:36.000 --> 00:09:40.000 So, you can see why they tell you all of that, 00:09:40.000 --> 00:09:43.000 because both voltage, and the frequency, 00:09:43.000 --> 00:09:47.000 and the number of gates come into the power of equation. 00:09:47.000 --> 00:09:50.000 OK, this really simple expression here, 00:09:50.000 --> 00:09:54.000 it's amazing how close this is to what people use for the 00:09:54.000 --> 00:09:59.000 dynamic power in chips. OK, so as the next step, 00:09:59.000 --> 00:10:04.000 what I'd like to do is, this guy, what do we do about 00:10:04.000 --> 00:10:07.000 that? OK, so we've taught you to 00:10:07.000 --> 00:10:13.000 build gates in a particular matter, but it's a non-starter. 00:10:13.000 --> 00:10:16.000 So, how do we get rid of static power? 00:10:16.000 --> 00:10:19.000 How do we get rid of static power? 00:10:19.000 --> 00:10:24.000 OK, to do so, let's build up a little bit of 00:10:24.000 --> 00:10:27.000 intuition. OK, so the intuition goes as 00:10:27.000 --> 00:10:31.000 follows. So let's say I take my 00:10:31.000 --> 00:10:33.000 inverter. Let me draw the circuit both on 00:10:33.000 --> 00:10:36.000 the on state and in the off state. 00:10:50.000 --> 00:10:55.000 So, when VIN is high, when VIN is high, 00:10:55.000 --> 00:11:02.000 I get the MOSFET turning on and has a resistance, 00:11:02.000 --> 00:11:07.000 RON, and Vo is the output voltage. 00:11:07.000 --> 00:11:14.000 Similarly, when VIN is low, so when VIN was high, 00:11:14.000 --> 00:11:20.000 Vo was low because RON is much less than RL. 00:11:20.000 --> 00:11:27.000 So, this voltage was low, while here, when VIN is low, 00:11:27.000 --> 00:11:34.000 the MOSFET is off, and so I have an open circuit 00:11:34.000 --> 00:11:39.000 out here. And because of that open 00:11:39.000 --> 00:11:43.000 circuit, the voltage here was going to be high because VS 00:11:43.000 --> 00:11:47.000 would simply appear there. So let's tailor this and see if 00:11:47.000 --> 00:11:50.000 we can build up some intuition as to what to do. 00:11:50.000 --> 00:11:53.000 So, when VIN is low, I don't have any static power 00:11:53.000 --> 00:11:57.000 being dissipated because I don't have a connection from VS to 00:11:57.000 --> 00:11:59.000 ground. OK, the current, 00:11:59.000 --> 00:12:03.000 i, is zero. And, VS simply appears at the 00:12:03.000 --> 00:12:07.000 output. The reason this is so is have a 00:12:07.000 --> 00:12:09.000 switch here. So when this is low, 00:12:09.000 --> 00:12:15.000 the switch opens up and cuts the path from power to ground. 00:12:15.000 --> 00:12:19.000 This is a nice situation. Here, when VIN was high, 00:12:19.000 --> 00:12:22.000 there was no switch that turns off. 00:12:22.000 --> 00:12:26.000 Rather, I get a connection from VS to ground. 00:12:26.000 --> 00:12:30.000 OK, so think about this situation here. 00:12:30.000 --> 00:12:34.000 The insight here is, just imagine if I could do the 00:12:34.000 --> 00:12:38.000 following. Imagine if I could somehow 00:12:38.000 --> 00:12:42.000 magically elevate RL to be a very, very, very large number, 00:12:42.000 --> 00:12:46.000 if I could make this so high as to make the power really low 00:12:46.000 --> 00:12:50.000 only in the situation when the input was high, 00:12:50.000 --> 00:12:51.000 OK? So, imagine if I could do 00:12:51.000 --> 00:12:57.000 something like this. Imagine I could open circuit 00:12:57.000 --> 00:13:00.000 this guy, RON, so when VIN was high, 00:13:00.000 --> 00:13:07.000 if I could, instead of having an RL here, what if somehow I 00:13:07.000 --> 00:13:11.000 could make this RL become infinity? 00:13:11.000 --> 00:13:15.000 OK, so in this case, output VO would be low. 00:13:15.000 --> 00:13:19.000 OK, I get many benefits by doing this. 00:13:19.000 --> 00:13:25.000 One benefit is that, look, I have opened this switch 00:13:25.000 --> 00:13:29.000 here so I don't have any standby current. 00:13:29.000 --> 00:13:35.000 OK, the standby current is zero. 00:13:35.000 --> 00:13:39.000 The second benefit is that my output gets dragged down to 00:13:39.000 --> 00:13:41.000 ground, OK? Out here, my output was VS 00:13:41.000 --> 00:13:45.000 multiplied by RON divided by the sum of these two. 00:13:45.000 --> 00:13:48.000 Out here, I have a direct connection to ground, 00:13:48.000 --> 00:13:52.000 and nothing to the power supply, VS, and so therefore I 00:13:52.000 --> 00:13:56.000 have a nice, solid low. So the question is that, 00:13:56.000 --> 00:14:01.000 can I get this situation? OK, that is a key insight. 00:14:01.000 --> 00:14:04.000 So, imagine that somehow, when this was high, 00:14:04.000 --> 00:14:08.000 I could get this to open up, much like when this was low, 00:14:08.000 --> 00:14:11.000 I got this to open up. OK, so think about it. 00:14:11.000 --> 00:14:15.000 So, the intuition is that what I need instead of a resistor 00:14:15.000 --> 00:14:19.000 here, what if I have something like the MOSFET that I have 00:14:19.000 --> 00:14:22.000 here? So, I have a MOSFET here that 00:14:22.000 --> 00:14:25.000 turned off when VIN was low. OK, what if I did the 00:14:25.000 --> 00:14:30.000 complementary thing? What if I put in some kind of 00:14:30.000 --> 00:14:35.000 MOSFET here that would turn off when VIN was high? 00:14:35.000 --> 00:14:41.000 OK, so, much like the MOSFET turned off when VIN was low down 00:14:41.000 --> 00:14:47.000 here, imagine if I could find a device that could turn off when 00:14:47.000 --> 00:14:51.000 VIN was high? OK, this would be on, 00:14:51.000 --> 00:14:56.000 but this would be off. So the behavior of this device 00:14:56.000 --> 00:15:02.000 would have to be complementary to this device. 00:15:02.000 --> 00:15:07.000 So, we need some sort of a switch to introduce this new, 00:15:07.000 --> 00:15:12.000 little MOSFET device with slightly different properties, 00:15:12.000 --> 00:15:18.000 let me quickly review for you the properties of the MOSFET 00:15:18.000 --> 00:15:22.000 that we know about, so our N channel MOSFET, 00:15:22.000 --> 00:15:27.000 also called the NFET, this is what we've been seeing 00:15:27.000 --> 00:15:31.000 all this while, is drawn like this. 00:15:31.000 --> 00:15:34.000 I have a gate; I have a drain; 00:15:34.000 --> 00:15:42.000 I have a source. And this guy is on when VGS is 00:15:42.000 --> 00:15:52.000 greater than or equal to VT, OK, and off when VGS is less 00:15:52.000 --> 00:15:57.000 than VT. You saw this before, 00:15:57.000 --> 00:16:04.000 OK, nothing new here. So, what I need is a device 00:16:04.000 --> 00:16:09.000 that behaves in a complementary manner. 00:16:09.000 --> 00:16:13.000 OK, so the device is a P channel MOSFET. 00:16:13.000 --> 00:16:19.000 By the way, I must point out, till about 1983-84 until the 00:16:19.000 --> 00:16:24.000 early '80s, that's exactly pretty much how chips were 00:16:24.000 --> 00:16:29.000 designed, OK, using an NFET for the switch 00:16:29.000 --> 00:16:34.000 looking down here, and a variety of different 00:16:34.000 --> 00:16:40.000 kinds of devices to be used as resistors. 00:16:40.000 --> 00:16:44.000 OK, that's when technology began moving towards this new 00:16:44.000 --> 00:16:48.000 kind of technology I'm going to talk about, and that 00:16:48.000 --> 00:16:51.000 dramatically reducing the power consumed. 00:16:51.000 --> 00:16:55.000 And, the P channel MOSFET was created, and this guy's called 00:16:55.000 --> 00:16:58.000 the PFET. It's a complementary device 00:16:58.000 --> 00:17:03.000 that looks as follows. OK, the difference here is 00:17:03.000 --> 00:17:06.000 that, to show this is complementary, 00:17:06.000 --> 00:17:09.000 I'll put a little circle here. It has a gate. 00:17:09.000 --> 00:17:14.000 Just to make things a little clearer, flip the drain and 00:17:14.000 --> 00:17:17.000 source terminals, and this guy is on at a 00:17:17.000 --> 00:17:22.000 distinguished threshold voltage of this with the NFET device, 00:17:22.000 --> 00:17:27.000 let me put an N here to say that this is the VT for the N 00:17:27.000 --> 00:17:31.000 channel device. And for this guy, 00:17:31.000 --> 00:17:36.000 this guy came on when VGS was greater than some voltage. 00:17:36.000 --> 00:17:38.000 So, VTN could be, for example, 00:17:38.000 --> 00:17:42.000 one volt. So, VGS was more than one. 00:17:42.000 --> 00:17:44.000 This turned on. In this case, 00:17:44.000 --> 00:17:49.000 I wanted this to turn on when VGS is some value which is lower 00:17:49.000 --> 00:17:53.000 than, or much lower than, the source voltage. 00:17:53.000 --> 00:18:00.000 OK, so this guy turns on when the gate voltage is higher. 00:18:00.000 --> 00:18:03.000 This guy should turn on when the gate voltage is 00:18:03.000 --> 00:18:07.000 significantly lower than the source voltage, 00:18:07.000 --> 00:18:10.000 just the complementary behavior. 00:18:10.000 --> 00:18:13.000 OK, so when VGS is less than or equal to VTP. 00:18:13.000 --> 00:18:17.000 And in this case, the threshold voltage for the 00:18:17.000 --> 00:18:20.000 PMOS device, say, just as an example, 00:18:20.000 --> 00:18:23.000 maybe -1V. So this means that if the 00:18:23.000 --> 00:18:25.000 source is at, say, 5V, OK, 00:18:25.000 --> 00:18:30.000 then this device would turn on if the gate, for example, 00:18:30.000 --> 00:18:35.000 using that example was less than 4V. 00:18:35.000 --> 00:18:39.000 So, this is five. If the gate fell below 4V, 00:18:39.000 --> 00:18:43.000 this guy would turn on. In this situation, 00:18:43.000 --> 00:18:49.000 remember, if this was at zero, the gate would have to be 00:18:49.000 --> 00:18:53.000 greater than 1V to turn on. In this situation, 00:18:53.000 --> 00:18:59.000 the gate has to be less than 4V if the source was at five to 00:18:59.000 --> 00:19:03.000 turn on. And, it's off. 00:19:03.000 --> 00:19:06.000 OK, so this is a complementary device that I postulate that 00:19:06.000 --> 00:19:08.000 behaves in a complementary manner. 00:19:08.000 --> 00:19:11.000 So, the gate voltage rises, this guy turns on, 00:19:11.000 --> 00:19:14.000 and in this situation, when the gate voltage drops 00:19:14.000 --> 00:19:17.000 below the source voltage, this guy turns on. 00:19:17.000 --> 00:19:20.000 OK, so when there's a rising guy that turns on in this 00:19:20.000 --> 00:19:24.000 particular situation when it falls, the gate turns on and 00:19:24.000 --> 00:19:26.000 shows some resistance. In this case, 00:19:26.000 --> 00:19:29.000 the resistance would be RON. And to show that it's N 00:19:29.000 --> 00:19:34.000 channel, let me say N. And in this case, 00:19:34.000 --> 00:19:39.000 the resistance, when it turns on, 00:19:39.000 --> 00:19:44.000 would be RONp to represent P channel. 00:19:44.000 --> 00:19:51.000 OK, so now consider the following circuit for the 00:19:51.000 --> 00:19:56.000 inverter. So, instead of my resistor, 00:19:56.000 --> 00:20:05.000 I put a complementary device, OK, and that's it. 00:20:05.000 --> 00:20:09.000 So all I've done here is replace my resistor with a 00:20:09.000 --> 00:20:14.000 MOSFET that behaves complementary to the N channel 00:20:14.000 --> 00:20:16.000 MOSFET. So this is my gate, 00:20:16.000 --> 00:20:19.000 my drain. This is my source, 00:20:19.000 --> 00:20:22.000 my gate, my source, and my drain. 00:20:22.000 --> 00:20:27.000 OK, and this guy is called a pull up, and this guy is called 00:20:27.000 --> 00:20:33.000 a pull down. OK, and the reason is that this 00:20:33.000 --> 00:20:37.000 guy pulls the output to ground when it's turned on, 00:20:37.000 --> 00:20:41.000 while this guy, when switched on, 00:20:41.000 --> 00:20:46.000 will pull this node up to VS. So, I pull it down or pull it 00:20:46.000 --> 00:20:50.000 up based on when the VIN is high or low. 00:20:50.000 --> 00:20:54.000 So, let's look at the two situations. 00:20:54.000 --> 00:20:57.000 So, let's say, as an example, 00:20:57.000 --> 00:21:00.000 my VS is 5V, and let's say VIN in one 00:21:00.000 --> 00:21:05.000 situation being 5V, and another situation being 00:21:05.000 --> 00:21:11.000 equal to 0V. Let's draw the equivalent 00:21:11.000 --> 00:21:17.000 circuit in both these cases. So, when VIN is high, 00:21:17.000 --> 00:21:22.000 I have my usual circuit. When VIN is high, 00:21:22.000 --> 00:21:27.000 this MOSFET, as before, when VIN is 5V, 00:21:27.000 --> 00:21:35.000 the N channel MOSFET below is turned on, and so I have an RON 00:21:35.000 --> 00:21:40.000 resistance here. But remember, 00:21:40.000 --> 00:21:45.000 VIN is 5, and VS is 5V, then the voltage across the 00:21:45.000 --> 00:21:51.000 source and the gate of this P channel FET is now equal, 00:21:51.000 --> 00:21:55.000 five and five. OK, so this one would turn off. 00:21:55.000 --> 00:22:00.000 And that's the circuit that I get. 00:22:00.000 --> 00:22:05.000 The output is suitably low. In this situation, 00:22:05.000 --> 00:22:10.000 if VIN is zero, what happens in this situation? 00:22:10.000 --> 00:22:13.000 Here's my output. If VIN is 0V, 00:22:13.000 --> 00:22:17.000 the lower device turns off. This is zero. 00:22:17.000 --> 00:22:21.000 This is zero. This guy turns off, 00:22:21.000 --> 00:22:26.000 and that's the situation for the N channel MOSFET. 00:22:26.000 --> 00:22:33.000 How about this guy here? What happens here? 00:22:33.000 --> 00:22:37.000 This is at 5. So let me just, 00:22:37.000 --> 00:22:41.000 this is at 5V. OK, and VIN is at 0V. 00:22:41.000 --> 00:22:47.000 OK, so therefore, the GS of this is -5V. 00:22:47.000 --> 00:22:52.000 If this is zero and this is five, G, source, 00:22:52.000 --> 00:22:59.000 and drain, GS is -5V, and -5V is significantly less 00:22:59.000 --> 00:23:06.000 than the threshold -1V in our example. 00:23:06.000 --> 00:23:12.000 So, this one will switch on. And if this one switches on, 00:23:12.000 --> 00:23:17.000 what I end up getting is RONp out there. 00:23:17.000 --> 00:23:24.000 So, when this one kicks in, it pulls the output high and VO 00:23:24.000 --> 00:23:28.000 goes high. So, all I've done is replaced 00:23:28.000 --> 00:23:36.000 my resistor with a complementary device, which switches off when 00:23:36.000 --> 00:23:41.000 the input is high, and switches on when the input 00:23:41.000 --> 00:23:46.000 is low. And the beauty of this is that 00:23:46.000 --> 00:23:50.000 at no point, assuming all the devices are ideal here, 00:23:50.000 --> 00:23:55.000 at no point do I have a short circuit between the output, 00:23:55.000 --> 00:23:59.000 do I have a current path from the output to the ground from 00:23:59.000 --> 00:24:03.000 the supply to ground, OK, I have this turned off or 00:24:03.000 --> 00:24:09.000 this turned off. So, this type of logic 00:24:09.000 --> 00:24:18.000 involving a PMOS transistor here, and the N channel 00:24:18.000 --> 00:24:25.000 transistor here is called CMOS logic for, OK, 00:24:25.000 --> 00:24:31.000 it's called complementary MOS logic. 00:24:31.000 --> 00:24:39.000 That's what CMOS comes from. OK, so I'm sure you've read in 00:24:39.000 --> 00:24:43.000 a number of places that most digital chips today use CMOS 00:24:43.000 --> 00:24:46.000 technology. It comes from complementary 00:24:46.000 --> 00:24:51.000 MOS, and complementary comes from the use of complementary 00:24:51.000 --> 00:24:55.000 transistors: N channel, P channel, turns on when high, 00:24:55.000 --> 00:24:58.000 turns off when high, turns off when low, 00:24:58.000 --> 00:25:01.000 turns on when low. OK, that's exactly 00:25:01.000 --> 00:25:07.000 complementary to each other. OK, so what you've seen here 00:25:07.000 --> 00:25:13.000 has been the workhorse of the digital industry for the past 00:25:13.000 --> 00:25:16.000 two decades, 20 years, CMOS logic. 00:25:16.000 --> 00:25:21.000 OK, and even the most advanced chip from Intel has an inverter 00:25:21.000 --> 00:25:26.000 that looks exactly like that. OK, if you count all the 00:25:26.000 --> 00:25:32.000 inverters in the universe today, I would say a significant 00:25:32.000 --> 00:25:37.000 fraction of those look exactly like that, no difference, 00:25:37.000 --> 00:25:42.000 just so simple. So, the key with something like 00:25:42.000 --> 00:25:47.000 that is there is no path from the power supply to the ground, 00:25:47.000 --> 00:25:51.000 and so by that model, I did not consume any standby 00:25:51.000 --> 00:25:54.000 power. OK, my standby power in that 00:25:54.000 --> 00:25:58.000 idealized model is zero. So, let's compute P. 00:25:58.000 --> 00:26:04.000 So, what is P dynamic? Let's use the method that we 00:26:04.000 --> 00:26:11.000 adopted in the last lecture, and draw the equivalent 00:26:11.000 --> 00:26:18.000 circuit, and compute the power. OK, so I'm going to model the 00:26:18.000 --> 00:26:24.000 following situation, and assume that I drive a 00:26:24.000 --> 00:26:26.000 capacitive load, C. 00:26:26.000 --> 00:26:32.000 OK, and as an input, as I did the last time, 00:26:32.000 --> 00:26:38.000 I'm going to assume I have some input voltage, 00:26:38.000 --> 00:26:45.000 VIN, that looks like this. The cycle time, 00:26:45.000 --> 00:26:53.000 T, and the frequency is 1/t, and let me assume that this is 00:26:53.000 --> 00:26:59.000 T1, and this is T2. OK, and I'm assuming that T1 00:26:59.000 --> 00:27:09.000 and T2 are both much larger than the respective time constants. 00:27:09.000 --> 00:27:13.000 OK, the time constants when, for discharging here, 00:27:13.000 --> 00:27:18.000 is C RONn, and here the relevant resistance is RONp. 00:27:18.000 --> 00:27:23.000 The charging time constant is RONp times C. 00:27:23.000 --> 00:27:30.000 OK, so T1 and T2 are assumed to be much greater than these two. 00:27:30.000 --> 00:27:34.000 So when you look at this, there's one other benefit 00:27:34.000 --> 00:27:38.000 besides the power benefit, OK, of using CMOS logic 00:27:38.000 --> 00:27:43.000 compared to using NMOS. OK, it not only cuts out my 00:27:43.000 --> 00:27:46.000 standby power, but there is another 00:27:46.000 --> 00:27:51.000 significant advantage which is almost equal to the power 00:27:51.000 --> 00:27:54.000 advantage of this kind of CMOS technology. 00:27:54.000 --> 00:28:00.000 Anybody have any ideas? What's the advantage? 00:28:00.000 --> 00:28:05.000 What does intuition tell you? Is CMOS going to be faster or 00:28:05.000 --> 00:28:07.000 slower than NMOS? Why? 00:28:07.000 --> 00:28:11.000 That's right. The key here is that the NMOS 00:28:11.000 --> 00:28:16.000 design I showed you earlier was relatively slow because it took 00:28:16.000 --> 00:28:21.000 me a while to charge up the load capacitor from RL. 00:28:21.000 --> 00:28:24.000 In this situation, RL will become really, 00:28:24.000 --> 00:28:27.000 really small; it's RONp. 00:28:27.000 --> 00:28:32.000 It's roughly the same magnitude as RONm. 00:28:32.000 --> 00:28:35.000 OK, if so both of these on resistances are more or less 00:28:35.000 --> 00:28:39.000 equal and small, then the rise time will be of 00:28:39.000 --> 00:28:42.000 the same order of magnitude as the fall time, 00:28:42.000 --> 00:28:45.000 which makes this much faster than the NMOS. 00:28:45.000 --> 00:28:49.000 In NMOS, my time constant was RLC, and RL was pretty large. 00:28:49.000 --> 00:28:53.000 In this case it's RONp C, and RONp can be made to be very 00:28:53.000 --> 00:28:58.000 small because when it's switched off, the resistance here is 00:28:58.000 --> 00:29:02.000 infinity. So, in this situation, 00:29:02.000 --> 00:29:07.000 if I assume T1 and T2 are much larger than the respective time 00:29:07.000 --> 00:29:12.000 constants, I can go ahead and draw my equivalent circuit. 00:29:12.000 --> 00:29:16.000 So, here's VS. So, for charging up, 00:29:16.000 --> 00:29:20.000 let's say this one is going to a one, or to a high. 00:29:20.000 --> 00:29:24.000 So, I have VS going through a resistor, RONp, 00:29:24.000 --> 00:29:30.000 to a capacitor, and this thing is a switch. 00:29:30.000 --> 00:29:34.000 So I have RONp, an ideal switch, 00:29:34.000 --> 00:29:40.000 going to a capacitor, C, this is my V out node, 00:29:40.000 --> 00:29:46.000 OK, so it's VS going through a resistance, RONp, 00:29:46.000 --> 00:29:50.000 an ideal switch, to a capacitor, 00:29:50.000 --> 00:29:54.000 C. That's a charging circuit. 00:29:54.000 --> 00:30:00.000 For discharging, I have C, discharging through 00:30:00.000 --> 00:30:06.000 an ideal switch with RONn. So, this situation, 00:30:06.000 --> 00:30:12.000 I have an ideal switch, RONn. 00:30:12.000 --> 00:30:20.000 OK, so that's the equivalent circuit for something like this. 00:30:20.000 --> 00:30:27.000 So, in this circuit, during T1, this guy's off, 00:30:27.000 --> 00:30:31.000 and this guy's on, on during T1, 00:30:31.000 --> 00:30:37.000 and off otherwise. This guy is on during T2, 00:30:37.000 --> 00:30:41.000 and off otherwise. OK, so just imagine, 00:30:41.000 --> 00:30:45.000 this guy switches on, this guy switches off, 00:30:45.000 --> 00:30:49.000 this guy switches on, this guy switches off, 00:30:49.000 --> 00:30:50.000 OK? And remember, 00:30:50.000 --> 00:30:56.000 this is exactly the circuit I had analyzed last time in the 00:30:56.000 --> 00:30:59.000 last lecture, and the result given by v 00:30:59.000 --> 00:31:03.000 double asterisk. And that result was simply 00:31:03.000 --> 00:31:10.000 average power being CVS^2f. That's the exact circuit we 00:31:10.000 --> 00:31:13.000 used to compute the dynamic power, CVS^2f. 00:31:13.000 --> 00:31:17.000 OK, so we're done. And how did this come about? 00:31:17.000 --> 00:31:21.000 This came about because the intuition here is that I'm 00:31:21.000 --> 00:31:26.000 charging up the capacitor fully, and then I'm discharging the 00:31:26.000 --> 00:31:30.000 capacitor through this other side, OK, and I'm consuming 00:31:30.000 --> 00:31:35.000 power, dissipating power, in these two resistances during 00:31:35.000 --> 00:31:39.000 charge up and during the discharge. 00:31:39.000 --> 00:31:43.000 Half the power gets consumed during charge up, 00:31:43.000 --> 00:31:49.000 and half during the discharge. So, I'd like to go back to 00:31:49.000 --> 00:31:54.000 doing a few numbers here, and taking a look at how, 00:31:54.000 --> 00:31:59.000 even with this expression, life can get pretty thorny as 00:31:59.000 --> 00:32:04.000 we go ahead into the next decade. 00:32:04.000 --> 00:32:15.000 OK, so for our previous example, we assumed that 10^8 00:32:15.000 --> 00:32:22.000 gates, F=1 GHz, C=0.1 femtofarads, 00:32:22.000 --> 00:32:32.000 VS was 5V, and I don't need RL anymore. 00:32:32.000 --> 00:32:36.000 OK, why is it that I don't have any resistance component here? 00:32:36.000 --> 00:32:40.000 I don't have it here because the power consumed by this 00:32:40.000 --> 00:32:44.000 circuit is independent of those resistances, provided T1 and T2 00:32:44.000 --> 00:32:48.000 are long enough, are much longer than the two 00:32:48.000 --> 00:32:50.000 time constants, RONp C, and RONn C. 00:32:50.000 --> 00:32:53.000 OK, so I don't have RL in my equation anymore. 00:32:53.000 --> 00:33:00.000 I don't have any standby power. So, based on this calculation, 00:33:00.000 --> 00:33:08.000 the calculation I did up there showed that I had 2.5 microwatts 00:33:08.000 --> 00:33:16.000 per gate, and for 10^8 gates I had 250W for a chip with 10^8 00:33:16.000 --> 00:33:21.000 gates. So, I'd like to dwell on this, 00:33:21.000 --> 00:33:27.000 if you can move over to page eight in your notes, 00:33:27.000 --> 00:33:31.000 here. Let me dwell on this for some 00:33:31.000 --> 00:33:38.000 time, and pontificate on a few things. 00:33:38.000 --> 00:33:40.000 First of all, this number, 00:33:40.000 --> 00:33:43.000 as I said before, is high, but not a disaster. 00:33:43.000 --> 00:33:48.000 OK, so you can't use this in laptops, but it's quite OK for a 00:33:48.000 --> 00:33:51.000 desktop or a server, and so on. 00:33:51.000 --> 00:33:55.000 If you just go and put your ear to a pedestal computer, 00:33:55.000 --> 00:34:00.000 you'll always hear it making a sound, and that sound is because 00:34:00.000 --> 00:34:07.000 of a big fan that's inside it. And, if you have a big enough 00:34:07.000 --> 00:34:10.000 fan, 250W is not such a big deal. 00:34:10.000 --> 00:34:17.000 But, this is certainly a real problem for mobile devices. 00:34:17.000 --> 00:34:20.000 For a laptop, this is unthinkable. 00:34:20.000 --> 00:34:24.000 OK, so we have to deal with this. 00:34:24.000 --> 00:34:30.000 The second issue is the following, that it's 250W for 00:34:30.000 --> 00:34:34.000 1GHz. Now, the fastest Pentium 4s 00:34:34.000 --> 00:34:39.000 that money can by today are, what, how many GHz? 00:34:39.000 --> 00:34:44.000 What's the fastest Pentium 4 you can buy today? 00:34:44.000 --> 00:34:47.000 What's that? Does anybody have a 4GHz 00:34:47.000 --> 00:34:51.000 Pentium 4 here? Oh, darn, you beat me. 00:34:51.000 --> 00:34:53.000 Anybody have a 3? 3GHz? 00:34:53.000 --> 00:34:57.000 A couple. So, I have a couple of 3GHz 00:34:57.000 --> 00:35:03.000 machines, and our lab has a whole ton of them. 00:35:03.000 --> 00:35:06.000 So, if Intel comes out with 4GHz machines today, 00:35:06.000 --> 00:35:11.000 they've been going up by about 1GHz roughly every year for the 00:35:11.000 --> 00:35:14.000 past couple of years. And, within three or four 00:35:14.000 --> 00:35:19.000 years, you're going to see chips, microprocessors that are 00:35:19.000 --> 00:35:22.000 in the 5-10GHz range, OK, assuming that all other 00:35:22.000 --> 00:35:26.000 things stay equal, which of course they're not, 00:35:26.000 --> 00:35:29.000 but just to give you some insight here, 00:35:29.000 --> 00:35:33.000 if I clock these guys and build circuits that are ten times 00:35:33.000 --> 00:35:37.000 faster, I very soon go up to 2.5kW, again as I said, 00:35:37.000 --> 00:35:42.000 all things being equal which they're not. 00:35:42.000 --> 00:35:46.000 But just to give you a sense, as I increase my frequency, 00:35:46.000 --> 00:35:49.000 so does the power consumed by the chip, OK? 00:35:49.000 --> 00:35:52.000 So, I really have to do something here. 00:35:52.000 --> 00:35:55.000 So, if I stare at this equation, CVS^2f, 00:35:55.000 --> 00:35:59.000 I want to increase f because people will buy computers if I 00:35:59.000 --> 00:36:03.000 have higher frequencies. And, Intel has managed to use 00:36:03.000 --> 00:36:07.000 its marketing campaigns to pretty much convince consumers 00:36:07.000 --> 00:36:12.000 that high frequencies are a good thing. 00:36:12.000 --> 00:36:15.000 OK, and whether they really mean anything or not, 00:36:15.000 --> 00:36:19.000 that's a different issue. So, we've got this huge power 00:36:19.000 --> 00:36:22.000 for assuming 5V, OK, so it turns out that 00:36:22.000 --> 00:36:25.000 microprocessors, as they come out, 00:36:25.000 --> 00:36:29.000 newer and newer versions run at lower and lower voltages. 00:36:29.000 --> 00:36:33.000 OK, they invent technologies that use lower and lower 00:36:33.000 --> 00:36:38.000 voltages, and go from VS 5V to, today, VS on the order of 1.5 00:36:38.000 --> 00:36:44.000 to 1V, somewhere in that range. So the moment you do that, 00:36:44.000 --> 00:36:47.000 you get a 25x reduction in power. 00:36:47.000 --> 00:36:51.000 OK, so in going from 2.5kW, you would now come down to 00:36:51.000 --> 00:36:56.000 something on the order of 100W, which is, again, 00:36:56.000 --> 00:37:00.000 much more reasonable, again, all other things being 00:37:00.000 --> 00:37:03.000 equal. It turns out that the 00:37:03.000 --> 00:37:07.000 capacitance of devices also changes as you go to smaller and 00:37:07.000 --> 00:37:10.000 smaller devices. And, 100W is also pretty high, 00:37:10.000 --> 00:37:13.000 and still not good enough for mobile computers. 00:37:13.000 --> 00:37:16.000 So, there are many, many other tricks that people 00:37:16.000 --> 00:37:20.000 use to get even lower powers. One trick is to play games with 00:37:20.000 --> 00:37:22.000 the clock. OK, what you do is, 00:37:22.000 --> 00:37:26.000 let's say for example in some computation you are not going to 00:37:26.000 --> 00:37:30.000 be using your floating point unit. 00:37:30.000 --> 00:37:33.000 Or let's say I'm going to be using your integer adder unit. 00:37:33.000 --> 00:37:37.000 OK, so what you can do is you can turn off the clock to those 00:37:37.000 --> 00:37:41.000 devices so that those devices do not even switch when they're not 00:37:41.000 --> 00:37:43.000 working. OK, if I turn off the clock to 00:37:43.000 --> 00:37:46.000 a device, the device isn't even going to switch, 00:37:46.000 --> 00:37:50.000 it's just going to sit there in limbo without consuming any 00:37:50.000 --> 00:37:52.000 power. It's equivalent to turning off 00:37:52.000 --> 00:37:55.000 both transistors. If you turn off both the PMOS 00:37:55.000 --> 00:37:58.000 and NMOS somehow, OK, it's not consuming any 00:37:58.000 --> 00:38:01.000 power. And by doing that, 00:38:01.000 --> 00:38:03.000 you can further cut down the power. 00:38:03.000 --> 00:38:06.000 So, if you can idle some of your function units, 00:38:06.000 --> 00:38:10.000 it's called idling a function unit, idle a function unit for, 00:38:10.000 --> 00:38:14.000 let's say, half the time. OK, you would cut down power by 00:38:14.000 --> 00:38:17.000 another factor of two. We can idle, 00:38:17.000 --> 00:38:19.000 then, 75% of the time, come down to 25W. 00:38:19.000 --> 00:38:23.000 So, those are the classes of tricks that people play. 00:38:23.000 --> 00:38:26.000 I'm going to stop here and allow the underground guide 00:38:26.000 --> 00:38:30.000 folks to do the survey. But, suffice it to say that the 00:38:30.000 --> 00:38:34.000 power discussion that I've gone through with you is a very high 00:38:34.000 --> 00:38:39.000 level discussion as to the real thing. 00:38:39.000 --> 00:38:41.000 In real life, what actually happens is that 00:38:41.000 --> 00:38:44.000 there is a fair amount of standby power even for CMOS 00:38:44.000 --> 00:38:46.000 logic. It turns out that although I 00:38:46.000 --> 00:38:50.000 don't have a path from VS to ground for my two transistors, 00:38:50.000 --> 00:38:53.000 it turns out that there are many leakage currents. 00:38:53.000 --> 00:38:57.000 OK, currents leak through all kinds of places through the 00:38:57.000 --> 00:38:59.000 drain of the inverter, and so on and so forth. 00:38:59.000 --> 00:39:03.000 And so, there is some standby power. 00:39:03.000 --> 00:39:06.000 So, let me show you a quick demo while, I guess, 00:39:06.000 --> 00:39:09.000 the review handouts are going around. 00:39:09.000 --> 00:39:13.000 And this shows the temperature of my CMOS inverter, 00:39:13.000 --> 00:39:17.000 and as I increase the frequency, you can just watch 00:39:17.000 --> 00:39:21.000 the temperature go up, and hopefully we'll blow this 00:39:21.000 --> 00:39:24.000 transistor. So, I'm increasing the 00:39:24.000 --> 00:39:29.000 frequency as you can see on the side here, and higher frequency 00:39:29.000 --> 00:39:33.000 implies more power consumption, more temperature, 00:39:33.000 --> 00:39:37.000 OK, and hopefully you will see some smoke coming out of, 00:39:37.000 --> 00:39:42.000 OK, I think I blew the inverter. 00:39:42.000 --> 00:39:46.000 So, the output is gone. So, it's at 110 degrees there, 00:39:46.000 --> 00:39:49.000 and that blew it. Sometimes we see smoke come 00:39:49.000 --> 00:39:54.000 out, but I guess today is not one of our lucky days. 00:39:54.000 --> 00:39:58.000 OK, so let me stop here and have the underground guide folks 00:39:58.000 --> 00:40:01.000 go through the reviews.