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Here's another approach to improving the latency
of our adder, this time focusing just on the
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carry logic.
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Early on in the course, we learned that by
going from a chain of logic gates to a tree
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of logic gates, we could go from a linear
latency to a logarithmic latency.
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Let's try to do that here.
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We'll start by rewriting the equations for
the carry-out from the full adder module.
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The final form of the rewritten equation has
two terms.
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The G, or generate, term is true when the
inputs will cause the module to generate a
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carry-out right away, without having to wait
for the carry-in to arrive.
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The P, or propagate, term is true if the module
will generate a carry-out only if there's
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a carry-in.
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So there only two ways to get a carry-out
from the module: it's either generated by
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the current module or the carry-in is propagated
from the previous module.
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Actually, it's usual to change the logic for
the P term from "A OR B" to "A XOR B".
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This doesn't change the truth table for the
carry-out but will allow us to express the
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sum output as "P XOR carry-in".
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Here's the schematic for the reorganized full
adder module.
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The little sum-of-products circuit for the
carry-out can be implemented using 3 2-input
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NAND gates, which is a bit more compact than
the implementation for the three product terms
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we suggested in Lab 2.
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Time to update your full adder circuit!
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Now consider two adjacent adder modules in
a larger adder circuit:
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we'll use the label H to refer to the high-order
module and the label L to refer to the low-order
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module.
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We can use the generate and propagate information
from each of the modules to develop equations
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for the carry-out from the pair of modules
treated as a single block.
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We'll generate a carry-out from the block
when a carry-out is generated by the H module,
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or when a carry-out is generated by the L
module and propagated by the H module.
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And we'll propagate the carry-in through the
block only if the L module propagates its
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carry-in to the intermediate carry-out and
H module propagates that to the final carry-out.
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So we have two simple equations requiring
only a couple of logic gates to implement.
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Let's use these equations to build a generate-propagate
(GP) module and hook it to the H and L modules
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as shown.
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The G and P outputs of the GP module tell
us under what conditions we'll get a carry-out
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from the two individual modules treated as
a single, larger block.
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We can use additional layers of GP modules
to build a tree of logic that computes the
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generate and propagate logic for adders with
any number of inputs.
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For an adder with N inputs, the tree will
contain a total of N-1 GP modules and have
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a latency that's order log(N).
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In the next step, we'll see how to use the
generate and propagate information to quickly
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compute the carry-in for each of the original
full adder modules.
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Once we're given the carry-in C_0 for the
low-order bit, we can hierarchically compute
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the carry-in for each full adder module.
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Given the carry-in to a block of adders, we
simply pass it along as the carry-in to the
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low-half of the block.
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The carry-in for the high-half of the block
is computed the using the generate and propagate
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information from the low-half of the block.
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We can use these equations to build a C module
and arrange the C modules in a tree as shown
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to use the C_0 carry-in to hierarchically
compute the carry-in to each layer of successively
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smaller blocks, until we finally reach the
full adder modules.
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For example, these equations show how C4 is
computed from C0, and C6 is computed from
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C4.
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Again the total propagation delay from the
arrival of the C_0 input to the carry-ins
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for each full adder is order log(N).
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Notice that the G_L and P_L inputs to a particular
C module are the same as two of the inputs
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to the GP module in the same position in the
GP tree.
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We can combine the GP module and C module
to form a single carry-lookahead module that
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passes generate and propagate information
up the tree and carry-in information down
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the tree.
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The schematic at the top shows how to wire
up the tree of carry-lookahead modules.
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And now we get to the payoff for all this
hard work!
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The combined propagation delay to hierarchically
compute the generate and propagate information
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on the way up and the carry-in information
on the way down is order log(N),
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which is then the latency for the entire adder
since computing the sum outputs only takes
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one additional XOR delay.
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This is a considerable improvement over the
order N latency of the ripple-carry adder.
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A final design note: we no longer need the
carry-out circuitry in the full adder module,
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so it can be removed.
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Variations on this generate-propagate strategy
form the basis for the fastest-known adder
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circuits.
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If you'd like to learn more, look up "Kogge-Stone
adders" on Wikipedia.