WEBVTT 00:00:01.040 --> 00:00:05.100 This discussion of design tradeoffs completes Part 1 of the course. 00:00:05.100 --> 00:00:08.420 We've covered a lot of ground in the last eight lectures. 00:00:08.420 --> 00:00:13.740 We started by looking at the mathematics underlying information theory and used it to help evaluate 00:00:13.740 --> 00:00:20.430 various alternative ways of effectively using sequences of bits to encode information content. 00:00:20.430 --> 00:00:25.430 Then we turned our attention to adding carefully-chosen redundancies to our encoding to ensure that 00:00:25.430 --> 00:00:30.580 we could detect and even correct errors that corrupted our bit-level encodings. 00:00:30.580 --> 00:00:35.660 Next we learned how analog signaling accumulates errors as we added processing elements to 00:00:35.660 --> 00:00:36.910 our system. 00:00:36.910 --> 00:00:41.870 We solved the problem by using voltages "digitally" choosing two ranges of voltages to encode 00:00:41.870 --> 00:00:44.370 the bit values 0 and 1. 00:00:44.370 --> 00:00:49.220 We had different signaling specifications for our outputs and inputs, adding noise margins 00:00:49.220 --> 00:00:52.170 to make our signaling more robust. 00:00:52.170 --> 00:00:56.670 Then we developed the static discipline for combinational devices and were led to the 00:00:56.670 --> 00:01:02.890 conclusion that our devices had to be non-linear and exhibit gains > 1. 00:01:02.890 --> 00:01:08.010 In our study of combinational logic, we fist learned about the MOSFET, a voltage-controlled 00:01:08.010 --> 00:01:09.110 switch. 00:01:09.110 --> 00:01:14.330 We developed a technique for using MOSFETS to build CMOS combinational logic gates, which 00:01:14.330 --> 00:01:17.750 met all the criteria of the static discipline. 00:01:17.750 --> 00:01:23.090 Then we discussed systematic ways of synthesizing larger combinational circuits that could implement 00:01:23.090 --> 00:01:28.490 any functionality we could express in the form a truth table. 00:01:28.490 --> 00:01:33.759 To be able to perform sequences of operations, we first developed a reliable bistable storage 00:01:33.759 --> 00:01:36.750 element based on a positive feedback loop. 00:01:36.750 --> 00:01:41.640 To ensure the storage elements worked correctly we imposed the dynamic discipline which required 00:01:41.640 --> 00:01:46.560 inputs to the storage elements to be stable just before and after the time the storage 00:01:46.560 --> 00:01:49.229 element was transitioned to "memory mode". 00:01:49.229 --> 00:01:54.600 We introduced finite-state machines as a useful abstraction for designing sequential logic. 00:01:54.600 --> 00:01:59.200 And then we figured out how to deal with asynchronous inputs in way that minimized the chance of 00:01:59.200 --> 00:02:03.729 incorrect operation due to metastability. 00:02:03.729 --> 00:02:08.179 In the last two lectures we developed latency and throughput as performance measures for 00:02:08.179 --> 00:02:14.980 digital systems and discussed ways of achieving maximum throughput under various constraints. 00:02:14.980 --> 00:02:20.450 We discussed how it's possible to make tradeoffs to achieve goals of minimizing power dissipation 00:02:20.450 --> 00:02:25.840 and increasing performance through decreased latency or increased throughput. 00:02:25.840 --> 00:02:26.989 Whew! 00:02:26.989 --> 00:02:31.760 That's a lot of information in a short amount of time. 00:02:31.760 --> 00:02:36.849 Mr. Blue and the rest of the 6.004x staff hope you've found the course useful in increasing 00:02:36.849 --> 00:02:41.879 your skills in designing digital systems and analyzing their operation. 00:02:41.879 --> 00:02:45.829 You've completed several actual designs and you're well on your way to designing a complete 00:02:45.829 --> 00:02:48.510 computer using our standard cell library. 00:02:48.510 --> 00:02:50.829 That's quite an accomplishment. 00:02:50.829 --> 00:02:54.849 If you'd like to continue the journey, please join us for Part 2 of the course where we'll 00:02:54.849 --> 00:03:01.019 discuss programmable architectures and work out the design of a modern 32-bit processor. 00:03:01.019 --> 00:03:01.560 See you then!