1
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Let’s try using the latch
as the memory component

2
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in our sequential logic system.

3
00:00:06,170 --> 00:00:08,790
To load the encoding of the
new state into the latch,

4
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we open the latch by setting
the latch’s gate input HIGH,

5
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letting the new value propagate
to the latch’s Q output,

6
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which represents
the current state.

7
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This updated value
propagates through

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the combinational logic,
updating the new state

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00:00:22,340 --> 00:00:23,740
information.

10
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Oops, if the gate
stays HIGH too long,

11
00:00:26,300 --> 00:00:29,210
we’ve created a loop in our
system and our plan to load

12
00:00:29,210 --> 00:00:33,100
the latch with new state goes
awry as the new state value

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starts to change rapidly as
information propagates around

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and around the loop.

15
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So to make this work, we need
to carefully time the interval

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when G is HIGH.

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It has to be long enough
to satisfy the constraints

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of the dynamic discipline,

19
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but it has to be short enough
that the latch closes again

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before the new state information
has a chance to propagate

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all the way around the loop.

22
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Hmm.

23
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I think Mr. Blue is right: this
sort of tricky system timing

24
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would likely be error-prone
since the exact timing

25
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of signals is almost
impossible to guarantee.

26
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We have upper and lower
bounds on the timing of signal

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transitions but no guarantees
of exact intervals.

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To make this work, we
want to a load signal

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that marks an instant in
time, not an interval.

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Here’s an analogy that will help
us understand what’s happening

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and what we can do about it.

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Imagine a line cars waiting
at a toll booth gate.

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The sequence of cars
represents the sequence

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of states in our
sequential logic

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and the gated toll both
represents the latch.

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Initially the gate is closed and
the cars are waiting patiently

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to go through the toll booth.

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When the gate
opens, the first car

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proceeds out of the toll both.

40
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But you can see that the timing
of when to close the gate

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is going to be tricky.

42
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It has to be open long
enough for the first car

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to make it through, but not too
long lest the other cars also

44
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make it through.

45
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This is exactly
the issue we faced

46
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with using the latch
as our memory component

47
00:02:02,190 --> 00:02:04,570
in our sequential logic.

48
00:02:04,570 --> 00:02:09,580
So how do we ensure only one car
makes it through the open gate?

49
00:02:09,580 --> 00:02:12,110
One solution is
to use TWO gates!

50
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Here’s the plan: Initially Gate
1 is open allowing exactly one

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00:02:16,550 --> 00:02:20,640
car to enter the toll
booth and Gate 2 is closed.

52
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Then at a particular
point in time,

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we close Gate 1
while opening Gate 2.

54
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This lets the car in the
toll booth proceed on,

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but prevents any other
car from passing through.

56
00:02:31,600 --> 00:02:33,620
We can repeat this
two-step process

57
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to deal with each
car one-at-time.

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The key is that at
no time is there

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a path through both gates.

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This is the same arrangement
as the escapement mechanism

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in a mechanical clock.

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The escapement ensures that the
gear attached to the clock’s

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spring only advances
one tooth at a time,

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preventing the spring from
spinning the gear wildly

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causing a whole day
to pass at once!

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If we observed the
toll booth’s output,

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we would see a car emerge
shortly after the instant

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in time when Gate 2 opens.

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00:03:07,360 --> 00:03:09,100
The next car would
emerge shortly

70
00:03:09,100 --> 00:03:12,900
after the next time
Gate 2 opens, and so on.

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Cars would proceed
through the toll booth

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at a rate set by the interval
between Gate 2 openings.

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00:03:19,180 --> 00:03:21,980
Let’s apply this solution
to design a memory component

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00:03:21,980 --> 00:03:24,410
for our sequential logic.

75
00:03:24,410 --> 00:03:26,940
Taking our cue from
the 2-gate toll both,

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we’ll design a new component,
called a D register,

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using two back-to-back latches.

78
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The load signal for a D
register is typically called

79
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the register’s “clock”, but the
register’s D input and Q output

80
00:03:38,970 --> 00:03:42,200
play the same roles as
they did for the latch.

81
00:03:42,200 --> 00:03:44,480
First we’ll describe the
internal structure of the D

82
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register, then we’ll describe
what it does and look in detail

83
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at how it does it.

84
00:03:50,470 --> 00:03:53,330
The D input is connected to
what we call the master latch

85
00:03:53,330 --> 00:03:57,670
and the Q output is
connected to the slave latch.

86
00:03:57,670 --> 00:04:00,720
Note that the clock signal is
inverted before it’s connected

87
00:04:00,720 --> 00:04:03,580
to the gate input
of the master latch.

88
00:04:03,580 --> 00:04:07,470
So when the master latch is
open, the slave is closed,

89
00:04:07,470 --> 00:04:08,710
and vice versa.

90
00:04:08,710 --> 00:04:11,620
This achieves the escapement
behavior we saw on the previous

91
00:04:11,620 --> 00:04:15,540
slide: at no time is there
active path from the register’s

92
00:04:15,540 --> 00:04:18,680
D input to the
register’s Q output.

93
00:04:18,680 --> 00:04:21,160
The delay introduced by the
inverter on the clock signal

94
00:04:21,160 --> 00:04:23,430
might give us cause for concern.

95
00:04:23,430 --> 00:04:26,720
When there’s a rising 0-to-1
transition on the clock signal,

96
00:04:26,720 --> 00:04:29,920
might there be a brief interval
when the gate signal is HIGH

97
00:04:29,920 --> 00:04:33,210
for both latches since there
will be a small delay before

98
00:04:33,210 --> 00:04:36,490
the inverter’s output
transitions from 1 to 0?

99
00:04:36,490 --> 00:04:39,070
Actually the inverter
isn’t necessary:

100
00:04:39,070 --> 00:04:42,150
Mr Blue is looking at a slightly
different latch schematic

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00:04:42,150 --> 00:04:44,280
where the latch is
open when G is LOW

102
00:04:44,280 --> 00:04:46,520
and closed when G is high.

103
00:04:46,520 --> 00:04:49,920
Just what we need
for the master latch!

104
00:04:49,920 --> 00:04:52,440
By the way, you’ll sometimes
hear a register called

105
00:04:52,440 --> 00:04:55,620
a flip-flop because of the
bistable nature of the positive

106
00:04:55,620 --> 00:04:58,710
feedback loops in the latches.

107
00:04:58,710 --> 00:05:01,200
That’s the internal
structure of the D register.

108
00:05:01,200 --> 00:05:04,160
In the next section we’ll
take a step-by-step tour

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00:05:04,160 --> 00:05:06,630
of the register in operation.