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Using a D register as
the memory component

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00:00:02,960 --> 00:00:05,695
in our sequential logic
system works great!

3
00:00:05,695 --> 00:00:07,070
At each rising
edge of the clock,

4
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the register loads
the new state,

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00:00:08,880 --> 00:00:11,280
which then appears at
the register’s output

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as the current state for the
rest of the clock period.

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00:00:15,070 --> 00:00:18,000
The combinational logic uses
the current state and the value

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00:00:18,000 --> 00:00:21,020
of the inputs to calculate
the next state and the values

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for the outputs.

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A sequence of rising
clock edges and inputs

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will produce a sequence
of states, which

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leads to a sequence of outputs.

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In the next chapter we’ll
introduce a new abstraction,

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finite state machines, that
will make it easy to design

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00:00:37,260 --> 00:00:39,490
sequential logic systems.

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00:00:39,490 --> 00:00:42,370
Let’s use the timing analysis
techniques we’ve learned

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00:00:42,370 --> 00:00:46,070
on the sequential logic
system shown here.

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The timing specifications for
the register and combinational

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00:00:49,100 --> 00:00:51,150
logic are as shown.

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Here are the questions
we need to answer.

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The contamination delay of
the combinational logic isn’t

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specified.

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What does it have to be
in order for the system

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to work correctly?

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Well, we know that the
sum of register and logic

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contamination delays
has to be greater

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than or equal to the hold
time of the register.

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Using the timing
parameters we do know along

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with a little
arithmetic tells us

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that the contamination
delay of the logic

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has to be at least 1ns.

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What is the minimum value
for the clock period tCLK?

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The second timing inequality
from the previous section

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tells us that tCLK
has be greater

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00:01:30,430 --> 00:01:33,530
than than the sum of the
register and logic propagation

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00:01:33,530 --> 00:01:37,140
delays plus the setup
time of the register.

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Using the known values
for these parameters

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gives us a minimum
clock period of 10ns.

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What are the timing constraints
for the Input signal

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relative to the rising
edge of the clock?

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00:01:50,460 --> 00:01:53,450
For this we’ll need a diagram!

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The Next State signal is
the input to the register

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so it has to meet the setup
and hold times as shown here.

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00:02:00,870 --> 00:02:03,330
Next we show the
Input signal and how

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the timing of its
transitions affect

46
00:02:05,240 --> 00:02:07,730
to the timing of the
Next State signal.

47
00:02:07,730 --> 00:02:10,680
Now it’s pretty easy to figure
out when Input has to be stable

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00:02:10,680 --> 00:02:15,360
before the rising clock edge,
i.e., the setup time for Input.

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00:02:15,360 --> 00:02:17,410
The setup time for
Input is the sum

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00:02:17,410 --> 00:02:19,510
of propagation
delay of the logic

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00:02:19,510 --> 00:02:22,280
plus the setup time
for the register, which

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we calculate as 7ns.

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00:02:25,570 --> 00:02:29,300
In other words, if the Input
signal is stable at least 7ns

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00:02:29,300 --> 00:02:32,820
before the rising clock edge,
then Next State will be stable

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00:02:32,820 --> 00:02:36,780
at least 2ns before the rising
clock edge and hence meet

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00:02:36,780 --> 00:02:40,840
the register’s
specified setup time.

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00:02:40,840 --> 00:02:43,410
Similarly, the
hold time of Input

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00:02:43,410 --> 00:02:45,890
has to be the hold
time of the register

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00:02:45,890 --> 00:02:49,030
minus the contamination
delay of the logic, which

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00:02:49,030 --> 00:02:52,560
we calculate as 1ns.

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00:02:52,560 --> 00:02:55,230
In other words, if Input
is stable at least 1ns

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after the rising clock
edge, then Next State

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will be stable for another
1ns, i.e., a total of 2ns

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00:03:01,950 --> 00:03:04,210
after the rising clock edge.

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00:03:04,210 --> 00:03:08,480
This meets the specified
hold time of the register.

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00:03:08,480 --> 00:03:11,900
This completes our introduction
to sequential logic.

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00:03:11,900 --> 00:03:13,810
Pretty much every
digital system out

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there is a sequential
logic system

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00:03:16,030 --> 00:03:19,060
and hence is obeying the
timing constraints imposed

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by the dynamic discipline.

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So next time you see an ad
for a 1.7 GHz processor chip,

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00:03:25,380 --> 00:03:28,850
you’ll know where
the “1.7” came from!