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The goal of this problem is
to design a reliable latch.

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A latch can be designed using
a multiplexor where the G

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input is used to
determine whether or not

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a new data value should
be loaded into the latch.

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The way the latch works is that
when G = 0, the old value of Q

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is fed back through
the multiplexor

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so it retains its old value.

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When G = 1, the multiplexor
selects D as the input

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so Q gets updated to
be the value of D.

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The logic function
that describes

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the operation of the latch is Q
= (NOT(G) AND Q) OR (G AND D).

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We want to build this
latch using only AND, OR,

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and inverter gates.

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We are given three proposed
designs for the latch.

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For each proposed
design, we want

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to specify whether the design
is BAD, GOOD, or OBESE.

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BAD means that the latch
does not work reliably.

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GOOD means that the
latch works reliably.

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OBESE means that the latch
works, but uses more gates

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than necessary.

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Latch proposal A is shown here.

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Taking a closer look
at this circuit,

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we see that the logic
function that it implements

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is Q = (G AND Q) OR D.

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This is not the correct
logic equation for a latch,

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so this design is BAD.

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Next, we take a look
at proposals B and C.

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The logic equation for proposal
B is Q = (NOT(G) AND Q)

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OR (G AND D)).

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This is exactly the
same logic equation

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that we specified for our latch.

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However, this implementation
is not lenient

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because it does not
guarantee that you will not

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see glitches on your output
signal when G changes value.

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Proposal C, however, includes
the same logic function

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Q = (NOT(G) AND Q) OR (G
AND D)) plus one more term

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which is OR (Q AND D).

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If you create a karnaugh map for
both of these logic functions,

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you see that the QD
term is redundant

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because it doesn't
add any additional 1's

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to the karnaugh map.

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This means that logically the
two functions are equivalent,

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but the effect of the
extra term is that it makes

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the implementation lenient.

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So Proposal C is the GOOD
proposal and B is BAD.