WEBVTT

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Well, we’ll need at least one
MOSFET to serve as the access

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FET so we can select which
bits will be affected by read

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and write operations.

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We can use a simple
capacitor for storage,

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where the value
of a stored bit is

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represented by voltage across
the plates of the capacitor.

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The resulting circuit is termed
a dynamic random-access memory

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(DRAM) cell.

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If the capacitor voltage
exceeds a certain threshold,

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we’re storing a “1” bit,
otherwise we’re storing a “0”.

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The amount of charge
on the capacitor,

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which determines the
speed and reliability

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of reading the stored
value, is proportional

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to the capacitance.

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We can increase the
capacitance by increasing

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the dielectric constant
of the insulating layer

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between the two plates of
the capacitor, increasing

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the area of the plates, or by
decreasing the the distance

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between the plates.

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All of these are
constantly being improved.

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A cross section of a modern
DRAM cell is shown here.

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The capacitor is formed
in a large trench

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dug into the substrate material
of the integrated circuit.

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Increasing the depth of the
trench will increase the area

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of the capacitor plates without
increasing the cell’s area.

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The wordline forms the gate
of the N-FET access transistor

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connecting the outer plate of
the capacitor to the bitline.

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A very thin insulating layer
separates the outer plate

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from the inner plate,
which is connected

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to some reference voltage
(shown as GND in this diagram).

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You can Google “trench
capacitor” to get the latest

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information on the
dimensions and materials used

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in the construction
of the capacitor.

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The resulting circuit is quite
compact: about 20-times less

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area/bit than an SRAM bit cell.

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There are some
challenges however.

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There’s no circuitry to main the
static charge on the capacitor,

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so stored charge will
leak from the outer plate

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of the capacitor, hence
the name “dynamic memory”.

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The leakage is caused by small
picoamp currents through the PN

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junction with the
surrounding substrate,

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or subthreshold conduction of
the access FET even when it’s

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turned “off”.

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This limits the amount of time
we can leave the capacitor

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unattended and still expect
to read the stored value.

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This means we’ll have to arrange
to read then re-write each bit

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cell (called a “refresh”
cycle) every 10ms or so, adding

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to the complexity of the
DRAM interface circuitry.

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DRAM write operations
are straightforward:

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simply turn on the access FET
with the wordline and charge

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or discharge the storage
capacitor through the bitline.

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Reads are bit more complicated.

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First the bitline is precharged
to some intermediate voltage,

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e.g., VDD/2, and then
the precharge circuitry

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is disconnected.

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The wordline is activated,
connecting the storage

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capacitor of the selected
cell to the bitline causing

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the charge on the
capacitor to be

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shared with the charge stored by
the capacitance of the bitline.

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If the value stored by the
cell capacitor is a “1”,

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the bitline voltage will
increase very slightly (e.g.,

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a few tens of millivolts).

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If the stored value is a
“0”, the bitline voltage will

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decrease slightly.

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Sense amplifiers are used
to detect this small voltage

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change to produce a
digital output value.

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This means that read operations
wipe out the information stored

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in the bit cell, which
must then be rewritten

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with the detected value at
the end of the read operation.

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DRAM circuitry is usually
organized to have “wide” rows,

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i.e., multiple consecutive
locations are read in a single

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access.

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This particular
block of locations

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is selected by the
DRAM row address.

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Then the DRAM column
address is used

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to select a particular location
from the block to be returned.

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If we want to read multiple
locations in a single row,

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then we only need to
send a new column address

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and the DRAM will respond
with that location

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without having to access
the bit cells again.

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The first access to a
row has a long latency,

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but subsequent accesses to the
same row have very low latency.

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As we’ll see, we’ll be able
to use fast column accesses

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to our advantage.

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In summary, DRAM bit cells
consist of a single access FET

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connected to a storage capacitor
that’s cleverly constructed

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to take up as little
area as possible.

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DRAMs must rewrite the contents
of bit cells after they are

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read and every cell must be
read and written periodically

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to ensure that the stored
charge is refreshed before it’s

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corrupted by leakage currents.

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DRAMs have much
higher capacities

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than SRAMs because of the small
size of the DRAM bit cells,

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but the complexity of the
DRAM interface circuitry

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means that the initial
access to a row of locations

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is quite a bit slower
than an SRAM access.

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However subsequent
accesses to the same row

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happen at speeds close
to that of SRAM accesses.

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Both SRAMs and DRAMs
will store values as long

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as their circuitry has power.

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But if the circuitry
is powered down,

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the stored bits will be lost.

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For long-term
storage we will need

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to use non-volatile memory
technologies, the topic

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of the next lecture segment.