WEBVTT

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We'll describe the operation of the FSM for
our combination lock using a state transition

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diagram.

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Initially, the FSM has received no bits of
the combination, a state we'll call SX.

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In the state transition diagram, states are
represented as circles, each labeled for now

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with a symbolic name chosen to remind us of
what history it represents.

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For this FSM, the unlock output U will be
a function of the current state, so we'll

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indicate the value of U inside the circle.

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Since in state SX we know nothing about past
input bits, the lock should stay locked and

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so U = 0.

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We'll indicate the initial state with a wide
border on the circle.

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We'll use the successive states to remember
what we've seen so far of the input combination.

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So if the FSM is in state SX and it receives
a 0 input, it should transition to state S0

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to remind us that we've seen the first bit
of the combination of 0-1-1-0.

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We use arrows to indicate transitions between
states and each arrow has a label telling

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us when that transition should occur.

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So this particular arrow is telling us that
when the FSM is in state SX and the next input

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is a 0, the FSM should transition to state
S0.

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Transitions are triggered by the rising edge
of the FSM's clock input.

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Let's add the states for the remainder of
the specified combination.

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The rightmost state, S0110, represents the
point at which the FSM has detected the specified

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sequence of inputs, so the unlock signal is
1 in this state.

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Looking at the state transition diagram, we
see that if the FSM starts in state SX, the

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input sequence 0-1-1-0 will leave the FSM
in state S0110.

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So far, so good.

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What should the FSM do if an input bit is
not the next bit in the combination?

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For example, if the FSM is in state SX and
the input bit is a 1, it still has not received

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any correct combination bits, so the next
state is SX again.

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Here are the appropriate non-combination transitions
for the other states.

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Note that an incorrect combination entry doesn't
necessarily take the FSM to state SX.

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For example, if the FSM is in state S0110,
the last four input bits have been 0-1-1-0.

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If the next input is a 1, then the last four
inputs bits are now 1-1-0-1, which won't lead

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to an open lock.

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But the last two bits might be the first two
bits of a valid combination sequence and so

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the FSM transitions to S01, indicating that
a sequence of 0-1 has been entered over the

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last two bits.

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We've been working with an FSM where the outputs
are function of the current state, called

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a Moore machine.

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Here the outputs are written inside the state
circle.

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If the outputs are a function of both the
current state and the current inputs, it's

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called a Mealy machine.

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Since the transitions are also a function
of the current state and current inputs, we'll

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label each transition with appropriate output
values using a slash to separate input values

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from output values.

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So, looking at the state transition diagram
on the right, suppose the FSM is in state

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S3.

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If the input is a 0, look for the arrow leaving
S3 labeled "0/".

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The value after the slash tells us the output
value, in this case 1.

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If the input had been a 1, the output value
would be 0.

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There are some simple rules we can use to
check that a state transition diagram is well

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formed.

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The transitions from a particular state must
be mutually exclusive, i.e., for a each state,

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there can't be more than one transition with
the same input label.

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This makes sense: if the FSM is to operate
consistently there can't be any ambiguity

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about the next state for a given current state
and input.

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By "consistently" we mean that the FSM should
make the same transitions if it's restarted

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at the same starting state and given the same
input sequences.

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Moreover, the transitions leaving each state
should be collectively exhaustive, i.e., there

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should a transition specified for each possible
input value.

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If we wish the FSM to stay in it's current
state for that particular input value, we

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need to show a transition from the current
state back to itself.

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With these rules there will be exactly one
transition selected for every combination

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of current state and input value.

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All the information in a state transition
diagram can be represented in tabular form

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as a truth table.

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The rows of the truth table list all the possible
combinations of current state and inputs.

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And the output columns of the truth table
tell us the next state and output value associated

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with each row.

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If we substitute binary values for the symbolic
state names, we end up with a truth table

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just like the ones we saw in Chapter 4.

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If we have K states in our state transition
diagram we'll need log_2(K) state bits, rounded

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up to the next integer since we don't have
fractional bits!

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In our example, we have a 5-state FSM, so
we'll need 3 state bits.

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We can assign the state encodings in any convenient
way, e.g., 000 for the first state, 001 for

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the second state, and so on.

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But the choice of state encodings can have
a big effect on the logic needed to implement

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the truth table.

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It's actually fun to figure out the state
encoding that produces the simplest possible

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logic.

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With a truth table in hand, we can use the
techniques from Chapter 4 to design logic

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circuits that implement the combinational
logic for the FSM.

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Of course, we can take the easy way out and
simply use a read-only memory to do the job!

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In this circuit, a read-only memory is used
to compute the next state and outputs from

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the current state and inputs.

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We're encoding the 5 states of the FSM using
a 3-bit binary value, so we have a 3-bit state

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register.

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The rectangle with the edge-triggered input
is schematic shorthand for a multi-bit register.

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If a wire in the diagram represents a multi-bit
signal, we use a little slash across the wire

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with a number to indicate how many bits are
in the signal.

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In this example, both current_state and next_state
are 3-bit signals.

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The read-only memory has a total of 4 input
signals - 3 for the current state and 1 for

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the input value -
so the read-only memory has 2^4 or 16 locations,

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which correspond to the 16 rows in the truth
table.

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Each location in the ROM supplies the output
values for a particular row of the truth table.

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Since we have 4 output signals - 3 for the
next state and 1 for the output value - each

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location supplies 4 bits of information.

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Memories are often annotated with their number
of locations and the number of bits in each

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location.

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So our memory is a 16-by-4 ROM: 16 locations
of 4-bits each.

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Of course, in order for the state registers
to work correctly, we need to ensure that

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the dynamic discipline is obeyed.

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We can use the timing analysis techniques
described at the end of Chapter 5 to check

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that this is so.

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For now, we'll assume that the timing of transitions
on the inputs are properly synchronized with

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the rising edges of the clock.

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So now we have the FSM abstraction to use
when designing the functionality of a sequential

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logic system, and a general-purpose circuit
implementation of the FSM using a ROM and

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a multi-bit state register.

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Recapping our design choices: the output bits
can be strictly a function of the current

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state (the FSM would then be called a Moore
machine),

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or they can be a function of both the current
state and current inputs, in which case the

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FSM is called a Mealy machine.

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We can choose the number of state bits - S
state bits will give us the ability to encode

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2^S possible states.

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Note that each extra state bit DOUBLES the
number of locations in the ROM!

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So when using ROMs to implement the necessary
logic, we're very interested in minimizing

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the number of state bits.

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The waveforms for our circuitry are pretty
straightforward.

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The rising edge of the clock triggers a transition
in the state register outputs.

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The ROM then does its thing, calculating the
next state, which becomes valid at some point

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in the clock cycle.

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This is the value that gets loaded into the
state registers at the next rising clock edge.

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This process repeats over-and-over as the
FSM follows the state transitions dictated

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by the state transition diagram.

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There are a few housekeeping details that
need our attention.

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On start-up we need some way to set the initial
contents of the state register to the correct

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encoding for the initial state.

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Many designs use a RESET signal that's set
to 1 to force some initial state and then

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set to 0 to start execution.

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We could adopt that approach here, using the
RESET signal to select an initial value to

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be loaded into the state register.

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In our example, we used a 3-bit state encoding
which would allow us to implement an FSM with

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up to 2^3 = 8 states.

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We're only using 5 of these encodings, which
means there are locations in the ROM we'll

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never access.

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If that's a concern, we can always use logic
gates to implement the necessary combinational

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logic instead of ROMs.

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Suppose the state register somehow got loaded
with one of the unused encodings?

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Well, that would be like being in a state
that's not listed in our state transition

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diagram.

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One way to defend against this problem is
design the ROM contents so that unused states

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always point to the initial state.

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In theory the problem should never arise,
but with this fix at least it won't lead to

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unknown behavior.

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We mentioned earlier the interesting problem
of finding a state encoding that minimized

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the combinational logic.

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There are computer-aided design tools to help
do this as part of the larger problem of finding

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minimal logic implementations for Boolean
functions.

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Mr. Blue is showing us another approach to
building the state register for the combination

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lock:
use a shift register to capture the last four

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input bits, then simply look at the recorded
history to determine if it matches the combination.

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No fancy next0state logic here!

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Finally, we still have to address the problem
of ensuring that input transitions don't violate

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the dynamic discipline for the state register.

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We'll get to this in the last section of this
chapter.