1 00:00:01,310 --> 00:00:06,100 Okay, now that we understand how to build combinational logic gates using CMOS, let's 2 00:00:06,100 --> 00:00:10,510 turn our attention to the timing specifications for the gates. 3 00:00:10,510 --> 00:00:15,440 Here's a simple circuit consisting of two CMOS inverters connected in series, which 4 00:00:15,440 --> 00:00:20,340 we'll use to understand how to characterize the timing of the inverter on the left. 5 00:00:20,340 --> 00:00:24,890 It will be helpful to build an electrical model of what happens when we change V_IN, 6 00:00:24,890 --> 00:00:29,050 the voltage on the input to the left inverter. 7 00:00:29,050 --> 00:00:34,520 If V_IN makes a transition from a digital 0 to a digital 1, the PFET switch in the pullup 8 00:00:34,520 --> 00:00:40,180 turns off and the NFET switch in pulldown turns on, connecting the output node of the 9 00:00:40,180 --> 00:00:43,300 left inverter to GROUND. 10 00:00:43,300 --> 00:00:47,580 The electrical model for this node includes the distributed resistance and capacitance 11 00:00:47,580 --> 00:00:52,170 of the physical wire connecting the output of the left inverter to the input of the right 12 00:00:52,170 --> 00:00:53,450 inverter. 13 00:00:53,450 --> 00:00:57,960 And there is also capacitance associated with the gate terminals of the MOSFETs in the right 14 00:00:57,960 --> 00:00:59,960 inverter. 15 00:00:59,960 --> 00:01:04,959 When the output node is connected to GROUND, the charge on this capacitance will flow towards 16 00:01:04,959 --> 00:01:09,390 the GROUND connection through the resistance of the wire and the resistance of the conducting 17 00:01:09,390 --> 00:01:12,690 channel of the NFET pulldown switch. 18 00:01:12,690 --> 00:01:18,520 Eventually the voltage on the wire will reach the potential of the GROUND connection, 0V. 19 00:01:18,520 --> 00:01:23,819 The process is much the same for falling transitions on V_IN, which cause the output node to charge 20 00:01:23,819 --> 00:01:26,820 up to V_DD. 21 00:01:26,820 --> 00:01:30,569 Now let's look at the voltage waveforms as a function of time. 22 00:01:30,569 --> 00:01:37,380 The top plot shows both a rising and, later, a falling transition for V_IN. 23 00:01:37,380 --> 00:01:43,060 We see that the output waveform has the characteristic exponential shape for the voltage of a capacitor 24 00:01:43,060 --> 00:01:46,908 being discharged or charged though a resistor. 25 00:01:46,908 --> 00:01:52,649 The exponential is characterized by its associated R-C time constant, where, in this case, the 26 00:01:52,649 --> 00:01:58,689 R is the net resistance of the wire and MOSFET channel, and the C is the net capacitance 27 00:01:58,689 --> 00:02:02,729 of the wire and MOSFET gate terminals. 28 00:02:02,729 --> 00:02:07,670 Since neither the input nor output transition is instantaneous, we have some choices to 29 00:02:07,670 --> 00:02:11,140 make about how to measure the inverter's propagation delay. 30 00:02:11,140 --> 00:02:17,510 Happily, we have just the guidance we need from our signaling thresholds! 31 00:02:17,510 --> 00:02:22,000 The propagation delay of a combinational logic gate is defined to be an upper bound on the 32 00:02:22,000 --> 00:02:25,820 delay from valid inputs to valid outputs. 33 00:02:25,820 --> 00:02:31,650 Valid input voltages are defined by the V_IL and V_IH signaling thresholds, and valid output 34 00:02:31,650 --> 00:02:36,310 voltages are defined by the V_OL and V_OH signaling thresholds. 35 00:02:36,310 --> 00:02:40,290 We've shown these thresholds on the waveform plots. 36 00:02:40,290 --> 00:02:45,079 To measure the delay associated with the rising transition on V_IN, first identify the time 37 00:02:45,079 --> 00:02:51,920 when the input becomes a valid digital 1, i.e., the time at which V_IN crosses the V_IH 38 00:02:51,920 --> 00:02:53,190 threshold. 39 00:02:53,190 --> 00:02:59,180 Next identify the time when the output becomes a valid digital 0, i.e., the time at which 40 00:02:59,180 --> 00:03:02,310 V_OUT crosses the V_OL threshold. 41 00:03:02,310 --> 00:03:06,829 The interval between these two time points is the delay for this particular set of input 42 00:03:06,829 --> 00:03:09,680 and output transitions. 43 00:03:09,680 --> 00:03:13,790 We can go through the same process to measure the delay associated with a falling input 44 00:03:13,790 --> 00:03:14,790 transition. 45 00:03:14,790 --> 00:03:19,910 First, identify the time at which V_IN cross the V_IL threshold. 46 00:03:19,910 --> 00:03:24,599 Then find the time at which V_OUT crosses the V_OH threshold. 47 00:03:24,599 --> 00:03:28,060 The resulting interval is the delay we wanted to measure. 48 00:03:28,060 --> 00:03:35,129 Since the propagation delay, t_PD, is an upper bound on the delay associated with *any* input 49 00:03:35,129 --> 00:03:39,980 transition, we'll choose a value for t_PD that's greater than or equal to the measurements 50 00:03:39,980 --> 00:03:41,939 we just made. 51 00:03:41,939 --> 00:03:48,409 When a manufacturer selects the t_PD specification for a gate, it must take into account manufacturing 52 00:03:48,409 --> 00:03:53,620 variations, the effects of different environmental conditions such as temperature and power-supply 53 00:03:53,620 --> 00:03:55,579 voltage, and so on. 54 00:03:55,579 --> 00:04:00,739 It should choose a t_PD that will be an upper bound on any delay measurements their customers 55 00:04:00,739 --> 00:04:04,620 might make on actual devices. 56 00:04:04,620 --> 00:04:08,310 From the designer's point of view, we can rely on this upper bound for each component 57 00:04:08,310 --> 00:04:13,950 of a larger digital system and use it to calculate the system's t_PD without having to repeat 58 00:04:13,950 --> 00:04:17,690 all the manufacturer's measurements. 59 00:04:17,690 --> 00:04:22,130 If our goal is to minimize the propagation delay of our system, then we'll want to keep 60 00:04:22,130 --> 00:04:26,430 the capacitances and resistances as small as possible. 61 00:04:26,430 --> 00:04:31,120 There's an interesting tension here: to make the effective resistance of a MOSFET switch 62 00:04:31,120 --> 00:04:34,740 smaller, we would increase its width. 63 00:04:34,740 --> 00:04:39,270 But that would add additional capacitance to the switch's gate terminal, slowing down 64 00:04:39,270 --> 00:04:43,120 transitions on the input node that connects to the gate! 65 00:04:43,120 --> 00:04:47,870 It's a fun optimization problem to figure out transistor sizing that minimizes the overall 66 00:04:47,870 --> 00:04:50,930 propagation delay. 67 00:04:50,930 --> 00:04:55,630 Although not strictly required by the static discipline, it will be useful to define another 68 00:04:55,630 --> 00:04:59,789 timing specification, called the "contamination delay". 69 00:04:59,789 --> 00:05:04,720 It measures how long a gate's previous output value remains valid after the gate's inputs 70 00:05:04,720 --> 00:05:07,530 start to change and become invalid. 71 00:05:07,530 --> 00:05:12,690 Technically, the contamination delay will be a lower bound on the delay from an invalid 72 00:05:12,690 --> 00:05:15,920 input to an invalid output. 73 00:05:15,920 --> 00:05:19,620 We'll make the delay measurements much as we did for the propagation delay. 74 00:05:19,620 --> 00:05:25,180 On a rising input transition, the delay starts when the input is no longer a valid digital 75 00:05:25,180 --> 00:05:29,600 0, i.e., when V_IN crosses the V_IL threshold. 76 00:05:29,600 --> 00:05:36,360 And the delay ends when the output becomes invalid, i.e., when V_OUT crosses the V_OH 77 00:05:36,360 --> 00:05:37,360 threshold. 78 00:05:37,360 --> 00:05:42,740 We can make a similar delay measurement for the falling input transition. 79 00:05:42,740 --> 00:05:47,610 Since the contamination delay, t_CD, is a lower bound on the delay associated with *any* 80 00:05:47,610 --> 00:05:52,979 input transition, we'll choose a value for t_CD that's less than or equal to the measurements 81 00:05:52,979 --> 00:05:55,860 we just made. 82 00:05:55,860 --> 00:05:59,460 Do we really need the contamination delay specification? 83 00:05:59,460 --> 00:06:00,970 Usually not. 84 00:06:00,970 --> 00:06:06,200 And if not's specified, designers should assume that the t_CD for a combinational device is 85 00:06:06,200 --> 00:06:07,830 0. 86 00:06:07,830 --> 00:06:12,039 In other words a conservative assumption is that the outputs go invalid as soon as the 87 00:06:12,039 --> 00:06:13,750 inputs go invalid. 88 00:06:13,750 --> 00:06:19,830 By the way, manufacturers often use the term "minimum propagation delay" to refer to a 89 00:06:19,830 --> 00:06:22,770 device's contamination delay. 90 00:06:22,770 --> 00:06:26,340 That terminology is a bit confusing, but now you know what it is they're trying to tell 91 00:06:26,340 --> 00:06:28,520 you. 92 00:06:28,520 --> 00:06:33,479 So here's a quick summary of the timing specifications for combinational logic. 93 00:06:33,479 --> 00:06:38,500 These specifications tell us how the timing of changes in the output waveform (labeled 94 00:06:38,500 --> 00:06:43,180 B in this example) are related to the timing of changes in the input waveform (labeled 95 00:06:43,180 --> 00:06:44,180 A). 96 00:06:44,180 --> 00:06:49,870 A combinational device may retain its previous output value for some interval of time after 97 00:06:49,870 --> 00:06:51,780 an input transition. 98 00:06:51,780 --> 00:06:56,610 The contamination delay of the device is a guarantee on the minimum size of that interval, 99 00:06:56,610 --> 00:07:03,030 i.e., t_CD is a lower bound on how long the old output value stays valid. 100 00:07:03,030 --> 00:07:08,090 As stated in Note 2, a conservative assumption is that the contamination delay of a device 101 00:07:08,090 --> 00:07:13,680 is 0, meaning the device's output may change immediately after an input transition. 102 00:07:13,680 --> 00:07:19,860 So t_CD gives us information on when B will start to change. 103 00:07:19,860 --> 00:07:24,759 Similarly, it would be good to know when B is guaranteed to be done changing after an 104 00:07:24,759 --> 00:07:26,660 input transition. 105 00:07:26,660 --> 00:07:30,880 In other words, how long do we have to wait for a change in the inputs to reflected in 106 00:07:30,880 --> 00:07:34,080 an updated value on the outputs? 107 00:07:34,080 --> 00:07:39,379 This is what t_PD tells us since it is a upper bound on the time it takes for B to become 108 00:07:39,379 --> 00:07:43,409 valid and stable after an input transition. 109 00:07:43,409 --> 00:07:48,611 As Note 1 points out, in general there are no guarantees on the behavior of the output 110 00:07:48,611 --> 00:07:54,930 in the interval after t_CD and before t_PD, as measured from the input transition. 111 00:07:54,930 --> 00:07:59,610 It would legal for the B output to change several times in that interval, or even have 112 00:07:59,610 --> 00:08:02,889 a non-digital voltage for any part of the interval. 113 00:08:02,889 --> 00:08:08,699 As we'll see in the last video of this chapter, we'll be able to offer more insights into 114 00:08:08,699 --> 00:08:13,090 B's behavior in this interval for a subclass of combinational devices. 115 00:08:13,090 --> 00:08:17,319 But in general, a designer should make no assumptions about B's value in the interval 116 00:08:17,319 --> 00:08:21,250 between t_CD and t_PD. 117 00:08:21,250 --> 00:08:26,400 How do we calculate the propagation and contamination delays of a larger combinational circuit from 118 00:08:26,400 --> 00:08:29,260 the timing specifications of its components? 119 00:08:29,260 --> 00:08:37,700 Our example is a circuit of four NAND gates where each NAND has a t_PD of 4 ns and t_CD 120 00:08:37,700 --> 00:08:39,049 of 1 ns. 121 00:08:39,049 --> 00:08:43,549 To find the propagation delay for the larger circuit, we need to find the maximum delay 122 00:08:43,549 --> 00:08:49,481 from an input transition on nodes A, B, or C to a valid and stable value on the output 123 00:08:49,481 --> 00:08:51,220 Y. 124 00:08:51,220 --> 00:08:57,240 To do this, consider each possible path from one of the inputs to Y and compute the path 125 00:08:57,240 --> 00:09:02,070 delay by summing the t_PDs of the components along the path. 126 00:09:02,070 --> 00:09:06,610 Choose the largest such path delay as the t_PD of the overall circuit. 127 00:09:06,610 --> 00:09:12,620 In our example, the largest delay is a path that includes three NAND gates, with a cumulative 128 00:09:12,620 --> 00:09:15,890 propagation delay of 12 ns. 129 00:09:15,890 --> 00:09:21,760 In other words, the output Y is guaranteed be stable and valid within 12 ns of a transition 130 00:09:21,760 --> 00:09:27,800 on A, B, or C. To find the contamination delay for the larger 131 00:09:27,800 --> 00:09:32,550 circuit, we again investigate all paths from inputs to outputs, but this time we're looking 132 00:09:32,550 --> 00:09:37,300 for the shortest path from an invalid input to an invalid output. 133 00:09:37,300 --> 00:09:42,430 So we sum the t_CDs of the components along each path and choose the smallest such path 134 00:09:42,430 --> 00:09:46,370 delay as the t_CD of the overall circuit. 135 00:09:46,370 --> 00:09:51,810 In our example, the smallest delay is a path that includes two NAND gates with a cumulative 136 00:09:51,810 --> 00:09:55,190 contamination delay of 2 ns. 137 00:09:55,190 --> 00:10:00,740 In other words, the output Y will retain its previous value for at least 2 ns after one 138 00:10:00,740 --> 00:10:02,470 of the inputs goes invalid.