1 00:00:01,069 --> 00:00:05,880 Let's review our wish list for the characteristics of a combinational device. 2 00:00:05,880 --> 00:00:09,820 In the previous lecture we worked hard to develop a voltage-based representation for 3 00:00:09,820 --> 00:00:14,710 information that could tolerate some amount error as the information flowed through a 4 00:00:14,710 --> 00:00:17,340 system of processing elements. 5 00:00:17,340 --> 00:00:23,029 We specified four signaling thresholds: V_OL and V_OH set the upper and lower bounds on 6 00:00:23,029 --> 00:00:29,320 voltages used to represent 0 and 1 respectively at the outputs of a combinational device. 7 00:00:29,320 --> 00:00:35,480 V_IL and V_IH served a similar role for interpreting the voltages at the inputs of a combinational 8 00:00:35,480 --> 00:00:36,780 device. 9 00:00:36,780 --> 00:00:42,930 We specified that V_OL be strictly less than V_IL, and termed the difference between these 10 00:00:42,930 --> 00:00:47,710 two low thresholds as the low noise margin, the amount of noise that could be added to 11 00:00:47,710 --> 00:00:53,539 an output signal and still have the signal interpreted correctly at any connected inputs. 12 00:00:53,539 --> 00:01:00,390 For the same reasons we specified that V_IH be strictly less than V_OH. 13 00:01:00,390 --> 00:01:04,430 We saw the implications of including noise margins when we looked at the voltage transfer 14 00:01:04,430 --> 00:01:10,659 characteristic - a plot of V_OUT vs. V_IN - for a combinational device. 15 00:01:10,659 --> 00:01:15,250 Since a combinational device must, in the steady state, produce a valid output voltage 16 00:01:15,250 --> 00:01:21,590 given a valid input voltage, we can identify forbidden regions in the VTC, which for valid 17 00:01:21,590 --> 00:01:26,110 input voltages identify regions of invalid output voltages. 18 00:01:26,110 --> 00:01:31,299 The VTC for a legal combinational device could not have any points that fall within these 19 00:01:31,299 --> 00:01:32,619 regions. 20 00:01:32,619 --> 00:01:38,299 The center region, bounded by the four threshold voltages, is narrower than it is high and 21 00:01:38,299 --> 00:01:43,939 so any legal VTC has to a have region where its gain is greater than 1 and the overall 22 00:01:43,939 --> 00:01:46,740 VTC has to be non-linear. 23 00:01:46,740 --> 00:01:53,090 The VTC shown here is that for a combinational device that serves as an inverter. 24 00:01:53,090 --> 00:01:58,430 If we're fortunate to be using a circuit technology that provides high gain and has output voltages 25 00:01:58,430 --> 00:02:04,259 close the ground and the power supply voltage, we can push V_OL and V_OH outward towards 26 00:02:04,259 --> 00:02:10,470 the power supply rails, and push V_IL and V_IH inward, with the happy consequence of 27 00:02:10,470 --> 00:02:14,750 increasing the noise margins - always a good thing! 28 00:02:14,750 --> 00:02:19,030 Remembering back to the beginning of Lecture 2, we'll be wanting billions of devices in 29 00:02:19,030 --> 00:02:24,470 our digital systems, so each device will have to be quite inexpensive and small. 30 00:02:24,470 --> 00:02:28,920 In today's mobile world, the ability to run our systems on battery power for long periods 31 00:02:28,920 --> 00:02:33,829 of time means that we'll want to have our systems dissipate as little power as possible. 32 00:02:33,829 --> 00:02:39,829 Of course, manipulating information will necessitate changing voltages within the system and that 33 00:02:39,829 --> 00:02:42,110 will cost us some amount of power. 34 00:02:42,110 --> 00:02:46,911 But if our system is idle and no internal voltages are changing, we'd like for our system 35 00:02:46,911 --> 00:02:49,600 to have zero power dissipation. 36 00:02:49,600 --> 00:02:54,630 Finally, we'll want to be able to implement systems with useful functionality and so need 37 00:02:54,630 --> 00:03:00,010 to develop a catalog of the logic computations we want to perform. 38 00:03:00,010 --> 00:03:04,540 Quite remarkably, there is a circuit technology that will make our wishes come true! 39 00:03:04,540 --> 00:03:07,620 That technology is the subject of this lecture. 40 00:03:07,620 --> 00:03:14,760 The star of our show is the metal-oxide-semiconductor field-effect transistor, or MOSFET for short. 41 00:03:14,760 --> 00:03:19,650 Here's a 3D drawing showing a cross-section of a MOSFET, which is constructed from a complicated 42 00:03:19,650 --> 00:03:23,760 sandwich of electrical materials as part of an integrated circuit, 43 00:03:23,760 --> 00:03:28,760 so called because the individual devices in an integrated circuit are manufactured en-masse 44 00:03:28,760 --> 00:03:32,170 during a series of manufacturing steps. 45 00:03:32,170 --> 00:03:36,870 In modern technologies the dimensions of the block shown here are a few 10's of nanometers 46 00:03:36,870 --> 00:03:42,380 on a side - that's 1/1000 of the thickness of a thin human hair. 47 00:03:42,380 --> 00:03:47,930 This dimension is so small that MOSFETs can't be viewed using an ordinary optical microscope, 48 00:03:47,930 --> 00:03:56,120 whose resolution is limited by the wavelength of visible light, which is 400 to 750nm. 49 00:03:56,120 --> 00:04:00,430 For many years, engineers have been able to shrink the device dimensions by a factor of 50 00:04:00,430 --> 00:04:05,681 2 every 24 months or so, an observation known as "Moore's Law" after 51 00:04:05,681 --> 00:04:12,010 Gordon Moore, one of the founders of Intel, who first remarked on this trend in 1965. 52 00:04:12,010 --> 00:04:17,260 Each 50% shrink in dimensions enables integrated circuit (IC) manufacturers to build four times 53 00:04:17,260 --> 00:04:22,970 as many devices in the same area as before, and, as we'll see, the devices themselves 54 00:04:22,970 --> 00:04:24,320 get faster too! 55 00:04:24,320 --> 00:04:31,790 An integrated circuit in 1975 might have had 2500 devices; today we're able to build ICs 56 00:04:31,790 --> 00:04:34,690 with two to three billion devices. 57 00:04:34,690 --> 00:04:37,409 Here's a quick tour of what we see in the diagram. 58 00:04:37,409 --> 00:04:42,210 The substrate upon which the IC is built is a thin wafer of silicon crystal which has 59 00:04:42,210 --> 00:04:45,250 had impurities added to make it conductive. 60 00:04:45,250 --> 00:04:50,470 In this case the impurity was an acceptor atom like Boron, and we characterize the doped 61 00:04:50,470 --> 00:04:53,680 silicon as a p-type semiconductor. 62 00:04:53,680 --> 00:04:59,020 The IC will include an electrical contact to the p-type substrate, called the "bulk" 63 00:04:59,020 --> 00:05:01,540 terminal, so we can control its voltage. 64 00:05:01,540 --> 00:05:06,260 When want to provide electrical insulation between conducting materials, we'll use a 65 00:05:06,260 --> 00:05:08,630 layer of silicon dioxide (SiO2). 66 00:05:08,630 --> 00:05:13,160 Normally the thickness of the insulator isn't terribly important, except for when it's used 67 00:05:13,160 --> 00:05:18,030 to isolate the gate of the transistor (shown here in red) from the substrate. 68 00:05:18,030 --> 00:05:23,030 The insulating layer in that region is very thin so that the electrical field from charges 69 00:05:23,030 --> 00:05:26,560 on the gate conductor can easily affect the substrate. 70 00:05:26,560 --> 00:05:32,310 The gate terminal of the transistor is a conductor, in this case, polycrystalline silicon. 71 00:05:32,310 --> 00:05:38,200 The gate, the thin oxide insulating layer, and the p-type substrate form a capacitor, 72 00:05:38,200 --> 00:05:42,760 where changing the voltage on the gate will cause electrical changes in the p-type substrate 73 00:05:42,760 --> 00:05:44,800 directly under the gate. 74 00:05:44,800 --> 00:05:52,920 In early manufacturing processes the gate terminal was made of metal, and the term "metal-oxide-semiconductor" 75 00:05:52,920 --> 00:05:57,070 (MOS) is referring to this particular structure. 76 00:05:57,070 --> 00:06:02,410 After the gate terminal is in place, donor atoms such as Phosphorous are implanted into 77 00:06:02,410 --> 00:06:07,360 the p-type substrate in two rectangular regions on either side of the gate. 78 00:06:07,360 --> 00:06:13,460 This changes those regions to an n-type semiconductor, which become the final two terminals of the 79 00:06:13,460 --> 00:06:16,980 MOSFET, called the source and the drain. 80 00:06:16,980 --> 00:06:21,110 Note that source and drain are usually physically identical and are distinguished by the role 81 00:06:21,110 --> 00:06:25,070 they play during the operation of the device, our next topic. 82 00:06:25,070 --> 00:06:30,070 As we'll see in the next slide, the MOSFET functions as a voltage-controlled switch connecting 83 00:06:30,070 --> 00:06:33,150 the source and drain terminals of the device. 84 00:06:33,150 --> 00:06:37,120 When the switch is conducting, current will flow from the drain to the source through 85 00:06:37,120 --> 00:06:41,720 the conducting channel formed as the second plate of the gate capacitor. 86 00:06:41,720 --> 00:06:46,880 The MOSFET has two critical dimensions: its length L, which measures the distance the 87 00:06:46,880 --> 00:06:52,320 current must cross as it flows from drain to source, and its width W, which determines 88 00:06:52,320 --> 00:06:55,920 how much channel is available to conduct current. 89 00:06:55,920 --> 00:07:00,430 The the current, termed I_DS, flowing across the switch is proportional to the ratio of 90 00:07:00,430 --> 00:07:03,060 the channel's width to its length. 91 00:07:03,060 --> 00:07:07,760 Typically, IC designers make the length as short as possible. 92 00:07:07,760 --> 00:07:14,760 When a news article refers to a "14nm process," the 14nm refers to the smallest allowable 93 00:07:14,760 --> 00:07:17,480 value for the channel length. 94 00:07:17,480 --> 00:07:21,760 And designers choose the channel width to set the desired amount of current flow. 95 00:07:21,760 --> 00:07:27,090 If I_DS is large, voltage transitions on the source and drain nodes will be quick, at the 96 00:07:27,090 --> 00:07:29,770 cost of a physically larger device. 97 00:07:29,770 --> 00:07:37,220 To summarize: the MOSFET has four electrical terminals: bulk, gate, source, and drain. 98 00:07:37,220 --> 00:07:42,460 Two of the device dimensions are under the control of the designer: the channel length, 99 00:07:42,460 --> 00:07:47,800 usually chosen to be as small as possible, and the channel width chosen to set the current 100 00:07:47,800 --> 00:07:49,570 flow to the desired value. 101 00:07:49,570 --> 00:07:55,240 It's a solid-state switch - there are no moving parts - and the switch operation is controlled 102 00:07:55,240 --> 00:07:59,310 by electrical fields determined by the relative voltages of the four terminals.