1 00:00:01,449 --> 00:00:06,529 We'll describe the operation of the FSM for our combination lock using a state transition 2 00:00:06,529 --> 00:00:07,540 diagram. 3 00:00:07,540 --> 00:00:14,170 Initially, the FSM has received no bits of the combination, a state we'll call SX. 4 00:00:14,170 --> 00:00:18,800 In the state transition diagram, states are represented as circles, each labeled for now 5 00:00:18,800 --> 00:00:23,600 with a symbolic name chosen to remind us of what history it represents. 6 00:00:23,600 --> 00:00:30,321 For this FSM, the unlock output U will be a function of the current state, so we'll 7 00:00:30,321 --> 00:00:33,730 indicate the value of U inside the circle. 8 00:00:33,730 --> 00:00:38,980 Since in state SX we know nothing about past input bits, the lock should stay locked and 9 00:00:38,980 --> 00:00:41,620 so U = 0. 10 00:00:41,620 --> 00:00:46,930 We'll indicate the initial state with a wide border on the circle. 11 00:00:46,930 --> 00:00:52,350 We'll use the successive states to remember what we've seen so far of the input combination. 12 00:00:52,350 --> 00:00:59,320 So if the FSM is in state SX and it receives a 0 input, it should transition to state S0 13 00:00:59,320 --> 00:01:05,250 to remind us that we've seen the first bit of the combination of 0-1-1-0. 14 00:01:05,250 --> 00:01:09,880 We use arrows to indicate transitions between states and each arrow has a label telling 15 00:01:09,880 --> 00:01:12,049 us when that transition should occur. 16 00:01:12,049 --> 00:01:18,289 So this particular arrow is telling us that when the FSM is in state SX and the next input 17 00:01:18,289 --> 00:01:23,908 is a 0, the FSM should transition to state S0. 18 00:01:23,908 --> 00:01:28,450 Transitions are triggered by the rising edge of the FSM's clock input. 19 00:01:28,450 --> 00:01:32,310 Let's add the states for the remainder of the specified combination. 20 00:01:32,310 --> 00:01:38,850 The rightmost state, S0110, represents the point at which the FSM has detected the specified 21 00:01:38,850 --> 00:01:44,149 sequence of inputs, so the unlock signal is 1 in this state. 22 00:01:44,149 --> 00:01:50,529 Looking at the state transition diagram, we see that if the FSM starts in state SX, the 23 00:01:50,529 --> 00:01:57,348 input sequence 0-1-1-0 will leave the FSM in state S0110. 24 00:01:57,348 --> 00:01:59,130 So far, so good. 25 00:01:59,130 --> 00:02:03,719 What should the FSM do if an input bit is not the next bit in the combination? 26 00:02:03,719 --> 00:02:09,978 For example, if the FSM is in state SX and the input bit is a 1, it still has not received 27 00:02:09,978 --> 00:02:15,629 any correct combination bits, so the next state is SX again. 28 00:02:15,629 --> 00:02:20,239 Here are the appropriate non-combination transitions for the other states. 29 00:02:20,239 --> 00:02:26,739 Note that an incorrect combination entry doesn't necessarily take the FSM to state SX. 30 00:02:26,739 --> 00:02:36,200 For example, if the FSM is in state S0110, the last four input bits have been 0-1-1-0. 31 00:02:36,200 --> 00:02:42,870 If the next input is a 1, then the last four inputs bits are now 1-1-0-1, which won't lead 32 00:02:42,870 --> 00:02:44,849 to an open lock. 33 00:02:44,849 --> 00:02:50,689 But the last two bits might be the first two bits of a valid combination sequence and so 34 00:02:50,689 --> 00:02:57,010 the FSM transitions to S01, indicating that a sequence of 0-1 has been entered over the 35 00:02:57,010 --> 00:02:59,390 last two bits. 36 00:02:59,390 --> 00:03:03,909 We've been working with an FSM where the outputs are function of the current state, called 37 00:03:03,909 --> 00:03:05,629 a Moore machine. 38 00:03:05,629 --> 00:03:09,439 Here the outputs are written inside the state circle. 39 00:03:09,439 --> 00:03:13,400 If the outputs are a function of both the current state and the current inputs, it's 40 00:03:13,400 --> 00:03:14,890 called a Mealy machine. 41 00:03:14,890 --> 00:03:19,880 Since the transitions are also a function of the current state and current inputs, we'll 42 00:03:19,880 --> 00:03:25,469 label each transition with appropriate output values using a slash to separate input values 43 00:03:25,469 --> 00:03:27,090 from output values. 44 00:03:27,090 --> 00:03:33,019 So, looking at the state transition diagram on the right, suppose the FSM is in state 45 00:03:33,019 --> 00:03:35,040 S3. 46 00:03:35,040 --> 00:03:39,130 If the input is a 0, look for the arrow leaving S3 labeled "0/". 47 00:03:39,130 --> 00:03:45,359 The value after the slash tells us the output value, in this case 1. 48 00:03:45,359 --> 00:03:51,120 If the input had been a 1, the output value would be 0. 49 00:03:51,120 --> 00:03:55,349 There are some simple rules we can use to check that a state transition diagram is well 50 00:03:55,349 --> 00:03:56,700 formed. 51 00:03:56,700 --> 00:04:02,349 The transitions from a particular state must be mutually exclusive, i.e., for a each state, 52 00:04:02,349 --> 00:04:06,549 there can't be more than one transition with the same input label. 53 00:04:06,549 --> 00:04:11,560 This makes sense: if the FSM is to operate consistently there can't be any ambiguity 54 00:04:11,560 --> 00:04:15,170 about the next state for a given current state and input. 55 00:04:15,170 --> 00:04:20,700 By "consistently" we mean that the FSM should make the same transitions if it's restarted 56 00:04:20,700 --> 00:04:24,950 at the same starting state and given the same input sequences. 57 00:04:24,950 --> 00:04:31,711 Moreover, the transitions leaving each state should be collectively exhaustive, i.e., there 58 00:04:31,711 --> 00:04:36,730 should a transition specified for each possible input value. 59 00:04:36,730 --> 00:04:41,390 If we wish the FSM to stay in it's current state for that particular input value, we 60 00:04:41,390 --> 00:04:46,230 need to show a transition from the current state back to itself. 61 00:04:46,230 --> 00:04:50,560 With these rules there will be exactly one transition selected for every combination 62 00:04:50,560 --> 00:04:54,830 of current state and input value. 63 00:04:54,830 --> 00:04:59,450 All the information in a state transition diagram can be represented in tabular form 64 00:04:59,450 --> 00:05:01,360 as a truth table. 65 00:05:01,360 --> 00:05:06,330 The rows of the truth table list all the possible combinations of current state and inputs. 66 00:05:06,330 --> 00:05:11,450 And the output columns of the truth table tell us the next state and output value associated 67 00:05:11,450 --> 00:05:13,990 with each row. 68 00:05:13,990 --> 00:05:19,150 If we substitute binary values for the symbolic state names, we end up with a truth table 69 00:05:19,150 --> 00:05:22,380 just like the ones we saw in Chapter 4. 70 00:05:22,380 --> 00:05:28,680 If we have K states in our state transition diagram we'll need log_2(K) state bits, rounded 71 00:05:28,680 --> 00:05:31,950 up to the next integer since we don't have fractional bits! 72 00:05:31,950 --> 00:05:38,740 In our example, we have a 5-state FSM, so we'll need 3 state bits. 73 00:05:38,740 --> 00:05:45,560 We can assign the state encodings in any convenient way, e.g., 000 for the first state, 001 for 74 00:05:45,560 --> 00:05:48,390 the second state, and so on. 75 00:05:48,390 --> 00:05:52,360 But the choice of state encodings can have a big effect on the logic needed to implement 76 00:05:52,360 --> 00:05:53,380 the truth table. 77 00:05:53,380 --> 00:05:58,050 It's actually fun to figure out the state encoding that produces the simplest possible 78 00:05:58,050 --> 00:06:00,170 logic. 79 00:06:00,170 --> 00:06:04,830 With a truth table in hand, we can use the techniques from Chapter 4 to design logic 80 00:06:04,830 --> 00:06:08,090 circuits that implement the combinational logic for the FSM. 81 00:06:08,090 --> 00:06:15,100 Of course, we can take the easy way out and simply use a read-only memory to do the job! 82 00:06:15,100 --> 00:06:19,310 In this circuit, a read-only memory is used to compute the next state and outputs from 83 00:06:19,310 --> 00:06:22,010 the current state and inputs. 84 00:06:22,010 --> 00:06:27,720 We're encoding the 5 states of the FSM using a 3-bit binary value, so we have a 3-bit state 85 00:06:27,720 --> 00:06:28,720 register. 86 00:06:28,720 --> 00:06:34,840 The rectangle with the edge-triggered input is schematic shorthand for a multi-bit register. 87 00:06:34,840 --> 00:06:40,340 If a wire in the diagram represents a multi-bit signal, we use a little slash across the wire 88 00:06:40,340 --> 00:06:44,440 with a number to indicate how many bits are in the signal. 89 00:06:44,440 --> 00:06:47,500 In this example, both current_state and next_state are 3-bit signals. 90 00:06:47,500 --> 00:06:54,930 The read-only memory has a total of 4 input signals - 3 for the current state and 1 for 91 00:06:54,930 --> 00:07:00,470 the input value - so the read-only memory has 2^4 or 16 locations, 92 00:07:00,470 --> 00:07:04,680 which correspond to the 16 rows in the truth table. 93 00:07:04,680 --> 00:07:10,770 Each location in the ROM supplies the output values for a particular row of the truth table. 94 00:07:10,770 --> 00:07:16,120 Since we have 4 output signals - 3 for the next state and 1 for the output value - each 95 00:07:16,120 --> 00:07:20,510 location supplies 4 bits of information. 96 00:07:20,510 --> 00:07:25,020 Memories are often annotated with their number of locations and the number of bits in each 97 00:07:25,020 --> 00:07:26,500 location. 98 00:07:26,500 --> 00:07:32,700 So our memory is a 16-by-4 ROM: 16 locations of 4-bits each. 99 00:07:32,700 --> 00:07:38,110 Of course, in order for the state registers to work correctly, we need to ensure that 100 00:07:38,110 --> 00:07:41,220 the dynamic discipline is obeyed. 101 00:07:41,220 --> 00:07:45,530 We can use the timing analysis techniques described at the end of Chapter 5 to check 102 00:07:45,530 --> 00:07:47,640 that this is so. 103 00:07:47,640 --> 00:07:52,150 For now, we'll assume that the timing of transitions on the inputs are properly synchronized with 104 00:07:52,150 --> 00:07:53,870 the rising edges of the clock. 105 00:07:53,870 --> 00:07:59,600 So now we have the FSM abstraction to use when designing the functionality of a sequential 106 00:07:59,600 --> 00:08:05,260 logic system, and a general-purpose circuit implementation of the FSM using a ROM and 107 00:08:05,260 --> 00:08:07,240 a multi-bit state register. 108 00:08:07,240 --> 00:08:12,370 Recapping our design choices: the output bits can be strictly a function of the current 109 00:08:12,370 --> 00:08:16,250 state (the FSM would then be called a Moore machine), 110 00:08:16,250 --> 00:08:20,600 or they can be a function of both the current state and current inputs, in which case the 111 00:08:20,600 --> 00:08:23,720 FSM is called a Mealy machine. 112 00:08:23,720 --> 00:08:28,520 We can choose the number of state bits - S state bits will give us the ability to encode 113 00:08:28,520 --> 00:08:31,520 2^S possible states. 114 00:08:31,520 --> 00:08:36,630 Note that each extra state bit DOUBLES the number of locations in the ROM! 115 00:08:36,630 --> 00:08:41,450 So when using ROMs to implement the necessary logic, we're very interested in minimizing 116 00:08:41,450 --> 00:08:44,920 the number of state bits. 117 00:08:44,920 --> 00:08:48,390 The waveforms for our circuitry are pretty straightforward. 118 00:08:48,390 --> 00:08:54,170 The rising edge of the clock triggers a transition in the state register outputs. 119 00:08:54,170 --> 00:08:58,770 The ROM then does its thing, calculating the next state, which becomes valid at some point 120 00:08:58,770 --> 00:09:00,890 in the clock cycle. 121 00:09:00,890 --> 00:09:06,620 This is the value that gets loaded into the state registers at the next rising clock edge. 122 00:09:06,620 --> 00:09:11,370 This process repeats over-and-over as the FSM follows the state transitions dictated 123 00:09:11,370 --> 00:09:14,550 by the state transition diagram. 124 00:09:14,550 --> 00:09:18,690 There are a few housekeeping details that need our attention. 125 00:09:18,690 --> 00:09:23,250 On start-up we need some way to set the initial contents of the state register to the correct 126 00:09:23,250 --> 00:09:26,300 encoding for the initial state. 127 00:09:26,300 --> 00:09:30,990 Many designs use a RESET signal that's set to 1 to force some initial state and then 128 00:09:30,990 --> 00:09:34,260 set to 0 to start execution. 129 00:09:34,260 --> 00:09:39,340 We could adopt that approach here, using the RESET signal to select an initial value to 130 00:09:39,340 --> 00:09:43,360 be loaded into the state register. 131 00:09:43,360 --> 00:09:48,610 In our example, we used a 3-bit state encoding which would allow us to implement an FSM with 132 00:09:48,610 --> 00:09:52,180 up to 2^3 = 8 states. 133 00:09:52,180 --> 00:09:56,240 We're only using 5 of these encodings, which means there are locations in the ROM we'll 134 00:09:56,240 --> 00:09:57,240 never access. 135 00:09:57,240 --> 00:10:02,700 If that's a concern, we can always use logic gates to implement the necessary combinational 136 00:10:02,700 --> 00:10:06,460 logic instead of ROMs. 137 00:10:06,460 --> 00:10:11,160 Suppose the state register somehow got loaded with one of the unused encodings? 138 00:10:11,160 --> 00:10:15,370 Well, that would be like being in a state that's not listed in our state transition 139 00:10:15,370 --> 00:10:16,860 diagram. 140 00:10:16,860 --> 00:10:22,010 One way to defend against this problem is design the ROM contents so that unused states 141 00:10:22,010 --> 00:10:25,840 always point to the initial state. 142 00:10:25,840 --> 00:10:30,000 In theory the problem should never arise, but with this fix at least it won't lead to 143 00:10:30,000 --> 00:10:32,050 unknown behavior. 144 00:10:32,050 --> 00:10:37,710 We mentioned earlier the interesting problem of finding a state encoding that minimized 145 00:10:37,710 --> 00:10:40,730 the combinational logic. 146 00:10:40,730 --> 00:10:46,020 There are computer-aided design tools to help do this as part of the larger problem of finding 147 00:10:46,020 --> 00:10:50,760 minimal logic implementations for Boolean functions. 148 00:10:50,760 --> 00:10:54,760 Mr. Blue is showing us another approach to building the state register for the combination 149 00:10:54,760 --> 00:10:58,350 lock: use a shift register to capture the last four 150 00:10:58,350 --> 00:11:04,740 input bits, then simply look at the recorded history to determine if it matches the combination. 151 00:11:04,740 --> 00:11:07,230 No fancy next0state logic here! 152 00:11:07,230 --> 00:11:12,220 Finally, we still have to address the problem of ensuring that input transitions don't violate 153 00:11:12,220 --> 00:11:15,420 the dynamic discipline for the state register. 154 00:11:15,420 --> 00:11:17,709 We'll get to this in the last section of this chapter.