WEBVTT

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We’ll get a good understanding
of how the register operates

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as we follow the signals
through the circuit.

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The overall operation of
the register is simple:

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At the rising 0-to-1
transition of the clock input,

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the register samples
the value of the D input

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and stores that value until
the next rising clock edge.

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The Q output is simply the
value stored in the register.

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Let’s see how the register
implements this functionality.

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The clock signal is connected
to the gate inputs of the master

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and slave latches.

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Since all the action
happens when the clock makes

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a transition, it’s those
events we’ll focus on.

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The clock transition
from LOW to HIGH

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is called the rising
edge of the clock.

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And its transition from HIGH to
LOW is called the falling edge.

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Let’s start by looking the
operation of the master latch

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and its output signal, which
is labeled STAR in the diagram.

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On the rising edge of
the clock, the master

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latch goes from open to closed,
sampling the value on its input

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and entering memory mode.

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The sampled value thus becomes
the output of the latch

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as long as the
latch stays closed.

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You can see that the STAR
signal remains stable whenever

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the clock signal is high.

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On the falling edge of the
clock the master latch opens

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and its output will
then reflect any changes

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in the D input, delayed
by the tPD of the latch.

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Now let’s figure out
what the slave is doing.

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It’s output signal, which
also serves as the output of D

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register, is shown as
the bottom waveform.

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On the rising edge of the
clock the slave latch opens

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and its output will follow
the value of the STAR signal.

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Remember though that the
STAR signal is stable

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while the clock is HIGH since
the master latch is closed,

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so the Q signal is also stable
after an initial transition

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if value saved in the
slave latch is changing.

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At the falling
clock edge [CLICK],,

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the slave goes from
open to closed,

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sampling the value on its
input and entering memory mode.

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The sampled value then becomes
the output of the slave

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latch as long as the
latch stays closed.

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You can see that that the Q
output remains stable whenever

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the clock signal is LOW.

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Now let’s just look at the Q
signal by itself for a moment.

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It only changes
when the slave latch

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opens at the rising
edge of the clock.

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The rest of the time either the
input to slave latch is stable

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or the slave latch is closed.

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The change in the Q output is
triggered by the rising edge

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of the clock, hence the name
“positive-edge-triggered D

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register”.

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The convention for
labeling the clock input

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in the schematic icon for
an edge-triggered device

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is to use a little triangle.

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You can see that here in the
schematic symbol for the D

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register.

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There is one tricky
problem we have

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to solve when designing the
circuitry for the register.

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On the falling clock edge,
the slave latch transitions

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from open to closed and so
its input (the STAR signal)

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must meet the setup and
hold times of the slave

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latch in order to ensure
correct operation.

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The complication is
that the master latch

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opens at the same time, so the
STAR signal may change shortly

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after the clock edge.

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The contamination delay
of the master latch

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tells us how long
the old value will

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be stable after the
falling clock edge.

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And the hold time
on the slave latch

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tells us how long it
has to remain stable

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after the falling clock edge.

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So to ensure correct
operation of the slave latch,

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the contamination delay
of the master latch

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has to be greater than or equal
to the hold time of the slave

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latch.

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Doing the necessary
analysis can be a bit tricky

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since we have to consider
manufacturing variations as

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well as environmental factors
such as temperature and power

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supply voltage.

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If necessary, extra
gate delays (e.g.,

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pairs of inverters) can be added
between the master and slave

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latches to increase
the contamination delay

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on the slave’s input relative
to the falling clock edge.

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Note that we can only
solve slave latch hold

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time issues by changing
the design of the circuit.

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Here’s a summary of the
timing specifications for a D

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register.

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Changes in the Q signal
are triggered by a rising

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edge on the clock input.

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The propagation delay
t_PD of the register

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is an upper bound on the time
it takes for the Q output

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to become valid and stable
after the rising clock edge.

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The contamination
delay of the register

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is a lower bound on the
time the previous value of Q

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remains valid after
the rising clock edge.

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Note that both t_CD and t_PD are
measured relative to the rising

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edge of the clock.

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Registers are designed to
be lenient in the sense

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that if the previous value
of Q and the new value of Q

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are the same, the
stability of the Q signal

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is guaranteed during
the rising clock edge.

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In other words, the t_CD
and t_PD specifications

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only apply when the Q
output actually changes.

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In order to ensure correct
operation of the master latch,

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the register’s D input must
meet the setup and hold time

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constraints for
the master latch.

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So the following
two specifications

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are determined by the
timing of the master latch.

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t_SETUP is the amount
of time that the D input

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must be valid and stable
before the rising clock

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edge and t_HOLD is
the amount of time

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that D must be valid and
stable after the rising clock.

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This region of stability
surrounding the clock edge

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ensures that we’re obeying
the dynamic discipline

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for the master latch.

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So when you use a D register
component from a manufacturer’s

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gate library,

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you’ll need to look up these
four timing specifications

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in the register’s data sheet
in order to analyze the timing

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of your overall circuit.

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We’ll see how this analysis
is done in the next section.