1 00:00:00,760 --> 00:00:05,970 For this problem, we are going to make use of this simple datapath that consists of a 2 00:00:05,970 --> 00:00:12,000 four register register file, a relatively simple arithmetic logic unit that can perform 3 00:00:12,000 --> 00:00:18,700 ADD, SUB, MUL, and NAND operations. In addition, it can compare two inputs and 4 00:00:18,700 --> 00:00:23,820 determine whether or not they are equal. The result of the comparison, Z, can then 5 00:00:23,820 --> 00:00:29,350 be used to control what happens next. There are multiple control signals in this 6 00:00:29,350 --> 00:00:33,550 datapath. The first two are Asel and Bsel. 7 00:00:33,550 --> 00:00:38,829 These are used to select which register drives the corresponding multiplexer output. 8 00:00:38,829 --> 00:00:44,199 The value stored in the register selected by Asel becomes the A input to the arithmetic 9 00:00:44,199 --> 00:00:49,440 operations and is passed to the arithmetic units along the red wire. 10 00:00:49,440 --> 00:00:54,699 The value stored in the register selected by Bsel becomes the B input to the arithmetic 11 00:00:54,699 --> 00:01:00,069 operations and is passed to the arithmetic units along the blue wire. 12 00:01:00,069 --> 00:01:05,410 The next control signal is Opsel. It selects which of the four operation outputs 13 00:01:05,410 --> 00:01:11,220 should be selected by the Opsel multiplexer as the result of our operation. 14 00:01:11,220 --> 00:01:16,070 This result is fed back to the register file along the purple wire. 15 00:01:16,070 --> 00:01:22,960 The Wen is a write enable for the register file which specifies whether or not the result 16 00:01:22,960 --> 00:01:27,420 of our operation should be written back into the register file. 17 00:01:27,420 --> 00:01:33,130 If it is supposed to be written back to the register file, then the Wsel control signal 18 00:01:33,130 --> 00:01:37,729 selects to which of the registers the result should be written. 19 00:01:37,729 --> 00:01:43,530 The yellow box is the control FSM. It generates the control signals for the rest 20 00:01:43,530 --> 00:01:49,020 of the datapath based on the operations that you want to perform. 21 00:01:49,020 --> 00:01:52,140 Suppose the initial value of our 4 registers is: 22 00:01:52,140 --> 00:02:02,450 R0 = 1, R1 = 0, R2 = -1, and R3 = N. We want to evaluate the result of the function 23 00:02:02,450 --> 00:02:11,389 3 * N – 2 and store the result into R3. Our job is to design the control FSM so that 24 00:02:11,389 --> 00:02:15,430 it produces the correct signals to achieve what we want. 25 00:02:15,430 --> 00:02:19,959 To help us get started, here is an incomplete listing of the code that will achieve what 26 00:02:19,959 --> 00:02:24,400 we want. The Sx labels are the names of the states 27 00:02:24,400 --> 00:02:30,129 corresponding to each instruction in our program. Our first job is to figure out the values 28 00:02:30,129 --> 00:02:36,099 of RX, RY, and RZ so that our code behaves as expected. 29 00:02:36,099 --> 00:02:42,709 Let's begin by looking at state S0. We want to end up with the value -2 in R2 30 00:02:42,709 --> 00:02:48,170 by adding R2 which currently holds -1 to some register. 31 00:02:48,170 --> 00:02:55,439 In order to produce -2, we need to add -1 which means that RX = R2. 32 00:02:55,439 --> 00:03:02,931 Next, we look at state S1. Here we want to end up with the value 2 in 33 00:03:02,931 --> 00:03:08,099 R1 by adding Ry to R0 which currently holds a 1. 34 00:03:08,099 --> 00:03:16,969 In order to produce 2, we need to add 1 which means RY = R0. 35 00:03:16,969 --> 00:03:21,939 State S2 adds R0 to R1 and stores the result in R1. 36 00:03:21,939 --> 00:03:28,200 Since R0 still equals 1 and R1 = 2, then we produce R1 = 3. 37 00:03:28,200 --> 00:03:35,120 Now, let's look at state S3. Our goal is to multiply 3*N and store the 38 00:03:35,120 --> 00:03:41,280 result into R3. To achieve this, we multiply RZ by R3 and 39 00:03:41,280 --> 00:03:46,930 store the result in R3. Since R3 currently = N, that means that we 40 00:03:46,930 --> 00:03:53,599 want to multiply it by R1 which equals 3. So RZ = R1. 41 00:03:53,599 --> 00:04:02,809 Finally, we add R3 and R2 to produce 3*N-2 and store that result back into R3. 42 00:04:02,809 --> 00:04:08,639 S5 just executes a HALT() instruction to indicate that we are done. 43 00:04:08,639 --> 00:04:13,340 Now that we have working code, our next goal is to determine the settings for the control 44 00:04:13,340 --> 00:04:19,170 FSM that will make the correct operations be executed by our datapath. 45 00:04:19,170 --> 00:04:24,320 Since we have 6 states, we will need 3 state bits to encode the value of the current and 46 00:04:24,320 --> 00:04:30,020 next state. We begin with state S0. 47 00:04:30,020 --> 00:04:38,120 In order to encode that we are in state zero using 3 bits, we set our current state, S[2:0] 48 00:04:38,120 --> 00:04:42,840 to 000. In this operation we don't care about the 49 00:04:42,840 --> 00:04:50,440 Z signal, so Z = X which means don't care. The instruction that we want to execute after 50 00:04:50,440 --> 00:04:58,760 this first ADD, is the next ADD in state S1. This means that our next state is 001. 51 00:04:58,760 --> 00:05:05,500 Note that the notation S' is often used to represent the next state. 52 00:05:05,500 --> 00:05:10,080 Our register select signals each need to select one of 4 registers. 53 00:05:10,080 --> 00:05:14,080 This means that these signals must each be 2 bits wide. 54 00:05:14,080 --> 00:05:19,480 Our Asel control signal identifies the register that should be used as input A. 55 00:05:19,480 --> 00:05:28,720 This register is R2, so Asel is 10. Bsel identifies the second source operand. 56 00:05:28,720 --> 00:05:35,830 In this case it is also R2, so Bsel = 10 as well. 57 00:05:35,830 --> 00:05:40,620 The Opsel signal identifies which operation we want to perform. 58 00:05:40,620 --> 00:05:45,770 Since we have 4 distinct operations, we would need two bits to distinguish amongst them 59 00:05:45,770 --> 00:05:50,690 and we would make each operation be associated with one of the 4 encodings. 60 00:05:50,690 --> 00:05:56,250 For simplicity, let's just label Opsel as ADD to indicate that we selected the encoding 61 00:05:56,250 --> 00:06:01,960 for the ADD. The register we want to write our result to, 62 00:06:01,960 --> 00:06:07,030 also known as the destination register, is R2 for this operation. 63 00:06:07,030 --> 00:06:16,180 This means that Wsel = 10 and Wen = 1. Wen is a signal that enables writing to the 64 00:06:16,180 --> 00:06:20,490 register file. If it is set to 0, then regardless of the 65 00:06:20,490 --> 00:06:26,490 value of Wsel, no value will be written into the register file. 66 00:06:26,490 --> 00:06:30,310 Now let's quickly run through the rest of our instructions. 67 00:06:30,310 --> 00:06:36,620 Our current state is state S1, or 001. Once again Z is a don't care. 68 00:06:36,620 --> 00:06:43,890 Since the instruction that will be executed next is the one in S2, our next state is 010. 69 00:06:43,890 --> 00:06:58,400 Our Asel = 00 and Bsel = 00. Opsel = ADD and Wsel = 01 and Wen = 1. 70 00:06:58,400 --> 00:07:05,760 State 2 follows the same model, so current state is 010 and next state is 011. 71 00:07:05,760 --> 00:07:15,860 Here Asel = 00, Bsel = 01 and Wsel = 01 and Wen = 1. 72 00:07:15,860 --> 00:07:22,480 Once again our Opsel is an ADD. We move on to state 3 whose current state 73 00:07:22,480 --> 00:07:37,020 is 011 and next state is 100. Asel = 01, Bsel = 11, Wsel = 11, and Wen = 1. 74 00:07:37,020 --> 00:07:44,409 Here our Opsel is MUL to indicate that the operation to be executed here is a multiply. 75 00:07:44,409 --> 00:07:51,870 For state four, we have current state set to 100 and next state to 101. 76 00:07:51,870 --> 00:08:02,930 Asel = 11, Bsel = 10, Wsel = 11, and Wen = 1. Our Opsel is once again ADD. 77 00:08:02,930 --> 00:08:08,030 Finally, we reach state 5. This state looks a little different from the 78 00:08:08,030 --> 00:08:11,620 previous states so lets examine it a little more closely. 79 00:08:11,620 --> 00:08:16,090 The first thing to note, is that when we get to state 5 we want to stay there because we 80 00:08:16,090 --> 00:08:23,150 are done with our execution, so both the current state and the next state are 101. 81 00:08:23,150 --> 00:08:28,910 Most of the other control bits can be set to don't care because at this point we mostly 82 00:08:28,910 --> 00:08:32,429 don't care about what the rest of the datapath is doing. 83 00:08:32,429 --> 00:08:36,990 The only other signal that we do need to worry about is Wen. 84 00:08:36,990 --> 00:08:41,770 Since we are allowing the rest of our datapath to run in whatever way, we need to ensure 85 00:08:41,770 --> 00:08:47,550 that nothing produced on the datapath at this stage gets written back to any of the registers. 86 00:08:47,550 --> 00:08:55,110 In order to guarantee that, we set Wen = 0. Here is the complete control ROM that will 87 00:08:55,110 --> 00:09:01,140 execute the function 3*N-2 and store its result into R3.