WEBVTT

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On our to-do list from
the previous section

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is figuring out how to build AND
and OR gates with many inputs.

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These will be needed
when creating circuit

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implementations using a
sum-of-products equation

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as our template.

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Let’s assume our gate library
only has 2-input gates

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and figure how to build wider
gates using the 2-input gates

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as building blocks.

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We’ll work on creating
3- and 4-input gates,

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but the approach we use can
be generalized to create AND

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and OR gates of
any desired width.

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The approach shown here relies
on the associative property

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of the AND operator.

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This means we can
perform an N-way

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AND by doing pair-wise ANDs
in any convenient order.

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The OR and XOR operations
are also associative,

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so the same approach will work
for designing wide OR and XOR

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circuits from the
corresponding 2-input gate.

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Simply substitute 2-input OR
gates or 2-input XOR gates

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for the 2-input AND gates shown
below and you’re good to go!

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Let’s start by designing a
circuit that computes the AND

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of three inputs A, B, and C.

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In the circuit shown here,
we first compute (A AND B),

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then AND that result with C.

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Using the same strategy, we
can build a 4-input AND gate

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from three 2-input AND gates.

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Essentially we’re building
a chain of AND gates,

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which implement an N-way AND
using N-1 2-input AND gates.

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We can also associate the
four inputs a different way:

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computing (A AND B) in
parallel with (C AND D),

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then combining those two
results using a third AND gate.

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Using this approach, we’re
building a tree of AND gates.

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Which approach is
best: chains or trees?

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First we have to decide
what we mean by “best”.

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When designing circuits
we’re interested in cost,

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which depends on the number of
components, and performance,

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which we characterize
by the propagation delay

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of the circuit.

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Both strategies require the
same number of components

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since the total number
of pair-wise ANDs

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is the same in both cases.

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So it’s a tie when
considering costs.

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Now consider propagation delay.

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The chain circuit in the middle
has a tPD of 3 gate delays,

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and we can see that the
tPD for an N-input chain

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will be N-1 gate delays.

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The propagation delay
of chains grows linearly

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with the number of inputs.

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The tree circuit
on the bottom has

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a tPD of 2 gates,
smaller than the chain.

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The propagation delay of
trees grows logarithmically

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with the number of inputs.

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Specifically, the
propagation delay

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of tree circuits built using
2-input gates grows as log2(N).

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When N is large,
tree circuits can

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have dramatically
better propagation delay

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than chain circuits.

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The propagation
delay is an upper

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bound on the worst-case
delay from inputs to outputs

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and is a good measure
of performance

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assuming that all inputs
arrive at the same time.

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But in large circuits,
A, B, C and D

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might arrive at
different times depending

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on the tPD of the circuit
generating each one.

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Suppose input D
arrives considerably

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after the other inputs.

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If we used the tree circuit
to compute the AND of all four

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inputs, the additional
delay in computing Z

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is two gate delays
after the arrival of D.

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However, if we use
the chain circuit,

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the additional
delay in computing Z

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might be as little
as one gate delay.

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The moral of this story:
it’s hard to know which

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implementation of a subcircuit,
like the 4-input AND shown

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here, will yield the smallest
overall tPD unless we know

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the tPD of the circuits
that compute the values

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for the input signals.

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In designing CMOS circuits,
the individual gates

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are naturally inverting, so
instead of using AND and OR

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gates, for the best
performance we want to the use

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the NAND and NOR
gates shown here.

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NAND and NOR gates can be
implemented as a single CMOS

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gate involving one pullup
circuit and one pulldown

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circuit.

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AND and OR gates
require two CMOS gates

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in their implementation,
e.g., a NAND gate

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followed by an INVERTER.

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We’ll talk about how to build
sum-of-products circuitry using

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NANDs and NORs in
the next section.

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Note that NAND and NOR
operations are not associative:

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NAND(A,B,C) is not equal
to NAND(NAND(A,B),C).

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So we can’t build a NAND gate
with many inputs by building

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a tree of 2-input NANDs.

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We’ll talk about this
in the next section too!

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We’ve mentioned the
exclusive-or operation,

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sometimes called
XOR, several times.

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This logic function
is very useful

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when building circuitry
for arithmetic or parity

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calculations.

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As you’ll see in Lab 2,
implementing a 2-input XOR gate

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will take many more NFETs
and PFETs than required

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for a 2-input NAND or NOR.

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We know we can come up with
a sum-of-products expression

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for any truth table
and hence build

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a circuit implementation
using INVERTERs, AND gates,

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and OR gates.

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It turns out we
can build circuits

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with the same functionality
using only 2-INPUT NAND gates.

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We say the the 2-INPUT
NAND is a universal gate.

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Here we show how to implement
the sum-of-products building

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blocks using just
2-input NAND gates.

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In a minute we’ll show a
more direct implementation

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for sum-of-products
using only NANDs,

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but these little schematics are
a proof-of-concept showing that

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NAND-only equivalent
circuits exist.

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2-INPUT NOR gates
are also universal,

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as shown by these
little schematics.

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Inverting logic takes a
little getting used to,

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but its the key to designing
low-cost high-performance

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circuits in CMOS.