1
00:00:00,500 --> 00:00:03,770
We’ll get a good understanding
of how the register operates

2
00:00:03,770 --> 00:00:07,030
as we follow the signals
through the circuit.

3
00:00:07,030 --> 00:00:09,930
The overall operation of
the register is simple:

4
00:00:09,930 --> 00:00:13,120
At the rising 0-to-1
transition of the clock input,

5
00:00:13,120 --> 00:00:15,770
the register samples
the value of the D input

6
00:00:15,770 --> 00:00:20,180
and stores that value until
the next rising clock edge.

7
00:00:20,180 --> 00:00:23,360
The Q output is simply the
value stored in the register.

8
00:00:23,360 --> 00:00:27,890
Let’s see how the register
implements this functionality.

9
00:00:27,890 --> 00:00:31,100
The clock signal is connected
to the gate inputs of the master

10
00:00:31,100 --> 00:00:32,790
and slave latches.

11
00:00:32,790 --> 00:00:35,150
Since all the action
happens when the clock makes

12
00:00:35,150 --> 00:00:39,010
a transition, it’s those
events we’ll focus on.

13
00:00:39,010 --> 00:00:41,440
The clock transition
from LOW to HIGH

14
00:00:41,440 --> 00:00:43,920
is called the rising
edge of the clock.

15
00:00:43,920 --> 00:00:47,780
And its transition from HIGH to
LOW is called the falling edge.

16
00:00:47,780 --> 00:00:50,610
Let’s start by looking the
operation of the master latch

17
00:00:50,610 --> 00:00:55,488
and its output signal, which
is labeled STAR in the diagram.

18
00:00:55,488 --> 00:00:57,280
On the rising edge of
the clock, the master

19
00:00:57,280 --> 00:01:01,000
latch goes from open to closed,
sampling the value on its input

20
00:01:01,000 --> 00:01:03,120
and entering memory mode.

21
00:01:03,120 --> 00:01:05,770
The sampled value thus becomes
the output of the latch

22
00:01:05,770 --> 00:01:08,460
as long as the
latch stays closed.

23
00:01:08,460 --> 00:01:11,590
You can see that the STAR
signal remains stable whenever

24
00:01:11,590 --> 00:01:14,880
the clock signal is high.

25
00:01:14,880 --> 00:01:17,840
On the falling edge of the
clock the master latch opens

26
00:01:17,840 --> 00:01:20,300
and its output will
then reflect any changes

27
00:01:20,300 --> 00:01:25,210
in the D input, delayed
by the tPD of the latch.

28
00:01:25,210 --> 00:01:28,150
Now let’s figure out
what the slave is doing.

29
00:01:28,150 --> 00:01:31,190
It’s output signal, which
also serves as the output of D

30
00:01:31,190 --> 00:01:34,440
register, is shown as
the bottom waveform.

31
00:01:34,440 --> 00:01:37,250
On the rising edge of the
clock the slave latch opens

32
00:01:37,250 --> 00:01:40,750
and its output will follow
the value of the STAR signal.

33
00:01:40,750 --> 00:01:42,920
Remember though that the
STAR signal is stable

34
00:01:42,920 --> 00:01:46,210
while the clock is HIGH since
the master latch is closed,

35
00:01:46,210 --> 00:01:49,530
so the Q signal is also stable
after an initial transition

36
00:01:49,530 --> 00:01:54,042
if value saved in the
slave latch is changing.

37
00:01:54,042 --> 00:01:55,500
At the falling
clock edge [CLICK],,

38
00:01:55,500 --> 00:01:57,900
the slave goes from
open to closed,

39
00:01:57,900 --> 00:02:01,550
sampling the value on its
input and entering memory mode.

40
00:02:01,550 --> 00:02:04,400
The sampled value then becomes
the output of the slave

41
00:02:04,400 --> 00:02:07,260
latch as long as the
latch stays closed.

42
00:02:07,260 --> 00:02:10,090
You can see that that the Q
output remains stable whenever

43
00:02:10,090 --> 00:02:12,540
the clock signal is LOW.

44
00:02:12,540 --> 00:02:16,530
Now let’s just look at the Q
signal by itself for a moment.

45
00:02:16,530 --> 00:02:18,560
It only changes
when the slave latch

46
00:02:18,560 --> 00:02:21,340
opens at the rising
edge of the clock.

47
00:02:21,340 --> 00:02:25,090
The rest of the time either the
input to slave latch is stable

48
00:02:25,090 --> 00:02:27,720
or the slave latch is closed.

49
00:02:27,720 --> 00:02:30,790
The change in the Q output is
triggered by the rising edge

50
00:02:30,790 --> 00:02:34,220
of the clock, hence the name
“positive-edge-triggered D

51
00:02:34,220 --> 00:02:35,340
register”.

52
00:02:35,340 --> 00:02:37,350
The convention for
labeling the clock input

53
00:02:37,350 --> 00:02:39,860
in the schematic icon for
an edge-triggered device

54
00:02:39,860 --> 00:02:41,780
is to use a little triangle.

55
00:02:41,780 --> 00:02:44,230
You can see that here in the
schematic symbol for the D

56
00:02:44,230 --> 00:02:45,650
register.

57
00:02:45,650 --> 00:02:47,490
There is one tricky
problem we have

58
00:02:47,490 --> 00:02:50,880
to solve when designing the
circuitry for the register.

59
00:02:50,880 --> 00:02:53,440
On the falling clock edge,
the slave latch transitions

60
00:02:53,440 --> 00:02:56,760
from open to closed and so
its input (the STAR signal)

61
00:02:56,760 --> 00:02:59,120
must meet the setup and
hold times of the slave

62
00:02:59,120 --> 00:03:01,990
latch in order to ensure
correct operation.

63
00:03:01,990 --> 00:03:03,910
The complication is
that the master latch

64
00:03:03,910 --> 00:03:07,620
opens at the same time, so the
STAR signal may change shortly

65
00:03:07,620 --> 00:03:10,110
after the clock edge.

66
00:03:10,110 --> 00:03:12,200
The contamination delay
of the master latch

67
00:03:12,200 --> 00:03:14,220
tells us how long
the old value will

68
00:03:14,220 --> 00:03:17,230
be stable after the
falling clock edge.

69
00:03:17,230 --> 00:03:18,900
And the hold time
on the slave latch

70
00:03:18,900 --> 00:03:21,620
tells us how long it
has to remain stable

71
00:03:21,620 --> 00:03:24,010
after the falling clock edge.

72
00:03:24,010 --> 00:03:27,060
So to ensure correct
operation of the slave latch,

73
00:03:27,060 --> 00:03:29,620
the contamination delay
of the master latch

74
00:03:29,620 --> 00:03:32,640
has to be greater than or equal
to the hold time of the slave

75
00:03:32,640 --> 00:03:34,260
latch.

76
00:03:34,260 --> 00:03:36,640
Doing the necessary
analysis can be a bit tricky

77
00:03:36,640 --> 00:03:39,630
since we have to consider
manufacturing variations as

78
00:03:39,630 --> 00:03:42,910
well as environmental factors
such as temperature and power

79
00:03:42,910 --> 00:03:44,800
supply voltage.

80
00:03:44,800 --> 00:03:47,700
If necessary, extra
gate delays (e.g.,

81
00:03:47,700 --> 00:03:51,620
pairs of inverters) can be added
between the master and slave

82
00:03:51,620 --> 00:03:53,850
latches to increase
the contamination delay

83
00:03:53,850 --> 00:03:57,090
on the slave’s input relative
to the falling clock edge.

84
00:03:57,090 --> 00:03:59,420
Note that we can only
solve slave latch hold

85
00:03:59,420 --> 00:04:02,720
time issues by changing
the design of the circuit.

86
00:04:02,720 --> 00:04:05,440
Here’s a summary of the
timing specifications for a D

87
00:04:05,440 --> 00:04:06,780
register.

88
00:04:06,780 --> 00:04:09,440
Changes in the Q signal
are triggered by a rising

89
00:04:09,440 --> 00:04:11,500
edge on the clock input.

90
00:04:11,500 --> 00:04:14,090
The propagation delay
t_PD of the register

91
00:04:14,090 --> 00:04:17,060
is an upper bound on the time
it takes for the Q output

92
00:04:17,060 --> 00:04:21,190
to become valid and stable
after the rising clock edge.

93
00:04:21,190 --> 00:04:23,180
The contamination
delay of the register

94
00:04:23,180 --> 00:04:26,040
is a lower bound on the
time the previous value of Q

95
00:04:26,040 --> 00:04:29,500
remains valid after
the rising clock edge.

96
00:04:29,500 --> 00:04:33,860
Note that both t_CD and t_PD are
measured relative to the rising

97
00:04:33,860 --> 00:04:35,670
edge of the clock.

98
00:04:35,670 --> 00:04:38,100
Registers are designed to
be lenient in the sense

99
00:04:38,100 --> 00:04:41,900
that if the previous value
of Q and the new value of Q

100
00:04:41,900 --> 00:04:44,780
are the same, the
stability of the Q signal

101
00:04:44,780 --> 00:04:47,980
is guaranteed during
the rising clock edge.

102
00:04:47,980 --> 00:04:51,080
In other words, the t_CD
and t_PD specifications

103
00:04:51,080 --> 00:04:55,760
only apply when the Q
output actually changes.

104
00:04:55,760 --> 00:04:58,960
In order to ensure correct
operation of the master latch,

105
00:04:58,960 --> 00:05:02,140
the register’s D input must
meet the setup and hold time

106
00:05:02,140 --> 00:05:04,250
constraints for
the master latch.

107
00:05:04,250 --> 00:05:06,990
So the following
two specifications

108
00:05:06,990 --> 00:05:10,270
are determined by the
timing of the master latch.

109
00:05:10,270 --> 00:05:12,920
t_SETUP is the amount
of time that the D input

110
00:05:12,920 --> 00:05:15,400
must be valid and stable
before the rising clock

111
00:05:15,400 --> 00:05:17,480
edge and t_HOLD is
the amount of time

112
00:05:17,480 --> 00:05:21,640
that D must be valid and
stable after the rising clock.

113
00:05:21,640 --> 00:05:24,410
This region of stability
surrounding the clock edge

114
00:05:24,410 --> 00:05:27,420
ensures that we’re obeying
the dynamic discipline

115
00:05:27,420 --> 00:05:29,630
for the master latch.

116
00:05:29,630 --> 00:05:33,280
So when you use a D register
component from a manufacturer’s

117
00:05:33,280 --> 00:05:34,440
gate library,

118
00:05:34,440 --> 00:05:37,090
you’ll need to look up these
four timing specifications

119
00:05:37,090 --> 00:05:40,660
in the register’s data sheet
in order to analyze the timing

120
00:05:40,660 --> 00:05:42,590
of your overall circuit.

121
00:05:42,590 --> 00:05:46,530
We’ll see how this analysis
is done in the next section.