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In the last chapter we
developed sequential logic,

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which contains both
combinational logic and memory

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components.

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The combinational logic
cloud is an acyclic graph

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of components that obeys
the static discipline.

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The static discipline guarantees
if we supply valid and stable

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digital inputs, then we
will get valid and stable

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digital outputs
by some specified

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interval after the
last input transition.

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There’s also a functional
specification that tells us

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the output values for every
possible combination of input

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values.

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In this diagram, there are
k+m inputs and k+n outputs,

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so the truth table for the
combinational logic will have

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2^(k+m) rows and
k+n output columns.

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The job of the
state registers is

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to remember the current state
of the sequential logic.

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The state is encoded as
some number k of bits,

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which will allow us to
represent 2^k unique states.

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Recall that the state
is used to capture,

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in some appropriate way, the
relevant history of the input

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sequence.

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To the extent that previous
input values influence

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the operation of the
sequential logic,

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that happens through
the stored state bits.

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Typically the LOAD input
of the state registers

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is triggered by the rising edge
of a periodic signal, which

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updates the stored state
with the new state calculated

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by the combinational logic.

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As designers we
have several tasks:

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first we must decide
what output sequences

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need to be generated in
response to the expected input

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sequences.

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A particular input may, in
fact, generate a long sequence

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of output values.

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Or the output may
remain unchanged

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while the input sequence
is processed, step-by-step,

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where the FSM is remembering
the relevant information

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by updating its internal state.

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Then we have to develop the
functional specification

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for the logic so it
calculates the correct output

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and next state values.

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Finally, we need to come up
with an actual circuit diagram

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for sequential logic system.

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All the tasks are
pretty interesting,

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so let’s get started!

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As an example sequential system,
let’s make a combination lock.

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The lock has a
1-bit input signal,

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where the user enters
the combination

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as a sequence of bits.

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There’s one output
signal, UNLOCK,

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which is 1 if and only if the
correct combination has been

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entered.

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In this example, we want
to assert UNLOCK, i.e.,

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set UNLOCK to 1, when the
last four input values are

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the sequence 0-1-1-0.

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Mr. Blue is asking
a good question:

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how many state bits do we need?

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Do we have to remember
the last four input bits?

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In which case, we’d
need four state bits.

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Or can we remember
less information

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and still do our job?

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Aha!

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We don’t need the complete
history of the last four

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inputs, we only need to know
if the most recent entries

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represent some part of a
partially-entered correct

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combination.

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In other words if the input
sequence doesn’t represent

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a correct combination, we don’t
need to keep track of exactly

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how it’s incorrect, we only
need to know that is incorrect.

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With that observation in
mind, let’s figure out how

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to represent the desired
behavior of our digital system.

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We can characterize the behavior
of a sequential system using

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a new abstraction called
a finite state machine,

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or FSM for short.

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The goal of the
FSM abstraction is

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to describe the
input/output behavior

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of the sequential
logic, independent

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of its actual implementation.

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A finite state machine has
a periodic CLOCK input.

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A rising clock edge will
trigger the transition

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from the current state
to the next state.

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The FSM has a some
fixed number of states,

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with a particular
state designated

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as the initial or
starting state when

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the FSM is first turned on.

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One of the interesting
challenges in designing an FSM

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is to determine the required
number of states since there’s

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often a tradeoff between
the number of state bits

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and the complexity of the
internal combinational logic

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required to compute the
next state and outputs.

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There are some number
of inputs, used

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to convey all the
external information

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necessary for the
FSM to do its job.

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Again, there are interesting
design tradeoffs.

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Suppose the FSM required
100 bits of input.

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Should we have 100 inputs
and deliver the information

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all at once?

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Or should we have a single input
and deliver the information

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as a 100-cycle sequence?

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In many real world situations
where the sequential logic is

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*much* faster than whatever
physical process we’re trying

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to control,

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we’ll often see the use
of bit-serial inputs where

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the information arrives as a
sequence, one bit at a time.

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That will allow us to use
much less signaling hardware,

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at the cost of the time
required to transmit

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the information sequentially.

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The FSM has some number
outputs to convey the results

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of the sequential
logic’s computations.

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The comment before about
serial vs. parallel inputs

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applies equally to choosing
how information should

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be encoded on the outputs.

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There are a set of
transition rules,

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specifying how the
next state S-prime is

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determined from the current
state S and the inputs I.

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The specification
must be complete,

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enumerating S-prime for
every possible combination

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of S and I.

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And, finally, there’s
the specification for how

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the output values
should be determined.

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The FSM design is
often a bit simpler

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if the outputs are strictly a
function of the current state

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S, but, in general,
the outputs can

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be a function of both S
and the current inputs.

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Now that we have our
abstraction in place,

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let’s see how to use it to
design our combinational lock.