6.012 | Spring 2009 | Undergraduate

Microelectronic Devices and Circuits

Pages

PROBLEM SETS
Problem set 1 (PDF)
Problem set 2 (PDF)
Problem set 3 (PDF)
Problem set 4 (PDF)
Problem set 5 (PDF)
Problem set 6 (PDF)
Problem set 7 (PDF)
Problem set 8 (PDF)
Problem set 9 (PDF)

EXAMS
Quiz 1

2005 quiz 1 (PDF)

2007 quiz 1 (PDF)

Quiz 2

2005 quiz 2 (PDF)

2007 quiz 2 (PDF)

Final Exam

2005 final exam (PDF)

2007 final exam (PDF)

Abbreviations

MOS = metal-on-silicon
MOSFET = metal-oxide-semiconductor field-effect transistor
NMOS = n-type metal-oxide-semiconductor
CMOS = complementary metal-oxide-semiconductor

LEC # TOPICS LECTURE NOTES
1

6.012 outline: grading, ethics

Overview of semiconductor applications, silicon integrated circuit technology

(PDF)
2 Intrinsic semiconductors, electrons and holes, bond model, generation recombination and thermal equilibrium; doping, donors, acceptors, compensation (PDF)
3 Carrier transport, drift velocity, drift current density, diffusion current density (PDF)
4 The p-n junction, carrier concentration and potential in thermal equilibrium, 60mV rule (PDF)
5 The p-n junction in thermal equilibrium (PDF)
6 Introduction to the MOS structure, MOS capacitor in thermal equilibrium (PDF)
7 MOS capacitor under applied bias; accumulation, depletion, and inversion regions (PDF)
8 MOSFET physical structure, circuit symbol and terminal characteristics, MOS transistor characteristics (PDF)
9 MOS transistor, backgate effect, MOSFET in saturation (PDF)
10 MOSFET small-signal model (PDF - 1.3MB)
11 Digital logic concepts, inverter characteristics, logic levels and noise margins, transient characteristics, inverter circuits, NMOS/resistor loads (PDF)
12 NMOS/current source load, CMOS inverter, static analysis (PDF)
13 CMOS inverter, propagation delay model, static CMOS gates (PDF)
14 p-n junction diode terminal characteristics, minority carrier concentration under forward and reverse bias (PDF)
15 Short base approximation, steady state diffusion equation with currents in p-n junction (PDF)
16 p-n junction diode circuit model, large signal static model, small signal model, diffusion capacitance (PDF)
17 Introduction of bipolar junction transistor, terminal characteristics, forward active bias, current gain (PDF)
18 Reverse active mode and saturation, the Ebers-Moll model (PDF)
19 Single stage amplifiers, two port small signal model, common source amplifier with resistor and current source supply (PDF)
20 Common base/gate amplifier, common collector/drain (PDF)
21 Review frequency domain analysis; current gain frequency response of common emitter amplifier (PDF)
22 Voltage gain frequency response of common emitter amplifier, full analysis of common emitter, the Miller approximation (PDF)
23 Open circuit time constant analysis, common-gate (CG) and common-drain (CD) amplifiers (PDF)
24 Multistage amplifiers, cascading small signal two port models (PDF)
25 DC coupling, voltage sources, MOS current sources, current sources and sinks (PDF)
26 Analyzing complex circuits, course wrap-up (PDF)

MIT Microelectronics WebLab

The MIT Microelectronics WebLab is a microelectronics device characterization laboratory that can be accessed through the internet. This online laboratory has been developed as part of the iLab project, under the aegis of iCampus (the MIT-Microsoft® Alliance).

MIT students and collaborating institutions can access this lab here (registration required).

Documentation about the MIT Microelectronics WebLab can be found here.

If you or your institution wishes to use this lab on a regular basis in your courses, you are encouraged to contact Prof. Jesús del Alamo at [alamo at mit dot edu].

Labs

LABS
Lab 1 (PDF)
Lab 2 (PDF)

Design Project

PROJECT FILES
Project instructions (PDF)
LTSpice quickstart guide (PDF)
HSPICE quickstart guide (PDF)
Models (SUB)

LTSpice can be downloaded from here.

The readings given below refer to sections in the course textbook:

Howe, Roger, and Charles Sodini. Microelectronics: An Integrated Approach. Upper Saddle River, NJ: Prentice Hall, 1996. ISBN: 9780135885185.

Abbreviations

MOS = metal-on-silicon
MOSFET = metal-oxide-semiconductor field-effect transistor
NMOS = n-type metal-oxide-semiconductor
CMOS = complementary metal-oxide-semiconductor

LEC # TOPICS READINGS
1

6.012 outline: grading, ethics

Overview of semiconductor applications, silicon integrated circuit technology

2.5
2 Intrinsic semiconductors, electrons and holes, bond model, generation recombination and thermal equilibrium; doping, donors, acceptors, compensation 2.1-2.2
3 Carrier transport, drift velocity, drift current density, diffusion current density 2.4
4 The p-n junction, carrier concentration and potential in thermal equilibrium, 60mV rule 3.2-3.3
5 The p-n junction in thermal equilibrium 3.4
6 Introduction to the MOS structure, MOS capacitor in thermal equilibrium 3.7
7 MOS capacitor under applied bias; accumulation, depletion, and inversion regions 3.8
8 MOSFET physical structure, circuit symbol and terminal characteristics, MOS transistor characteristics 4.1-4.3
9 MOS transistor, backgate effect, MOSFET in saturation 4.4
10 MOSFET small-signal model 4.5
11 Digital logic concepts, inverter characteristics, logic levels and noise margins, transient characteristics, inverter circuits, NMOS/resistor loads 5.1-5.2
12 NMOS/current source load, CMOS inverter, static analysis 5.3-5.4
13 CMOS inverter, propagation delay model, static CMOS gates 5.5
14 p-n junction diode terminal characteristics, minority carrier concentration under forward and reverse bias 6.1-6.3
15 Short base approximation, steady state diffusion equation with currents in p-n junction 6.3
16 p-n junction diode circuit model, large signal static model, small signal model, diffusion capacitance 6.4
17 Introduction of bipolar junction transistor, terminal characteristics, forward active bias, current gain 7.1-7.2
18 Reverse active mode and saturation, the Ebers-Moll model 7.3-7.4
19 Single stage amplifiers, two port small signal model, common source amplifier with resistor and current source supply 8.1-8.6
20 Common base/gate amplifier, common collector/drain 8.8-8.9
21 Review frequency domain analysis; current gain frequency response of common emitter amplifier 10.1-10.3
22 Voltage gain frequency response of common emitter amplifier, full analysis of common emitter, the Miller approximation 10.4
23 Open circuit time constant analysis, common-gate (CG) and common-drain (CD) amplifiers 10.5-10.6
24 Multistage amplifiers, cascading small signal two port models 9.1-9.2
25 DC coupling, voltage sources, MOS current sources, current sources and sinks 9.4
26 Analyzing complex circuits and course wrap-up 9.6 and 10.7

These recitation notes were developed by Prof. Jing Kong, and were transcribed by Pavitra Krishnaswamy.

Abbreviations

MOS = metal-on-silicon
MOSFET = metal-oxide-semiconductor field-effect transistor
CMOS = complementary metal-oxide-semiconductor
BJT = bipolar junction transmitter

REC # TOPICS RECITATION NOTES
1 Integrated circuit technology (PDF)
2 Equilibrium electron and hole concentration from doping (PDF)
3 Carrier action (PDF)
4 Electrostatic potential and carrier concentration (PDF)
5 Review of electrostatics (PDF)
6 p-n junction (PDF)
7 From n+p diode to MOS structure (PDF)
8 MOS electrostatics under bias, MOS capacitor (PDF)
9 MOSFET V-I characteristics (PDF)
10 MOSFET V-I characteristics: channel length modulation and back gate effect (PDF)
11 Small signal model of MOSFET, MOSFET in digital circuits (PDF)
12 CMOS noise margin (PDF)
13 Propagation delay, NAND/NOR gates (PDF)
14 p-n diode I-V characteristics (I) (PDF)
15 p-n diode I-V characteristics (II) (PDF)
16 Small signal model of p-n diode (PDF)
17 BJT: basic operation in forward-active regime (PDF)
18 BJT: regions of operation, small signal model (PDF)
19 Common emitter amplifier (PDF)
20 Amplifiers review (PDF)
21 Intrinsic frequency response of common source (CS) and common emitter (CE) amplifier (PDF)
22 CS amplifier frequency response (PDF)
23 Frequency response of common collector (CC) and common base (CB) amplifier (PDF)
24 BiCMOS cascode amplifier (PDF)
25 CMOS cascade amplifier (PDF)

Course Meeting Times

Lectures: 2 sessions / week, 1 hour / session

Recitations: 2 sessions / week, 1 hour / session

Tutorials: 1 session / week, 1 hour / session

Required Text

Howe, Roger, and Charles Sodini. Microelectronics: An Integrated Approach. Upper Saddle River, NJ: Prentice Hall, 1996. ISBN: 9780135885185.

Reference Texts

Fonstad, Clifton. Microelectronic Devices and Circuits. New York, NY: McGraw-Hill, 1994. ISBN: 9780070214965.

Sedra, Adel, and Kenneth Smith. Microelectronic Circuits. New York, NY: Oxford University Press, 2007. ISBN: 9780195338836.

Horenstein, Mark. Microelectronic Circuits and Devices. New York, NY: Pearson, 1996. ISBN: 9780536846761.

Modular Series on Solid State Devices

Pierret, Robert. Semiconductor Fundamentals. Vol. I. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 1988. ISBN: 9780201122954.

Neudeck, George. The PN Junction Diode. Vol. II. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 1988. ISBN: 9780201122961.

———. The Bipolar Junction Transistor. Vol. III. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 1989. ISBN: 9780201122978.

Pierret, Robert. Field Effect Devices. Vol. IV. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 1990. ISBN: 9780201122985.

Grading

All the items below will enter into the computation of the final grade.

Quizzes

Two two-hour evening quizzes, open book, calculator required.

Final Exam

Three hours, open book, calculator required.

Homework

A total of eight problem sets will be handed out. The homework must be turned in by 4pm sharp on the due date. A 50% penalty will be applied to homework turned in after 4pm. Homework turned in after solutions are distributed (about 3 days later) will be graded, but no credit will be given. All exceptions to this policy have to be approved by the lecturer. All homework sets will weigh equally towards the final grade.

Design Problem and Web Labs

The design problem will be handed out one day after L12 and will be due one day after L17. There will also be two Web labs that will introduce you to real live device characterization. If you turn in the design problem or any of the Web labs after its due date, the same policy as late homework applies.

Attendance

We expect students to attend lectures and recitations, and we will keep track of attendance. The attendance record will be counted for 10% of the final grade.

The course grade will be determined as follows:

ACTIVITIES PERCENTAGES
Quiz 1 15%
Quiz 2 15%
Final exam 30%
Homework 10%
Design problem and web labs 20%
Attendance 10%

The final letter grade will also take into consideration non-numerical assessments of your command of the subject matter as evaluated by the lecturer, instructors, and TAs.

Policy for Academic Conduct (PDF)

Students attended one-hour weekly tutorial sessions. The following materials were used as in-class problems.

TUTORIALS
Tutorial 1 (PDF)
Tutorial 2 (PDF)
Tutorial 3 (PDF)
Tutorial 4 (PDF)
Tutorial 5 (PDF)
Tutorial 6 (PDF)
Tutorial 7 (PDF)
Tutorial 8 (PDF)
Tutorial 9 (PDF)
Tutorial 10 (PDF)
Tutorial 11 (PDF)
Tutorial 12 (PDF)
Learning Resource Types
Problem Sets
Exams
Lecture Notes
Projects