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We have two programs to test the
board. They are intended to verify the operation of the CPLD as well as the
connections between the 50-pin connector and the logic analyzer.
Driver: This program loads a 31 bit counter that
is displayed on the NuBus LED's.
Reader: This program reads the first 25 I/O lines
of the NuBus connector and extends them to the 50-pin connector .
The output of the first 25 bits
of the NuBus can therefore be seen on the Logic Analyzer. The remaining 6 bits
on the NuBus can be directly probed by the scope.
The
above files along with an empty pre-numbered VHDL file (374sample.vhd) can be
found at /mit/6.111/cpld/sources/test/