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Interface
25 I/O pins are interconnected
among the 4 CPLD's and the 50-pin connector. The signals of the 50-pin
connector interface directly to the logic analyzer via the connector on the
kit. Table 2 provides details of these interconnections. Logic Blocks are
partitions internal to the CPLD chip. This information, at times, can be useful
during device fitting.
Table 2: 50-pin Connector Interface
Note: If you use K1, then
IO-53 must not be used. Similarly, if you use K2, then IO-11 must not be used.