WEBVTT 00:00:00.000 --> 00:00:01.996 align:middle line:90% [SQUEAKING] 00:00:01.996 --> 00:00:03.992 align:middle line:90% [RUSTLING] 00:00:03.992 --> 00:00:09.290 align:middle line:90% [CLICKING] 00:00:09.290 --> 00:00:11.390 align:middle line:84% PROFESSOR: So what I'd like to do today 00:00:11.390 --> 00:00:15.620 align:middle line:84% is talk about an entirely different class 00:00:15.620 --> 00:00:19.040 align:middle line:84% of switching power converter than we've talked about before. 00:00:19.040 --> 00:00:22.010 align:middle line:90% And we are going to-- 00:00:22.010 --> 00:00:24.800 align:middle line:90% 00:00:24.800 --> 00:00:30.180 align:middle line:84% we are going to look at-- for this class and next class, 00:00:30.180 --> 00:00:33.520 align:middle line:84% we're going to talk about switched capacitor converters. 00:00:33.520 --> 00:00:42.620 align:middle line:90% 00:00:42.620 --> 00:00:47.755 align:middle line:84% And that's Principles of Power Electronics chapter six. 00:00:47.755 --> 00:00:53.720 align:middle line:90% 00:00:53.720 --> 00:00:58.250 align:middle line:84% Most converters introduce magnetics in them. 00:00:58.250 --> 00:01:00.078 align:middle line:84% They have some magnetic component in them. 00:01:00.078 --> 00:01:00.870 align:middle line:90% Why do you want it? 00:01:00.870 --> 00:01:03.860 align:middle line:84% Why do you want, say, an inductor or an inductive energy 00:01:03.860 --> 00:01:05.370 align:middle line:84% storage element in your converter? 00:01:05.370 --> 00:01:09.048 align:middle line:84% That's because if I put a voltage difference across it, 00:01:09.048 --> 00:01:11.340 align:middle line:84% from, say, an input voltage or an output voltage or two 00:01:11.340 --> 00:01:15.000 align:middle line:84% voltages, the inductor can instantaneously 00:01:15.000 --> 00:01:18.540 align:middle line:84% take that energy difference, absorb the voltage difference, 00:01:18.540 --> 00:01:20.980 align:middle line:84% absorb energy, then we can recover later. 00:01:20.980 --> 00:01:23.115 align:middle line:84% And that's the principle we operate on. 00:01:23.115 --> 00:01:24.990 align:middle line:84% And that's why almost all of these converters 00:01:24.990 --> 00:01:30.660 align:middle line:84% use magnetics or something that acts like a magnetic component. 00:01:30.660 --> 00:01:33.000 align:middle line:84% On the other hand, sometimes, you 00:01:33.000 --> 00:01:37.360 align:middle line:84% can get away without any magnetic components, 00:01:37.360 --> 00:01:39.260 align:middle line:84% without any inductors in your circuit. 00:01:39.260 --> 00:01:41.420 align:middle line:84% And why might you want to do that? 00:01:41.420 --> 00:01:43.600 align:middle line:84% Well, because if you look at things 00:01:43.600 --> 00:01:47.860 align:middle line:84% that are on the scale of my thumb or something, 00:01:47.860 --> 00:01:50.830 align:middle line:84% some small element, the energy density 00:01:50.830 --> 00:01:55.000 align:middle line:84% you can achieve with a capacitor is orders of magnitude 00:01:55.000 --> 00:01:56.500 align:middle line:84% higher than the energy density you 00:01:56.500 --> 00:01:58.540 align:middle line:84% can achieve with a magnetic component 00:01:58.540 --> 00:02:02.560 align:middle line:84% at similar efficiencies and energy storage levels. 00:02:02.560 --> 00:02:07.490 align:middle line:84% So capacitors are just extremely highly energy dense. 00:02:07.490 --> 00:02:10.600 align:middle line:84% So if I happen to have an application where I can get away 00:02:10.600 --> 00:02:13.120 align:middle line:84% with only capacitive energy storage, 00:02:13.120 --> 00:02:16.980 align:middle line:84% you can build a much smaller, more efficient converter. 00:02:16.980 --> 00:02:20.350 align:middle line:84% But that application space is limited. 00:02:20.350 --> 00:02:22.460 align:middle line:90% And we're going to get into why. 00:02:22.460 --> 00:02:25.150 align:middle line:84% So switch capacitor converters are essentially-- 00:02:25.150 --> 00:02:28.000 align:middle line:84% to come back to their definition-- are essentially 00:02:28.000 --> 00:02:32.060 align:middle line:84% converters where I process all my energy using capacitors. 00:02:32.060 --> 00:02:33.730 align:middle line:84% And so I have capacitors and switches 00:02:33.730 --> 00:02:35.480 align:middle line:90% to do the energy throughput. 00:02:35.480 --> 00:02:37.570 align:middle line:84% I've brought a couple of examples with these. 00:02:37.570 --> 00:02:41.460 align:middle line:84% These are both kind of prototype designs. 00:02:41.460 --> 00:02:46.110 align:middle line:84% This one is a very small power, low power one. 00:02:46.110 --> 00:02:47.780 align:middle line:84% You'll see much of it on the front, 00:02:47.780 --> 00:02:50.310 align:middle line:84% and it has some energy storage capacitors on the back. 00:02:50.310 --> 00:02:54.740 align:middle line:84% This is another overall circuit, and this part over here 00:02:54.740 --> 00:02:58.230 align:middle line:84% is a switch capacitor converter of a certain type. 00:02:58.230 --> 00:03:01.340 align:middle line:84% So just to illustrate what we're talking about, 00:03:01.340 --> 00:03:03.620 align:middle line:90% you can take a look at these. 00:03:03.620 --> 00:03:11.690 align:middle line:84% And so in order to illustrate their strengths and weaknesses, 00:03:11.690 --> 00:03:15.200 align:middle line:84% let's look at the simplest switch capacitor 00:03:15.200 --> 00:03:16.860 align:middle line:90% converter I can think of. 00:03:16.860 --> 00:03:20.480 align:middle line:84% And this is sometimes known as a 2-to-1 step-down converter, 00:03:20.480 --> 00:03:25.130 align:middle line:84% although we'll come back to why people call it that, 00:03:25.130 --> 00:03:28.110 align:middle line:90% but what its tradeoffs are. 00:03:28.110 --> 00:03:29.680 align:middle line:90% So here's the idea. 00:03:29.680 --> 00:03:37.010 align:middle line:84% Suppose I had some input voltage from which 00:03:37.010 --> 00:03:42.000 align:middle line:84% I'm going to draw power, and I'm going to have a capacitor here. 00:03:42.000 --> 00:03:46.770 align:middle line:84% And this capacitor is my energy transfer capacitor. 00:03:46.770 --> 00:03:49.650 align:middle line:90% So here c, ic, and vc. 00:03:49.650 --> 00:03:52.340 align:middle line:84% So, in this example I'm going to do, 00:03:52.340 --> 00:03:55.880 align:middle line:84% this element is where I'm storing 00:03:55.880 --> 00:03:58.850 align:middle line:84% the energy in the intermediate form 00:03:58.850 --> 00:04:01.340 align:middle line:90% to do this energy processing. 00:04:01.340 --> 00:04:03.640 align:middle line:90% So I'll have switches. 00:04:03.640 --> 00:04:06.770 align:middle line:90% 00:04:06.770 --> 00:04:10.035 align:middle line:84% And then I will have delivered to some output. 00:04:10.035 --> 00:04:11.660 align:middle line:84% And I'm going to call this c big-- this 00:04:11.660 --> 00:04:14.090 align:middle line:90% is like my filter capacitor. 00:04:14.090 --> 00:04:17.820 align:middle line:84% And then, here, I have some output current. 00:04:17.820 --> 00:04:21.410 align:middle line:90% This is the load current. 00:04:21.410 --> 00:04:26.810 align:middle line:90% And this is v out. 00:04:26.810 --> 00:04:33.620 align:middle line:84% So I'm going to have these two capacitors, these two switches, 00:04:33.620 --> 00:04:37.400 align:middle line:84% and these are phase one switches. 00:04:37.400 --> 00:04:39.870 align:middle line:84% Then I'm going to put two more switches in. 00:04:39.870 --> 00:04:42.620 align:middle line:84% I'm going to call these phase two switches. 00:04:42.620 --> 00:04:47.660 align:middle line:84% So here's one, one, and two, two. 00:04:47.660 --> 00:04:51.140 align:middle line:84% And the idea here is that we're going 00:04:51.140 --> 00:04:56.240 align:middle line:84% to alternately take the switches that are labeled 1 00:04:56.240 --> 00:04:58.138 align:middle line:90% and close them together. 00:04:58.138 --> 00:04:59.930 align:middle line:84% And then, at some other point in the cycle, 00:04:59.930 --> 00:05:01.347 align:middle line:84% we're going to open those switches 00:05:01.347 --> 00:05:03.583 align:middle line:84% and close the switches that are labeled 2 together. 00:05:03.583 --> 00:05:05.000 align:middle line:84% And what you're going to see-- one 00:05:05.000 --> 00:05:06.920 align:middle line:84% of the characteristics of switched capacitor converters, 00:05:06.920 --> 00:05:08.640 align:middle line:84% they tend to have a lot of switches. 00:05:08.640 --> 00:05:10.790 align:middle line:84% And, in fact, if you want high conversion ratios, 00:05:10.790 --> 00:05:12.873 align:middle line:84% they have lots of switches and lots of capacitors. 00:05:12.873 --> 00:05:14.610 align:middle line:84% We'll talk about that a little bit more. 00:05:14.610 --> 00:05:19.350 align:middle line:84% So this beast in the box here, if you will-- 00:05:19.350 --> 00:05:22.130 align:middle line:84% I don't know, you can include the output capacitor, 00:05:22.130 --> 00:05:23.270 align:middle line:90% I suppose-- 00:05:23.270 --> 00:05:29.626 align:middle line:84% is the simplest switch capacitor or converter I can think of. 00:05:29.626 --> 00:05:32.650 align:middle line:84% To analyze it, let me just simplify it. 00:05:32.650 --> 00:05:35.588 align:middle line:84% I'm going to think about this as a really big output capacitor. 00:05:35.588 --> 00:05:37.380 align:middle line:84% So for the moment, let me just replace them 00:05:37.380 --> 00:05:39.870 align:middle line:90% with a voltage source v out. 00:05:39.870 --> 00:05:46.830 align:middle line:84% So for my analysis, I'm going to simplify this just a little, 00:05:46.830 --> 00:05:51.290 align:middle line:84% and I'll say we have an input voltage v in. 00:05:51.290 --> 00:05:56.550 align:middle line:90% 00:05:56.550 --> 00:06:05.710 align:middle line:84% Here's my capacitor vc, ic, c, my two switches. 00:06:05.710 --> 00:06:11.160 align:middle line:84% I'm just going to replace this with an output voltage, v out. 00:06:11.160 --> 00:06:18.630 align:middle line:84% And then I'm going to have this is switch 1, switch 1, switch 00:06:18.630 --> 00:06:24.720 align:middle line:90% 2, and switch 2. 00:06:24.720 --> 00:06:29.230 align:middle line:84% And this is the circuit we're going to analyze. 00:06:29.230 --> 00:06:38.390 align:middle line:84% So in state 1, I basically have these two switches closed. 00:06:38.390 --> 00:06:41.590 align:middle line:84% So in state 1, the converter looks like this-- 00:06:41.590 --> 00:06:42.330 align:middle line:90% v in. 00:06:42.330 --> 00:06:44.890 align:middle line:90% 00:06:44.890 --> 00:06:46.850 align:middle line:84% Our first switch is going to be on. 00:06:46.850 --> 00:06:48.560 align:middle line:90% I'll call that R switch. 00:06:48.560 --> 00:06:51.756 align:middle line:84% Then I'm going to have my capacitor. 00:06:51.756 --> 00:06:57.970 align:middle line:90% 00:06:57.970 --> 00:07:01.115 align:middle line:84% And then I'm going to have my second switch. 00:07:01.115 --> 00:07:02.865 align:middle line:84% And then that's going to go to the output. 00:07:02.865 --> 00:07:05.930 align:middle line:90% 00:07:05.930 --> 00:07:09.575 align:middle line:84% And in my second state, state 2-- 00:07:09.575 --> 00:07:12.980 align:middle line:90% 00:07:12.980 --> 00:07:15.266 align:middle line:84% the input's now going to be disconnected. 00:07:15.266 --> 00:07:21.590 align:middle line:90% 00:07:21.590 --> 00:07:34.390 align:middle line:84% But I am going to connect my capacitor through a resistor 00:07:34.390 --> 00:07:40.695 align:middle line:90% to the output, like this. 00:07:40.695 --> 00:07:46.250 align:middle line:90% 00:07:46.250 --> 00:07:51.110 align:middle line:84% Any questions about the two switch configurations? 00:07:51.110 --> 00:07:52.610 align:middle line:84% Let's just, for simplicity, assume 00:07:52.610 --> 00:07:55.040 align:middle line:84% I'm going to flop back and forth at 50% duty 00:07:55.040 --> 00:07:57.560 align:middle line:84% cycle between these two states, although we'll see, 00:07:57.560 --> 00:07:59.400 align:middle line:84% in some cases, the duty cycle matters. 00:07:59.400 --> 00:08:01.160 align:middle line:90% In some cases it doesn't. 00:08:01.160 --> 00:08:03.490 align:middle line:90% All right, any questions? 00:08:03.490 --> 00:08:03.990 align:middle line:90% Yeah? 00:08:03.990 --> 00:08:06.300 align:middle line:84% AUDIENCE: So in this case, we can't 00:08:06.300 --> 00:08:07.980 align:middle line:90% deal with [INAUDIBLE] switches. 00:08:07.980 --> 00:08:12.270 align:middle line:84% We have to think about the [INAUDIBLE]. 00:08:12.270 --> 00:08:15.990 align:middle line:84% PROFESSOR: It helps to think about the parasitic resistance 00:08:15.990 --> 00:08:18.307 align:middle line:84% because we were going to worry about how much energy we 00:08:18.307 --> 00:08:19.390 align:middle line:90% dissipate in the switches. 00:08:19.390 --> 00:08:21.630 align:middle line:84% But if I let the switch resistances go to 0, 00:08:21.630 --> 00:08:24.730 align:middle line:84% the answer doesn't change, actually. 00:08:24.730 --> 00:08:29.960 align:middle line:84% So, yeah, we'll come back to that point. 00:08:29.960 --> 00:08:34.880 align:middle line:84% So let's think about this now in order to analyze this. 00:08:34.880 --> 00:08:38.630 align:middle line:84% What I'd like to do is focus on-- 00:08:38.630 --> 00:08:42.860 align:middle line:90% here, I have v in. 00:08:42.860 --> 00:08:45.020 align:middle line:90% Here's v in. 00:08:45.020 --> 00:08:49.610 align:middle line:84% Let me talk about the current i in going into v in. 00:08:49.610 --> 00:08:53.810 align:middle line:90% And here, I have v out. 00:08:53.810 --> 00:08:57.110 align:middle line:90% And here's i out. 00:08:57.110 --> 00:09:01.970 align:middle line:90% And then I have vc and ic. 00:09:01.970 --> 00:09:04.350 align:middle line:84% I guess I should have drawn this on the main circuit. 00:09:04.350 --> 00:09:19.160 align:middle line:84% So this is v in, i in, v out, i out, and vc, ic. 00:09:19.160 --> 00:09:23.660 align:middle line:90% 00:09:23.660 --> 00:09:30.590 align:middle line:84% And what I would like to do is track the charge 00:09:30.590 --> 00:09:33.320 align:middle line:90% flowing through this converter. 00:09:33.320 --> 00:09:35.540 align:middle line:84% which is going to let me understand 00:09:35.540 --> 00:09:37.490 align:middle line:90% what its conversion ratio is. 00:09:37.490 --> 00:09:41.900 align:middle line:84% And analyzing any switch capacitor converter more or less 00:09:41.900 --> 00:09:44.100 align:middle line:84% comes down to the process I'm following. 00:09:44.100 --> 00:09:47.120 align:middle line:84% There are ways that we can organize 00:09:47.120 --> 00:09:49.860 align:middle line:90% it to do the general case. 00:09:49.860 --> 00:09:52.850 align:middle line:84% But let's just think about this case. 00:09:52.850 --> 00:09:54.650 align:middle line:84% And what I'm going to think about 00:09:54.650 --> 00:10:00.050 align:middle line:84% is let's suppose that when I close the switches 00:10:00.050 --> 00:10:01.910 align:middle line:84% and I have some switch resistances, 00:10:01.910 --> 00:10:03.180 align:middle line:90% the values don't matter. 00:10:03.180 --> 00:10:08.300 align:middle line:84% But let's ask what does the final voltage of the capacitor 00:10:08.300 --> 00:10:09.420 align:middle line:90% end up at? 00:10:09.420 --> 00:10:11.480 align:middle line:84% So at the end of state 1, what I'm 00:10:11.480 --> 00:10:13.910 align:middle line:84% going to assume for my first analysis-- 00:10:13.910 --> 00:10:16.790 align:middle line:84% and this is what's known as the slow switching limit-- 00:10:16.790 --> 00:10:21.260 align:middle line:84% is that I close my switches, and this capacitor 00:10:21.260 --> 00:10:25.490 align:middle line:84% charges to some final value and then stops charging. 00:10:25.490 --> 00:10:29.040 align:middle line:84% So what would be the final value of the capacitor in this state 00:10:29.040 --> 00:10:30.810 align:middle line:90% 1? 00:10:30.810 --> 00:10:39.800 align:middle line:84% So vc at the-- and state 1 at the end. 00:10:39.800 --> 00:10:41.770 align:middle line:90% What voltage would vc charge to? 00:10:41.770 --> 00:10:46.190 align:middle line:90% 00:10:46.190 --> 00:10:47.940 align:middle line:90% Has to be v in minus v out. 00:10:47.940 --> 00:10:51.990 align:middle line:90% 00:10:51.990 --> 00:11:00.240 align:middle line:84% And in state 2, at the end, correspondingly, vc 00:11:00.240 --> 00:11:03.510 align:middle line:90% has to go to v out. 00:11:03.510 --> 00:11:10.080 align:middle line:84% So the idea is if I looked at what vc was going to do, 00:11:10.080 --> 00:11:13.650 align:middle line:84% it's going to start off when I enter state 1-- 00:11:13.650 --> 00:11:16.680 align:middle line:84% or [INAUDIBLE] state 2 I'm going to be at v out. 00:11:16.680 --> 00:11:19.320 align:middle line:84% I'm going to flip my switches, and then vc 00:11:19.320 --> 00:11:22.200 align:middle line:84% is going to charge to v in minus v out. 00:11:22.200 --> 00:11:23.860 align:middle line:84% And I'm going to switch my switches. 00:11:23.860 --> 00:11:27.210 align:middle line:84% Then, vc is going to discharge in this case back to v out 00:11:27.210 --> 00:11:29.610 align:middle line:90% and it's going to repeat. 00:11:29.610 --> 00:11:30.960 align:middle line:90% That makes sense to everybody? 00:11:30.960 --> 00:11:35.715 align:middle line:84% So I'm assuming-- and this is the slow switching limit-- 00:11:35.715 --> 00:11:40.440 align:middle line:90% 00:11:40.440 --> 00:11:45.180 align:middle line:84% that what my capacitor voltage is going to do versus time-- 00:11:45.180 --> 00:11:53.400 align:middle line:84% if this is state 1 and this is state 2, 00:11:53.400 --> 00:11:55.470 align:middle line:84% I'm going to basically-- my capacitor is 00:11:55.470 --> 00:12:03.910 align:middle line:84% going to charge from v out up to v in minus v out. 00:12:03.910 --> 00:12:06.723 align:middle line:84% And then it's going to charge from v in minus v 00:12:06.723 --> 00:12:08.140 align:middle line:84% out, down to v out, and it's going 00:12:08.140 --> 00:12:12.320 align:middle line:84% to do something like this with some Rc time constant. 00:12:12.320 --> 00:12:15.010 align:middle line:84% And so I'm just assuming-- so this is going to-- 00:12:15.010 --> 00:12:17.320 align:middle line:84% at the end of state 1, it's going to v in minus v out. 00:12:17.320 --> 00:12:21.520 align:middle line:90% 00:12:21.520 --> 00:12:23.920 align:middle line:84% And then, in the next state, in state 2, 00:12:23.920 --> 00:12:27.340 align:middle line:90% it's going to charge to v out. 00:12:27.340 --> 00:12:30.730 align:middle line:84% So my only assumption is I'm going to-- each cycle, 00:12:30.730 --> 00:12:32.920 align:middle line:84% I'm going to charge up, I'm going to charge down, 00:12:32.920 --> 00:12:34.940 align:middle line:84% and I'm going to finish the charging. 00:12:34.940 --> 00:12:36.730 align:middle line:84% I'm going to let this Rc time constant 00:12:36.730 --> 00:12:40.120 align:middle line:90% go to where he's fully charged. 00:12:40.120 --> 00:12:45.050 align:middle line:84% So let's think about how much charge 00:12:45.050 --> 00:12:47.210 align:middle line:90% I transfer in each component. 00:12:47.210 --> 00:12:55.260 align:middle line:90% In state 1, what do I have? 00:12:55.260 --> 00:12:59.420 align:middle line:90% Delta qc in state 1-- 00:12:59.420 --> 00:13:03.410 align:middle line:84% the amount of charge that gets put onto the capacitor 00:13:03.410 --> 00:13:04.380 align:middle line:90% in state 1. 00:13:04.380 --> 00:13:05.630 align:middle line:90% Well, what's that going to be? 00:13:05.630 --> 00:13:07.220 align:middle line:90% That's going to be equal to-- 00:13:07.220 --> 00:13:13.700 align:middle line:84% delta q is c delta v, which is going 00:13:13.700 --> 00:13:18.510 align:middle line:84% to be c times the change in voltage across state 1. 00:13:18.510 --> 00:13:21.800 align:middle line:84% He's starting at v out, and he's going up to v in minus v out. 00:13:21.800 --> 00:13:26.510 align:middle line:84% So it's going to be v in minus v out minus v out is going to be 00:13:26.510 --> 00:13:30.060 align:middle line:90% c times v in minus 2 v out. 00:13:30.060 --> 00:13:32.840 align:middle line:90% 00:13:32.840 --> 00:13:39.500 align:middle line:84% So that's how much charge gets put on to this capacitor 00:13:39.500 --> 00:13:44.070 align:middle line:84% during state 1 in periodic steady state. 00:13:44.070 --> 00:13:45.840 align:middle line:90% Any questions about that? 00:13:45.840 --> 00:13:48.460 align:middle line:84% Because the rest of the analysis proceeds just like this. 00:13:48.460 --> 00:13:53.350 align:middle line:84% So I want to make sure people get what I'm calculating. 00:13:53.350 --> 00:13:56.542 align:middle line:84% NPSS-- I charge and discharge between two points. 00:13:56.542 --> 00:13:58.000 align:middle line:84% And I'm just saying how much charge 00:13:58.000 --> 00:14:02.110 align:middle line:84% went on to the capacitor in state 1, and that's it. 00:14:02.110 --> 00:14:10.970 align:middle line:84% Well, how much charge went into the input in state 1? 00:14:10.970 --> 00:14:14.150 align:middle line:84% Well, the way I've defined it here, the input-- 00:14:14.150 --> 00:14:17.000 align:middle line:84% and I've defined here because the general analysis 00:14:17.000 --> 00:14:18.470 align:middle line:90% tend to do it this way-- 00:14:18.470 --> 00:14:20.717 align:middle line:84% is the current going in the capacitor 00:14:20.717 --> 00:14:22.550 align:middle line:84% is exactly the opposite of the current going 00:14:22.550 --> 00:14:23.790 align:middle line:90% into the input in state 1. 00:14:23.790 --> 00:14:27.440 align:middle line:84% So the current-- the charge into the input 00:14:27.440 --> 00:14:28.690 align:middle line:90% just has to be the opposite. 00:14:28.690 --> 00:14:35.270 align:middle line:84% This is going to be minus c v in minus 2 v out. 00:14:35.270 --> 00:14:39.950 align:middle line:84% And likewise, the charge that got transferred into the output 00:14:39.950 --> 00:14:43.310 align:middle line:84% during state 1 is exactly equal to the charge 00:14:43.310 --> 00:14:45.780 align:middle line:84% in the capacity that transferred onto the capacitor. 00:14:45.780 --> 00:14:53.600 align:middle line:84% And I get delta q out in state 1 is equal to c v in minus 2 00:14:53.600 --> 00:14:54.180 align:middle line:90% v out. 00:14:54.180 --> 00:14:57.230 align:middle line:90% 00:14:57.230 --> 00:15:00.510 align:middle line:84% Does that make sense to everybody? 00:15:00.510 --> 00:15:03.890 align:middle line:90% Any questions? 00:15:03.890 --> 00:15:05.440 align:middle line:90% Let's think about state 2. 00:15:05.440 --> 00:15:11.950 align:middle line:90% 00:15:11.950 --> 00:15:16.930 align:middle line:84% Delta q c-- how much charge goes on the capacitor in state 2 00:15:16.930 --> 00:15:19.670 align:middle line:90% is equal to c delta v? 00:15:19.670 --> 00:15:22.960 align:middle line:84% Well, in state 2, I started at v in minus v out, 00:15:22.960 --> 00:15:24.550 align:middle line:90% and I ended at v out. 00:15:24.550 --> 00:15:27.700 align:middle line:84% So it's going to be v in minus v out, 00:15:27.700 --> 00:15:31.490 align:middle line:84% minus v out is what I'm going to get. 00:15:31.490 --> 00:15:40.975 align:middle line:84% But keep in mind that I could write this-- 00:15:40.975 --> 00:15:44.800 align:middle line:90% 00:15:44.800 --> 00:15:46.300 align:middle line:84% the charge that's going to-- he's 00:15:46.300 --> 00:15:50.690 align:middle line:84% going to end up at v out minus v in minus v out. 00:15:50.690 --> 00:15:53.120 align:middle line:84% So it's v out minus v in minus v out. 00:15:53.120 --> 00:15:56.020 align:middle line:90% It's 2 v out minus v in times c. 00:15:56.020 --> 00:16:06.820 align:middle line:84% But I could write that as minus c times v in minus 2 v out. 00:16:06.820 --> 00:16:09.482 align:middle line:84% And the reason I'm going to write-- first of all, 00:16:09.482 --> 00:16:10.940 align:middle line:84% does everybody get what I just did? 00:16:10.940 --> 00:16:16.450 align:middle line:84% All I did was I just expressed it as a with a minus sign 00:16:16.450 --> 00:16:16.950 align:middle line:90% out here. 00:16:16.950 --> 00:16:18.325 align:middle line:84% I pulled the minus sign out here. 00:16:18.325 --> 00:16:19.970 align:middle line:84% Why did I pull the minus sign out here? 00:16:19.970 --> 00:16:24.580 align:middle line:84% Because I want to emphasize that this is going 00:16:24.580 --> 00:16:26.800 align:middle line:90% to be a negative net charge. 00:16:26.800 --> 00:16:30.190 align:middle line:84% Or another way I ought to think about it is, look, 00:16:30.190 --> 00:16:33.910 align:middle line:84% I'm running this converter back and forth between state 1 00:16:33.910 --> 00:16:35.930 align:middle line:84% and state 2 in periodic steady state. 00:16:35.930 --> 00:16:39.880 align:middle line:84% What is the net charge that I'm going 00:16:39.880 --> 00:16:42.010 align:middle line:84% to transfer through the capacitor 00:16:42.010 --> 00:16:45.010 align:middle line:90% in periodic steady state? 00:16:45.010 --> 00:16:46.540 align:middle line:90% 0. 00:16:46.540 --> 00:16:51.850 align:middle line:84% So that means that delta q c 1 is a charge transferred 00:16:51.850 --> 00:16:54.975 align:middle line:84% onto the capacitor in state 1 plus delta q, c 2, 00:16:54.975 --> 00:16:57.100 align:middle line:84% the charge transfer onto the capacitor in state 2-- 00:16:57.100 --> 00:16:58.400 align:middle line:90% better add to 0. 00:16:58.400 --> 00:17:00.760 align:middle line:84% And you can see that it does if I write it this way. 00:17:00.760 --> 00:17:05.089 align:middle line:84% It's c v in minus 2 v out plus minus c v in minus 2 v out. 00:17:05.089 --> 00:17:06.339 align:middle line:90% So they add to 0. 00:17:06.339 --> 00:17:08.440 align:middle line:84% So indeed, if I made the assumption 00:17:08.440 --> 00:17:11.800 align:middle line:84% that it's charged to its initial and final states, 00:17:11.800 --> 00:17:15.130 align:middle line:84% this does satisfy the periodic steady state requirements 00:17:15.130 --> 00:17:16.910 align:middle line:90% on the capacitor. 00:17:16.910 --> 00:17:20.220 align:middle line:90% Any questions about that? 00:17:20.220 --> 00:17:21.599 align:middle line:90% So let's just say-- 00:17:21.599 --> 00:17:27.110 align:middle line:84% what happens-- what's delta q in in state 2? 00:17:27.110 --> 00:17:30.420 align:middle line:90% 00:17:30.420 --> 00:17:31.505 align:middle line:90% Anybody tell me that? 00:17:31.505 --> 00:17:34.700 align:middle line:90% 00:17:34.700 --> 00:17:36.500 align:middle line:90% This is v in. 00:17:36.500 --> 00:17:38.450 align:middle line:90% This is i in. 00:17:38.450 --> 00:17:43.870 align:middle line:84% How much charge is transferred into the input in state 2? 00:17:43.870 --> 00:17:44.710 align:middle line:90% AUDIENCE: None. 00:17:44.710 --> 00:17:48.670 align:middle line:84% PROFESSOR: 0-- no charge transferred in the input. 00:17:48.670 --> 00:17:55.630 align:middle line:84% How much charge is transferred to the output in state 2? 00:17:55.630 --> 00:17:58.280 align:middle line:90% 00:17:58.280 --> 00:18:04.190 align:middle line:84% Well, this is-- let's be careful about signs here-- 00:18:04.190 --> 00:18:05.430 align:middle line:90% here's v out. 00:18:05.430 --> 00:18:07.070 align:middle line:90% Here's i out. 00:18:07.070 --> 00:18:11.180 align:middle line:84% The negative of the capacitor current 00:18:11.180 --> 00:18:12.510 align:middle line:90% is going into the output. 00:18:12.510 --> 00:18:14.840 align:middle line:84% So whatever charge went into the capacitor, 00:18:14.840 --> 00:18:17.400 align:middle line:84% the negative of that charge went into the output. 00:18:17.400 --> 00:18:25.800 align:middle line:84% So delta q out 2 must be positive c v in minus 2 v out. 00:18:25.800 --> 00:18:28.840 align:middle line:90% 00:18:28.840 --> 00:18:32.490 align:middle line:84% Does that make sense to everybody? 00:18:32.490 --> 00:18:36.090 align:middle line:90% So what is the-- 00:18:36.090 --> 00:18:39.390 align:middle line:84% we know that the net total charge transferred 00:18:39.390 --> 00:18:42.480 align:middle line:84% on this energy storage capacitor in periodic steady state better 00:18:42.480 --> 00:18:43.500 align:middle line:90% be 0. 00:18:43.500 --> 00:18:46.210 align:middle line:84% But that's not true of the input or the output. 00:18:46.210 --> 00:18:49.770 align:middle line:84% So why don't we just find out what that is? 00:18:49.770 --> 00:19:02.880 align:middle line:84% We could then write delta q in is equal to q in state 1 plus 00:19:02.880 --> 00:19:07.890 align:middle line:84% delta q in in state 2 And if I just add those up, 00:19:07.890 --> 00:19:15.330 align:middle line:84% that's going to be 2 c v in minus 2 v out. 00:19:15.330 --> 00:19:21.660 align:middle line:84% And delta q out is going to be equal to delta q 00:19:21.660 --> 00:19:28.060 align:middle line:84% out in state 1 and delta q out in state 2. 00:19:28.060 --> 00:19:36.430 align:middle line:84% And if I add those up, it's going to be minus c v in minus 2 00:19:36.430 --> 00:19:38.860 align:middle line:90% v out. 00:19:38.860 --> 00:19:44.750 align:middle line:84% Now what's the current at the input on average? 00:19:44.750 --> 00:19:45.635 align:middle line:90% Yeah? 00:19:45.635 --> 00:19:50.480 align:middle line:84% AUDIENCE: Are these flipped, [INAUDIBLE]? 00:19:50.480 --> 00:19:52.215 align:middle line:90% PROFESSOR: Yes, thank you. 00:19:52.215 --> 00:19:54.780 align:middle line:90% 00:19:54.780 --> 00:19:57.040 align:middle line:90% How did I do that? 00:19:57.040 --> 00:20:00.015 align:middle line:84% Well, it's easier to do it this way. 00:20:00.015 --> 00:20:04.450 align:middle line:90% 00:20:04.450 --> 00:20:05.560 align:middle line:90% Thank you. 00:20:05.560 --> 00:20:07.930 align:middle line:90% Somebody's watching. 00:20:07.930 --> 00:20:13.840 align:middle line:84% So we have our input and output net charge. 00:20:13.840 --> 00:20:17.170 align:middle line:84% If I wanted to talk about the average current going 00:20:17.170 --> 00:20:21.790 align:middle line:84% to the input or the output averaged over a cycle, really, 00:20:21.790 --> 00:20:24.670 align:middle line:84% it's the charge divided by the period, 00:20:24.670 --> 00:20:28.080 align:middle line:84% or equivalently the charge times the switching frequency. 00:20:28.080 --> 00:20:31.750 align:middle line:84% So the local average or the average 00:20:31.750 --> 00:20:35.170 align:middle line:84% in periodic steady state, I could infer from this 00:20:35.170 --> 00:20:46.510 align:middle line:84% is that i in is equal to c times the switching frequency-- 00:20:46.510 --> 00:20:48.160 align:middle line:90% that's 1 over the period-- 00:20:48.160 --> 00:20:52.420 align:middle line:90% times v in minus 2 v out. 00:20:52.420 --> 00:20:55.420 align:middle line:90% 00:20:55.420 --> 00:20:57.560 align:middle line:84% And I should put my minus sign here. 00:20:57.560 --> 00:21:01.930 align:middle line:84% And that's this is the current going into the input. 00:21:01.930 --> 00:21:10.150 align:middle line:84% And likewise, i out is equal to 2 c f switch times v in minus 2 00:21:10.150 --> 00:21:12.760 align:middle line:90% v out. 00:21:12.760 --> 00:21:17.620 align:middle line:84% So if you look at this, the magnitude of i 00:21:17.620 --> 00:21:23.270 align:middle line:84% out is equal to 2 times the magnitude of i in. 00:21:23.270 --> 00:21:25.930 align:middle line:90% 00:21:25.930 --> 00:21:27.050 align:middle line:90% Why? 00:21:27.050 --> 00:21:29.380 align:middle line:84% Because what happens is, essentially-- 00:21:29.380 --> 00:21:32.300 align:middle line:84% and what's the deal with the minus sign? 00:21:32.300 --> 00:21:33.970 align:middle line:84% The minus sign is because I chose 00:21:33.970 --> 00:21:35.870 align:middle line:90% to define i in going this way. 00:21:35.870 --> 00:21:38.500 align:middle line:84% Had I defined it going this way, I'd 00:21:38.500 --> 00:21:41.290 align:middle line:84% have i out is equal to twice i in. 00:21:41.290 --> 00:21:43.340 align:middle line:84% But let's just worry about the magnitudes here. 00:21:43.340 --> 00:21:44.930 align:middle line:90% So what's going on? 00:21:44.930 --> 00:21:47.320 align:middle line:84% In the first part of the cycle, I 00:21:47.320 --> 00:21:50.230 align:middle line:84% dump a certain amount of charge from the input to the output 00:21:50.230 --> 00:21:51.380 align:middle line:90% through the capacitor. 00:21:51.380 --> 00:21:53.400 align:middle line:90% I charge the capacitor up. 00:21:53.400 --> 00:21:55.320 align:middle line:90% So that's some amount of charge. 00:21:55.320 --> 00:21:58.410 align:middle line:84% In the second part of the cycle, this capacitor 00:21:58.410 --> 00:22:01.710 align:middle line:84% then dumps that same amount of charge into the output again. 00:22:01.710 --> 00:22:03.640 align:middle line:84% So the output gets twice the amount of charge 00:22:03.640 --> 00:22:05.320 align:middle line:90% as the input over the cycle. 00:22:05.320 --> 00:22:08.360 align:middle line:84% And then I go back to the next cycle and I repeat. 00:22:08.360 --> 00:22:12.740 align:middle line:84% So whatever the current coming in from-- 00:22:12.740 --> 00:22:14.840 align:middle line:84% coming into the converter from the input 00:22:14.840 --> 00:22:16.850 align:middle line:84% is exactly half the current going 00:22:16.850 --> 00:22:21.680 align:middle line:84% to the output by periodic steady state and charge balance 00:22:21.680 --> 00:22:23.620 align:middle line:90% on the capacitor. 00:22:23.620 --> 00:22:25.755 align:middle line:90% Any questions about that? 00:22:25.755 --> 00:22:28.500 align:middle line:90% 00:22:28.500 --> 00:22:32.130 align:middle line:84% I should say that this is the defining feature of a switch 00:22:32.130 --> 00:22:34.030 align:middle line:90% capacitor converter. 00:22:34.030 --> 00:22:39.130 align:middle line:84% You will always have some rational relationship-- 00:22:39.130 --> 00:22:41.760 align:middle line:84% "rational" meaning an actual fraction-- 00:22:41.760 --> 00:22:44.610 align:middle line:84% relating the current from the input to the current 00:22:44.610 --> 00:22:45.220 align:middle line:90% on the output. 00:22:45.220 --> 00:22:45.720 align:middle line:90% Why? 00:22:45.720 --> 00:22:48.065 align:middle line:84% Because this is a very simple converter. 00:22:48.065 --> 00:22:50.190 align:middle line:84% We've got one capacitor that we're flipping around, 00:22:50.190 --> 00:22:53.250 align:middle line:84% but generally, you're going to be taking energy, storing charge 00:22:53.250 --> 00:22:56.230 align:middle line:84% from the input, doing something, and throwing it to the output. 00:22:56.230 --> 00:23:01.880 align:middle line:84% And those are always going to be related in some rational way. 00:23:01.880 --> 00:23:06.650 align:middle line:84% So that's what the core thing that a switch capacitor 00:23:06.650 --> 00:23:08.420 align:middle line:84% converter do-- is by charge balance 00:23:08.420 --> 00:23:11.720 align:middle line:84% is going to give you some concurrent conversion 00:23:11.720 --> 00:23:13.610 align:middle line:84% ratio between the input and the output 00:23:13.610 --> 00:23:17.335 align:middle line:84% that's fixed by the topology and the switching sequence. 00:23:17.335 --> 00:23:26.790 align:middle line:90% 00:23:26.790 --> 00:23:29.700 align:middle line:90% What else can we say about this? 00:23:29.700 --> 00:23:35.290 align:middle line:84% Well, look at this relationship here. 00:23:35.290 --> 00:23:38.145 align:middle line:84% First of all, any questions about what got me to that? 00:23:38.145 --> 00:23:41.000 align:middle line:90% 00:23:41.000 --> 00:23:41.510 align:middle line:90% Yeah? 00:23:41.510 --> 00:23:43.853 align:middle line:84% AUDIENCE: Is this assuming a 50% duty cycle? 00:23:43.853 --> 00:23:45.270 align:middle line:84% PROFESSOR: That's a good question. 00:23:45.270 --> 00:23:50.210 align:middle line:84% So long as the intervals are such that I 00:23:50.210 --> 00:23:53.960 align:middle line:84% fully charge and fully discharge in each subinterval, 00:23:53.960 --> 00:23:56.270 align:middle line:84% in state 1 and state 2, the actual duty ratio 00:23:56.270 --> 00:23:59.300 align:middle line:84% doesn't matter in this mode of operation. 00:23:59.300 --> 00:24:01.850 align:middle line:84% So the only thing I've assumed is 00:24:01.850 --> 00:24:04.670 align:middle line:84% that I'm waiting long enough or in state 1 for the capacitor 00:24:04.670 --> 00:24:06.090 align:middle line:90% to get to its final voltage. 00:24:06.090 --> 00:24:08.330 align:middle line:84% And I'm waiting long enough in state 2 for the pastor 00:24:08.330 --> 00:24:09.597 align:middle line:90% to get to its final voltage. 00:24:09.597 --> 00:24:11.180 align:middle line:84% And as long as I've waited long enough 00:24:11.180 --> 00:24:14.000 align:middle line:84% in both states, what the actual fraction of bond times are 00:24:14.000 --> 00:24:16.250 align:middle line:90% doesn't matter. 00:24:16.250 --> 00:24:17.890 align:middle line:90% We'll come back to that shortly. 00:24:17.890 --> 00:24:18.570 align:middle line:90% Yeah? 00:24:18.570 --> 00:24:19.820 align:middle line:90% AUDIENCE: I've got a question. 00:24:19.820 --> 00:24:23.045 align:middle line:84% This mode is called the slow switching [INAUDIBLE], right? 00:24:23.045 --> 00:24:23.670 align:middle line:90% PROFESSOR: Yes. 00:24:23.670 --> 00:24:28.565 align:middle line:84% AUDIENCE: And is that why we didn't include the [INAUDIBLE], 00:24:28.565 --> 00:24:29.390 align:middle line:90% like effect-- 00:24:29.390 --> 00:24:35.090 align:middle line:84% or those switches there are represented as resistors, 00:24:35.090 --> 00:24:40.520 align:middle line:84% so like the charge doesn't [INAUDIBLE]? 00:24:40.520 --> 00:24:41.810 align:middle line:90% PROFESSOR: Well, no, it does. 00:24:41.810 --> 00:24:44.560 align:middle line:90% We've included the resistance. 00:24:44.560 --> 00:24:49.780 align:middle line:84% All I've said is the only thing you really 00:24:49.780 --> 00:24:54.340 align:middle line:84% need to know in this is where did the capacitor start 00:24:54.340 --> 00:24:56.720 align:middle line:84% in terms of its voltage and where did it end? 00:24:56.720 --> 00:25:00.190 align:middle line:84% And if you know that, then how much charge went into it. 00:25:00.190 --> 00:25:04.910 align:middle line:84% So we have actually included the effect of the resistances. 00:25:04.910 --> 00:25:06.600 align:middle line:90% It's those Rc charging things. 00:25:06.600 --> 00:25:08.750 align:middle line:84% If the resistances get small, I just 00:25:08.750 --> 00:25:11.960 align:middle line:90% make those Rc charging shorter. 00:25:11.960 --> 00:25:13.430 align:middle line:90% AUDIENCE: I see, thanks. 00:25:13.430 --> 00:25:16.970 align:middle line:84% But wouldn't on-state and off-state voltages 00:25:16.970 --> 00:25:21.020 align:middle line:84% change, like wouldn't there be potential differences 00:25:21.020 --> 00:25:22.010 align:middle line:90% across the resistors? 00:25:22.010 --> 00:25:27.320 align:middle line:84% PROFESSOR: Well, if I've assumed that the capacitor is fully 00:25:27.320 --> 00:25:31.430 align:middle line:84% charged, the voltage across this resistor went to 0 by the end. 00:25:31.430 --> 00:25:34.860 align:middle line:84% So the only assumption I've made is this capacitor charges. 00:25:34.860 --> 00:25:36.570 align:middle line:84% Once the capacitor current goes to 0, 00:25:36.570 --> 00:25:39.430 align:middle line:90% these voltage drops go to 0. 00:25:39.430 --> 00:25:41.190 align:middle line:84% We'll relax that assumption shortly. 00:25:41.190 --> 00:25:43.760 align:middle line:90% 00:25:43.760 --> 00:25:46.130 align:middle line:84% So let me start from this relationship, 00:25:46.130 --> 00:25:48.890 align:middle line:84% and let me see if I can give you what 00:25:48.890 --> 00:25:50.610 align:middle line:90% the voltage relationship is. 00:25:50.610 --> 00:25:54.260 align:middle line:84% I've told you here, this is the current relationship 00:25:54.260 --> 00:25:55.670 align:middle line:90% of the converter. 00:25:55.670 --> 00:25:59.900 align:middle line:84% That's the fundamental thing that this converter does. 00:25:59.900 --> 00:26:03.020 align:middle line:84% Well, how are the input and output voltage related? 00:26:03.020 --> 00:26:05.720 align:middle line:90% Well, that's by this guy here. 00:26:05.720 --> 00:26:08.220 align:middle line:90% And I can rearrange this. 00:26:08.220 --> 00:26:11.870 align:middle line:84% So all I could do is maybe solve for v out. 00:26:11.870 --> 00:26:14.300 align:middle line:84% And if I solve this equation for v out, 00:26:14.300 --> 00:26:23.510 align:middle line:84% what I'm going to get is v out is equal to 1/2 of v in minus 1 00:26:23.510 --> 00:26:30.265 align:middle line:90% over 4 f switch c times i out. 00:26:30.265 --> 00:26:32.810 align:middle line:90% 00:26:32.810 --> 00:26:35.965 align:middle line:84% This is an equivalent statement as this. 00:26:35.965 --> 00:26:40.442 align:middle line:90% 00:26:40.442 --> 00:26:45.600 align:middle line:84% So what does that mean as in a practical matter? 00:26:45.600 --> 00:26:50.280 align:middle line:84% Well, let me create for you an equivalent circuit which 00:26:50.280 --> 00:26:59.940 align:middle line:84% does this same thing, So I told you, this is my converter. 00:26:59.940 --> 00:27:01.950 align:middle line:84% If I wanted a periodic steady state 00:27:01.950 --> 00:27:05.210 align:middle line:84% model for what this thing does, I have some input voltage. 00:27:05.210 --> 00:27:10.470 align:middle line:90% 00:27:10.470 --> 00:27:15.510 align:middle line:84% And then I have some load current connected to it 00:27:15.510 --> 00:27:17.310 align:middle line:90% that I'm going to call i out. 00:27:17.310 --> 00:27:19.690 align:middle line:84% What is the relationship between what's in there? 00:27:19.690 --> 00:27:21.250 align:middle line:90% It's defined by this. 00:27:21.250 --> 00:27:23.820 align:middle line:84% Well, here's a circuit that gives you 00:27:23.820 --> 00:27:25.440 align:middle line:90% this same relationship. 00:27:25.440 --> 00:27:32.840 align:middle line:84% If I had an ideal 2-to-1 transformer, 00:27:32.840 --> 00:27:36.590 align:middle line:84% if this is v in, this voltage would be half v 00:27:36.590 --> 00:27:40.880 align:middle line:84% in because that's what the transformer does. 00:27:40.880 --> 00:27:45.110 align:middle line:84% And then I would have an equivalent resistance 00:27:45.110 --> 00:27:48.650 align:middle line:84% that would give me a voltage drop that was i out times 1 00:27:48.650 --> 00:27:50.040 align:middle line:90% over 4 f switch. 00:27:50.040 --> 00:27:55.520 align:middle line:84% So I'd have an equivalent resistance of 1 over 4 00:27:55.520 --> 00:27:59.070 align:middle line:90% f switch c. 00:27:59.070 --> 00:28:01.090 align:middle line:84% And I could put this whole thing in a box. 00:28:01.090 --> 00:28:05.110 align:middle line:90% 00:28:05.110 --> 00:28:10.060 align:middle line:84% And this is a DC equivalent model 00:28:10.060 --> 00:28:12.040 align:middle line:90% for how this thing behaves. 00:28:12.040 --> 00:28:15.045 align:middle line:90% In other words, this is v out. 00:28:15.045 --> 00:28:18.040 align:middle line:90% 00:28:18.040 --> 00:28:20.770 align:middle line:84% So this gives me the right relationships between v 00:28:20.770 --> 00:28:22.660 align:middle line:90% and v out. 00:28:22.660 --> 00:28:32.290 align:middle line:84% v out is half v in minus the voltage drop 00:28:32.290 --> 00:28:36.400 align:middle line:84% across this which is i out over 4 c f switch. 00:28:36.400 --> 00:28:40.360 align:middle line:84% Likewise, if I have a current coming i out this way, 00:28:40.360 --> 00:28:43.510 align:middle line:84% the current this way through the ideal transformer 00:28:43.510 --> 00:28:45.700 align:middle line:84% is going to be exactly half of that. 00:28:45.700 --> 00:28:50.510 align:middle line:84% And that means the current this way is minus 1/2 i out. 00:28:50.510 --> 00:28:53.980 align:middle line:84% So this model in yellow here precisely 00:28:53.980 --> 00:28:58.723 align:middle line:84% captures the average circuit behavior of this system. 00:28:58.723 --> 00:29:00.140 align:middle line:84% Does that make sense to everybody? 00:29:00.140 --> 00:29:02.710 align:middle line:90% 00:29:02.710 --> 00:29:05.740 align:middle line:90% Now this is this converter. 00:29:05.740 --> 00:29:08.860 align:middle line:84% Any other switch capacitor converter I want to model, 00:29:08.860 --> 00:29:15.970 align:middle line:84% you can model likewise as some ideal transformer relationship. 00:29:15.970 --> 00:29:18.920 align:middle line:84% This gives me my current conversion ratio. 00:29:18.920 --> 00:29:21.580 align:middle line:84% The input and the output current are 00:29:21.580 --> 00:29:26.650 align:middle line:84% related by the ideal transformer and then a voltage drop that's 00:29:26.650 --> 00:29:31.690 align:middle line:84% related by some equivalent resistance that's 00:29:31.690 --> 00:29:34.420 align:middle line:84% related to the energy transfer capacitors and the switching 00:29:34.420 --> 00:29:36.010 align:middle line:90% frequency. 00:29:36.010 --> 00:29:38.680 align:middle line:84% So the details will vary, but this model really 00:29:38.680 --> 00:29:41.380 align:middle line:90% captures what's going on. 00:29:41.380 --> 00:29:45.220 align:middle line:84% Now if I said, well, what's a what's an-- 00:29:45.220 --> 00:29:47.440 align:middle line:84% if I wanted to just look back from the output 00:29:47.440 --> 00:29:49.810 align:middle line:84% and get Thevenin equivalent looking backwards, 00:29:49.810 --> 00:29:51.730 align:middle line:90% all I would see is-- 00:29:51.730 --> 00:29:54.220 align:middle line:84% another way to think about this is one half v 00:29:54.220 --> 00:29:57.670 align:middle line:90% in as a Thevenin voltage. 00:29:57.670 --> 00:30:04.330 align:middle line:84% And a Thevenin resistance would be Req is equal to 1 over 4 00:30:04.330 --> 00:30:07.420 align:middle line:90% f switch c. 00:30:07.420 --> 00:30:10.360 align:middle line:84% This is a Thevenin equivalent model 00:30:10.360 --> 00:30:13.300 align:middle line:84% looking back into the switch capacitor converter 00:30:13.300 --> 00:30:15.710 align:middle line:90% from at least a DC. 00:30:15.710 --> 00:30:17.630 align:middle line:90% This is legitimate. 00:30:17.630 --> 00:30:21.510 align:middle line:84% Does that make sense to everybody? 00:30:21.510 --> 00:30:27.570 align:middle line:84% Now we could say, what's the efficiency of the converter? 00:30:27.570 --> 00:30:40.050 align:middle line:84% Well, the efficiency is equal to v out i out divided 00:30:40.050 --> 00:30:44.890 align:middle line:90% by v in or minus v in i in. 00:30:44.890 --> 00:30:55.140 align:middle line:84% And since i out is twice minus i in, 00:30:55.140 --> 00:31:03.195 align:middle line:84% this would be equal to 2 times v out over v in. 00:31:03.195 --> 00:31:06.920 align:middle line:90% 00:31:06.920 --> 00:31:13.360 align:middle line:84% And we have an expression for v out right here. 00:31:13.360 --> 00:31:20.110 align:middle line:84% I could write this as also equal to v out over 1/2 v in. 00:31:20.110 --> 00:31:24.280 align:middle line:84% So to the extent that v out is smaller than half v in, 00:31:24.280 --> 00:31:26.450 align:middle line:90% the efficiency is less than 1. 00:31:26.450 --> 00:31:29.770 align:middle line:84% Well, we can see that the output is smaller 00:31:29.770 --> 00:31:33.960 align:middle line:84% than half v in by whatever drop is across this resistor. 00:31:33.960 --> 00:31:38.770 align:middle line:84% So this model is actually useful for calculating-- 00:31:38.770 --> 00:31:41.670 align:middle line:84% this model is actually useful for calculating efficiency 00:31:41.670 --> 00:31:42.660 align:middle line:90% as well. 00:31:42.660 --> 00:31:44.560 align:middle line:90% And I could rewrite that. 00:31:44.560 --> 00:31:47.295 align:middle line:84% If I plug that in, what I would get is-- 00:31:47.295 --> 00:31:50.280 align:middle line:90% 00:31:50.280 --> 00:31:56.070 align:middle line:84% I could rewrite this as the efficiency simply is equal to 1 00:31:56.070 --> 00:32:03.906 align:middle line:84% minus i out times Req over 1/2 v in. 00:32:03.906 --> 00:32:06.620 align:middle line:90% 00:32:06.620 --> 00:32:11.300 align:middle line:84% This is just illustrating if my load current goes to 0, 00:32:11.300 --> 00:32:15.480 align:middle line:90% the efficiency then goes to 1. 00:32:15.480 --> 00:32:19.860 align:middle line:84% If my load current gets really big, the output droops down. 00:32:19.860 --> 00:32:23.670 align:middle line:84% As my output gets really big, I get a bigger and bigger drop 00:32:23.670 --> 00:32:26.850 align:middle line:84% across this equivalent resistor, and my efficiency 00:32:26.850 --> 00:32:29.170 align:middle line:90% starts to decline. 00:32:29.170 --> 00:32:30.700 align:middle line:90% Does that make sense, everybody? 00:32:30.700 --> 00:32:33.640 align:middle line:84% Now, when I'm saying this, what losses 00:32:33.640 --> 00:32:35.930 align:middle line:84% am I counting when I'm calculating this efficiency? 00:32:35.930 --> 00:32:39.460 align:middle line:84% The losses I'm counting are essentially 00:32:39.460 --> 00:32:43.570 align:middle line:84% the resistor losses, the losses in the switch resistances 00:32:43.570 --> 00:32:46.510 align:middle line:84% and in the capacitor, like any parasitics in the capacitor. 00:32:46.510 --> 00:32:53.300 align:middle line:84% It's what we would call capacitor charging loss. 00:32:53.300 --> 00:32:57.290 align:middle line:84% So the only loss I'm not counting-- 00:32:57.290 --> 00:32:59.930 align:middle line:84% if these switch have gate drives and the gate drive-- 00:32:59.930 --> 00:33:02.060 align:middle line:84% gate capacitance [INAUDIBLE] charge and discharge 00:33:02.060 --> 00:33:04.760 align:middle line:84% or other losses like that are internal to the switches, 00:33:04.760 --> 00:33:09.050 align:middle line:84% but the loss associated with the switches delivering current 00:33:09.050 --> 00:33:11.907 align:middle line:84% through to charge the capacitor and discharge the capacitor. 00:33:11.907 --> 00:33:14.240 align:middle line:84% Now it doesn't matter-- you notice the switch resistance 00:33:14.240 --> 00:33:15.407 align:middle line:90% isn't even in here anywhere. 00:33:15.407 --> 00:33:18.770 align:middle line:84% It doesn't really matter what the switch resistance is. 00:33:18.770 --> 00:33:22.010 align:middle line:84% The only constraint I have is that I 00:33:22.010 --> 00:33:25.700 align:middle line:84% have to finish charging and discharging. 00:33:25.700 --> 00:33:28.100 align:middle line:90% And that's just because of-- 00:33:28.100 --> 00:33:30.950 align:middle line:84% you can do this by basically charging methods 00:33:30.950 --> 00:33:32.700 align:middle line:90% to find out the efficiency. 00:33:32.700 --> 00:33:36.485 align:middle line:90% 00:33:36.485 --> 00:33:37.860 align:middle line:84% AUDIENCE: Could you say it again, 00:33:37.860 --> 00:33:39.750 align:middle line:84% where the power is being dissipated? 00:33:39.750 --> 00:33:44.130 align:middle line:84% PROFESSOR: The power is being dissipated in-- 00:33:44.130 --> 00:33:48.030 align:middle line:90% if the only elements-- 00:33:48.030 --> 00:33:49.650 align:middle line:84% I mean, the power is being dissipated 00:33:49.650 --> 00:33:55.030 align:middle line:84% in any parasitic resistance in the charge and discharge path. 00:33:55.030 --> 00:33:59.590 align:middle line:84% So if I turn the switch on, it has some voltage drop across it, 00:33:59.590 --> 00:34:02.260 align:middle line:84% or if the capacitor has some parasitic resistance, 00:34:02.260 --> 00:34:07.498 align:middle line:90% it loses some energy in that. 00:34:07.498 --> 00:34:09.040 align:middle line:84% You say, well, what happens if I make 00:34:09.040 --> 00:34:10.940 align:middle line:90% my switch resistance go to 0? 00:34:10.940 --> 00:34:14.139 align:middle line:84% Well, all that happens is that the peak charging current 00:34:14.139 --> 00:34:16.429 align:middle line:90% gets higher. 00:34:16.429 --> 00:34:19.460 align:middle line:90% And it goes for a shorter time. 00:34:19.460 --> 00:34:21.826 align:middle line:84% And the total loss is the same thing. 00:34:21.826 --> 00:34:23.159 align:middle line:90% So mathematically, it works out. 00:34:23.159 --> 00:34:25.260 align:middle line:84% The actual value of the resistance doesn't matter. 00:34:25.260 --> 00:34:27.052 align:middle line:84% It doesn't even matter if the resistance is 00:34:27.052 --> 00:34:30.780 align:middle line:84% linear or nonlinear, but you get the same net loss. 00:34:30.780 --> 00:34:33.440 align:middle line:84% So it's basically the loss that I 00:34:33.440 --> 00:34:36.883 align:middle line:84% incur in putting the charge on the capacitor 00:34:36.883 --> 00:34:39.050 align:middle line:84% and then taking the charge back off to the capacitor 00:34:39.050 --> 00:34:42.730 align:middle line:84% to the output-- that's the loss that's included. 00:34:42.730 --> 00:34:43.420 align:middle line:90% Yeah? 00:34:43.420 --> 00:34:45.820 align:middle line:84% AUDIENCE: So if you use a smaller capacitor, which 00:34:45.820 --> 00:34:47.560 align:middle line:84% takes less time to charge your charge, 00:34:47.560 --> 00:34:50.290 align:middle line:90% can you see smaller losses? 00:34:50.290 --> 00:34:53.980 align:middle line:84% PROFESSOR: Ah, so if I wanted to reduce my losses, 00:34:53.980 --> 00:34:57.450 align:middle line:84% let's go back and look at my efficiency characteristic. 00:34:57.450 --> 00:35:00.740 align:middle line:84% If I want smaller losses, I should make Req small. 00:35:00.740 --> 00:35:05.140 align:middle line:84% To make R equivalent small, I should make either c 00:35:05.140 --> 00:35:08.670 align:middle line:90% big or switching frequency big. 00:35:08.670 --> 00:35:10.080 align:middle line:90% And the notion is-- 00:35:10.080 --> 00:35:13.150 align:middle line:84% and we'll come back to this and we'll look at this next class-- 00:35:13.150 --> 00:35:15.580 align:middle line:84% it comes down to the amount I'm charging and discharging 00:35:15.580 --> 00:35:16.080 align:middle line:90% the parser. 00:35:16.080 --> 00:35:19.380 align:middle line:84% When I charge the capacitor over a small, tiny delta voltage, 00:35:19.380 --> 00:35:21.580 align:middle line:84% I don't lose much energy in doing it. 00:35:21.580 --> 00:35:23.940 align:middle line:84% And so if I want lower loss, it's 00:35:23.940 --> 00:35:25.720 align:middle line:84% a very great insight on your part. 00:35:25.720 --> 00:35:27.387 align:middle line:84% But if I want lower loss, I want to make 00:35:27.387 --> 00:35:29.570 align:middle line:84% the capacitor bigger, not smaller 00:35:29.570 --> 00:35:31.170 align:middle line:90% for a given load current. 00:35:31.170 --> 00:35:33.800 align:middle line:90% 00:35:33.800 --> 00:35:39.650 align:middle line:84% So this model-- in fact, if I wanted, 00:35:39.650 --> 00:35:41.390 align:middle line:84% if I put a resistive load on here, 00:35:41.390 --> 00:35:43.610 align:middle line:84% the efficiency is exactly just the efficiency 00:35:43.610 --> 00:35:45.320 align:middle line:90% of a voltage divider. 00:35:45.320 --> 00:35:49.530 align:middle line:90% So this is a very good model. 00:35:49.530 --> 00:35:53.120 align:middle line:84% And the only thing that would vary if I model any other switch 00:35:53.120 --> 00:35:57.320 align:middle line:84% capacitor converter would be this transformer ratio, 00:35:57.320 --> 00:36:00.320 align:middle line:84% which relates to that perfect current conversion ratio 00:36:00.320 --> 00:36:03.680 align:middle line:84% we calculated, and what the exact value of this output 00:36:03.680 --> 00:36:07.550 align:middle line:84% resistance would look like, which is, again dictated 00:36:07.550 --> 00:36:10.220 align:middle line:90% by the losses. 00:36:10.220 --> 00:36:11.190 align:middle line:90% Questions? 00:36:11.190 --> 00:36:14.850 align:middle line:90% 00:36:14.850 --> 00:36:24.400 align:middle line:84% So let's think about what other case I might consider. 00:36:24.400 --> 00:36:26.730 align:middle line:84% We said, OK, suppose I want to-- and by the way, 00:36:26.730 --> 00:36:28.480 align:middle line:90% why do we like these converters? 00:36:28.480 --> 00:36:30.060 align:middle line:84% Because they can be hyperefficient. 00:36:30.060 --> 00:36:35.050 align:middle line:84% If I go buy a really big capacitor here 00:36:35.050 --> 00:36:38.500 align:middle line:84% or I switch really fast, this equivalent resistance 00:36:38.500 --> 00:36:39.940 align:middle line:90% can be very small. 00:36:39.940 --> 00:36:44.480 align:middle line:84% And I can get an almost perfect 2-to-1 voltage conversion. 00:36:44.480 --> 00:36:50.750 align:middle line:84% And, in fact, people would call this thing a 2-to-1 step-down 00:36:50.750 --> 00:36:52.380 align:middle line:90% switch capacitor converter. 00:36:52.380 --> 00:36:52.880 align:middle line:90% Why? 00:36:52.880 --> 00:36:55.670 align:middle line:84% Because they're thinking of the voltage. 00:36:55.670 --> 00:36:58.670 align:middle line:84% Ideally speaking, if I make this resistance really small, 00:36:58.670 --> 00:37:03.050 align:middle line:84% I'm really just doing like an ideal transformer 2-to-1. 00:37:03.050 --> 00:37:05.730 align:middle line:84% And so people would call that a 2-to-1. 00:37:05.730 --> 00:37:09.110 align:middle line:84% On the other hand, it's only approximately 2-to-1 00:37:09.110 --> 00:37:10.350 align:middle line:90% because this is not 0. 00:37:10.350 --> 00:37:12.840 align:middle line:84% This is some finite value of resistance. 00:37:12.840 --> 00:37:17.570 align:middle line:84% What it is, is a 1-to-2 current converter-- 00:37:17.570 --> 00:37:19.080 align:middle line:90% switch capacitor or converter. 00:37:19.080 --> 00:37:22.580 align:middle line:84% And that relationship is precise. 00:37:22.580 --> 00:37:25.440 align:middle line:90% So what should people call this? 00:37:25.440 --> 00:37:27.620 align:middle line:84% They should call this a 1-to-2 current conversion-- 00:37:27.620 --> 00:37:29.250 align:middle line:90% switch capacitor converter. 00:37:29.250 --> 00:37:30.630 align:middle line:84% But that's not what they call it. 00:37:30.630 --> 00:37:33.005 align:middle line:84% They call it a 2-to-1 voltage converter because everybody 00:37:33.005 --> 00:37:34.280 align:middle line:90% likes to think about voltages. 00:37:34.280 --> 00:37:36.440 align:middle line:84% So it's just you're stuck with the-- you're stuck 00:37:36.440 --> 00:37:41.240 align:middle line:84% with what people call things, but maybe it's not fair. 00:37:41.240 --> 00:37:51.480 align:middle line:84% So what do I get if I wanted to go up in performance? 00:37:51.480 --> 00:37:53.450 align:middle line:90% Suppose I want-- 00:37:53.450 --> 00:37:56.270 align:middle line:84% I should say, when would I want to use a switch capacitor 00:37:56.270 --> 00:37:56.863 align:middle line:90% converter? 00:37:56.863 --> 00:37:58.280 align:middle line:84% I'd want to use a switch capacitor 00:37:58.280 --> 00:38:04.730 align:middle line:84% converter-- for example, I have 5 volts and I need 2.5 volts. 00:38:04.730 --> 00:38:07.880 align:middle line:90% I want exactly half the voltage. 00:38:07.880 --> 00:38:10.405 align:middle line:84% Then, to the extent that I can make 00:38:10.405 --> 00:38:11.780 align:middle line:84% this equivalent resistance small, 00:38:11.780 --> 00:38:13.940 align:middle line:90% this is a great converter. 00:38:13.940 --> 00:38:15.620 align:middle line:84% On the other hand, I wouldn't want 00:38:15.620 --> 00:38:18.920 align:middle line:84% to use this converter when my input voltage was 5 volts 00:38:18.920 --> 00:38:21.500 align:middle line:84% and my output voltage was 2 volts, 00:38:21.500 --> 00:38:26.690 align:middle line:84% because then my efficiency would be 2 over 2.5, 00:38:26.690 --> 00:38:28.100 align:middle line:90% which isn't that high. 00:38:28.100 --> 00:38:31.970 align:middle line:84% So switch capacitors or converters 00:38:31.970 --> 00:38:34.730 align:middle line:84% are very efficient when your voltage conversion 00:38:34.730 --> 00:38:36.710 align:middle line:84% ratio is very close to the inverse 00:38:36.710 --> 00:38:39.590 align:middle line:84% of your intrinsic current conversion ratio. 00:38:39.590 --> 00:38:42.990 align:middle line:84% And then their efficiency droops down outside of that range. 00:38:42.990 --> 00:38:46.550 align:middle line:84% Sometimes, actually, people use this and vary this equivalent 00:38:46.550 --> 00:38:48.440 align:middle line:84% resistor to give yourself a linear regulator 00:38:48.440 --> 00:38:49.500 align:middle line:90% kind of action too. 00:38:49.500 --> 00:38:52.160 align:middle line:84% So instead of linear regulating down from v in, 00:38:52.160 --> 00:38:54.320 align:middle line:84% you linear regulate down from half v in, 00:38:54.320 --> 00:38:55.920 align:middle line:84% so you get an advantage that way. 00:38:55.920 --> 00:38:58.513 align:middle line:84% But if you want to talk about pure switch mode operation, 00:38:58.513 --> 00:39:00.430 align:middle line:84% you're usually trying to make this very small. 00:39:00.430 --> 00:39:03.020 align:middle line:90% 00:39:03.020 --> 00:39:04.520 align:middle line:90% How do I make that small? 00:39:04.520 --> 00:39:09.000 align:middle line:84% I either get big capacitors or I switch fast. 00:39:09.000 --> 00:39:12.750 align:middle line:84% Now there's an exception to what I said 00:39:12.750 --> 00:39:15.070 align:middle line:90% or a limit to what I said. 00:39:15.070 --> 00:39:22.110 align:middle line:84% This operation is all in what I've been calling 00:39:22.110 --> 00:39:24.240 align:middle line:90% the slow switching limit. 00:39:24.240 --> 00:39:28.740 align:middle line:84% This limit right here, where I'm fully 00:39:28.740 --> 00:39:33.587 align:middle line:84% charging and fully discharging, suppose 00:39:33.587 --> 00:39:34.920 align:middle line:90% I want to get higher efficiency. 00:39:34.920 --> 00:39:38.580 align:middle line:84% And I'm forgetting about gate losses and capacitor discharge 00:39:38.580 --> 00:39:40.390 align:middle line:84% losses and stuff inside the switches. 00:39:40.390 --> 00:39:42.880 align:middle line:84% I'm just talking about the charge transfer losses. 00:39:42.880 --> 00:39:45.520 align:middle line:84% I can switch faster and faster and faster. 00:39:45.520 --> 00:39:48.390 align:middle line:84% That output resistance keeps drooping, keeps getting smaller, 00:39:48.390 --> 00:39:49.710 align:middle line:90% and that's better. 00:39:49.710 --> 00:39:51.990 align:middle line:84% But eventually, I get to the point 00:39:51.990 --> 00:39:54.600 align:middle line:84% where if I increase my switching frequency-- 00:39:54.600 --> 00:39:58.080 align:middle line:84% suppose I just keep each time period half, 00:39:58.080 --> 00:39:59.670 align:middle line:84% that this time period is going to get 00:39:59.670 --> 00:40:04.200 align:middle line:84% so short that my capacitor doesn't fully charge up. 00:40:04.200 --> 00:40:06.250 align:middle line:84% And he doesn't fully charge down. 00:40:06.250 --> 00:40:10.020 align:middle line:84% If I keep pushing my switching frequency up enough, 00:40:10.020 --> 00:40:12.090 align:middle line:84% I'm going to violate the assumption under which I 00:40:12.090 --> 00:40:13.306 align:middle line:90% did this analysis. 00:40:13.306 --> 00:40:16.750 align:middle line:90% 00:40:16.750 --> 00:40:20.590 align:middle line:84% The extreme limit of that is the capacitor 00:40:20.590 --> 00:40:24.160 align:middle line:84% sitting close to some voltage, and he only 00:40:24.160 --> 00:40:26.640 align:middle line:90% charges up and down a little. 00:40:26.640 --> 00:40:31.830 align:middle line:84% So, in other words, suppose I made my time scale really short, 00:40:31.830 --> 00:40:33.450 align:middle line:90% and I will have-- 00:40:33.450 --> 00:40:36.300 align:middle line:84% here's state 1 and here's state 2. 00:40:36.300 --> 00:40:42.260 align:middle line:84% And, in state 1, he just does this. 00:40:42.260 --> 00:40:49.980 align:middle line:84% He charges a tiny bit, which is part of a much bigger charge. 00:40:49.980 --> 00:40:55.460 align:middle line:84% And then to state 2, he discharges just a tiny bit, 00:40:55.460 --> 00:40:59.480 align:middle line:84% which is part of a much longer time charge, 00:40:59.480 --> 00:41:02.620 align:middle line:84% So I can almost think in the fast-switching limit-- 00:41:02.620 --> 00:41:09.230 align:middle line:90% 00:41:09.230 --> 00:41:13.880 align:middle line:90% vc is almost constant. 00:41:13.880 --> 00:41:17.070 align:middle line:84% I don't have enough time to charge up or down substantially. 00:41:17.070 --> 00:41:21.140 align:middle line:84% The delta voltage I get is nowhere near the full swing. 00:41:21.140 --> 00:41:24.530 align:middle line:84% And I can just start to think about the capacitor 00:41:24.530 --> 00:41:27.640 align:middle line:90% as being a constant voltage. 00:41:27.640 --> 00:41:29.525 align:middle line:84% But it's a special constant voltage because, 00:41:29.525 --> 00:41:31.900 align:middle line:84% nonetheless, if I'm going to be in periodic steady state, 00:41:31.900 --> 00:41:35.500 align:middle line:84% however much he charges in the first state must balance 00:41:35.500 --> 00:41:38.120 align:middle line:84% the amount of discharges in the second state 00:41:38.120 --> 00:41:43.420 align:middle line:84% that I haven't gotten around that kind of rule. 00:41:43.420 --> 00:41:47.530 align:middle line:84% But nonetheless, we can think about this fast switching limit 00:41:47.530 --> 00:41:50.270 align:middle line:84% as the capacitor voltage almost becoming constant. 00:41:50.270 --> 00:41:54.550 align:middle line:84% So let's think about what would a converter do in the fast 00:41:54.550 --> 00:42:02.870 align:middle line:84% switching limit in the FSL in state-- 00:42:02.870 --> 00:42:04.720 align:middle line:90% so let me just think about-- 00:42:04.720 --> 00:42:09.400 align:middle line:84% I'm going to now mentally replace this capacitor 00:42:09.400 --> 00:42:14.110 align:middle line:90% with just a fixed voltage, vc. 00:42:14.110 --> 00:42:16.690 align:middle line:84% And in this other state, he's also 00:42:16.690 --> 00:42:19.420 align:middle line:90% going to be a fixed voltage vc. 00:42:19.420 --> 00:42:21.820 align:middle line:84% And the only thing I need is the net charge 00:42:21.820 --> 00:42:24.130 align:middle line:84% that goes into vc over a cycle to be 0. 00:42:24.130 --> 00:42:29.395 align:middle line:84% So how much charge do I transfer in state 1? 00:42:29.395 --> 00:42:34.220 align:middle line:90% 00:42:34.220 --> 00:42:39.325 align:middle line:84% And I'm going to do FSL with 50% duty ratio. 00:42:39.325 --> 00:42:44.480 align:middle line:90% 00:42:44.480 --> 00:42:46.760 align:middle line:84% In other words, I'm going to assume that in state 1, 00:42:46.760 --> 00:42:48.290 align:middle line:90% I spend half a period. 00:42:48.290 --> 00:42:52.430 align:middle line:84% In state 2, I'm going to spend half a period because 00:42:52.430 --> 00:42:55.970 align:middle line:84% in the FSL, the fast switching limit, how much time I 00:42:55.970 --> 00:42:58.385 align:middle line:84% spend in the two adjacent states matters. 00:42:58.385 --> 00:43:00.260 align:middle line:84% But let's just assume I'm going to spend half 00:43:00.260 --> 00:43:02.570 align:middle line:84% in each state for purposes of this analysis. 00:43:02.570 --> 00:43:08.120 align:middle line:84% So in state 1, what do I get for delta qc 1? 00:43:08.120 --> 00:43:14.150 align:middle line:84% Well, delta qc 1 is going to be what? 00:43:14.150 --> 00:43:17.720 align:middle line:84% I'm going to say, all right, if he's a constant voltage, 00:43:17.720 --> 00:43:20.390 align:middle line:84% I'm going to get a current that's 00:43:20.390 --> 00:43:26.480 align:middle line:84% going to be v in minus vc minus v out divided by 2 R switch. 00:43:26.480 --> 00:43:28.700 align:middle line:90% That's the current in state 1. 00:43:28.700 --> 00:43:37.400 align:middle line:84% So that's going to be v in minus vc minus v out divided 00:43:37.400 --> 00:43:39.920 align:middle line:90% by 2 R switch. 00:43:39.920 --> 00:43:42.370 align:middle line:84% And that's going to happen for how long? 00:43:42.370 --> 00:43:45.060 align:middle line:84% That's going to happen for one half t. 00:43:45.060 --> 00:43:50.700 align:middle line:84% Or I could write that as 1 over 2 f switch, 00:43:50.700 --> 00:43:52.760 align:middle line:90% This is times half a period. 00:43:52.760 --> 00:43:55.560 align:middle line:90% 00:43:55.560 --> 00:44:00.310 align:middle line:90% What is delta q in 1 look like? 00:44:00.310 --> 00:44:05.100 align:middle line:84% That's just going to be minus delta qc 1. 00:44:05.100 --> 00:44:08.980 align:middle line:84% And what's delta q in 2 look like? 00:44:08.980 --> 00:44:14.880 align:middle line:84% That's just going to be equal to delta qc 1. 00:44:14.880 --> 00:44:16.590 align:middle line:84% In other words, all I'm saying is 00:44:16.590 --> 00:44:19.473 align:middle line:84% that here, the input got the negative 00:44:19.473 --> 00:44:21.390 align:middle line:84% of the charge of the capacitor, and the output 00:44:21.390 --> 00:44:25.530 align:middle line:84% got the charge that went through the capacitor. 00:44:25.530 --> 00:44:26.770 align:middle line:90% Makes sense to everybody? 00:44:26.770 --> 00:44:30.050 align:middle line:90% 00:44:30.050 --> 00:44:45.560 align:middle line:84% If I do this for state 2, what I'm going to get is delta qc 2 00:44:45.560 --> 00:44:47.330 align:middle line:90% is simply going to be what? 00:44:47.330 --> 00:44:55.020 align:middle line:84% It's going to be v out minus vc over 2 R switch. 00:44:55.020 --> 00:45:01.880 align:middle line:84% Or it's going to be v out minus vc over 2 R switch 00:45:01.880 --> 00:45:13.100 align:middle line:84% is going to be minus vc minus v out over 2 R switch times 00:45:13.100 --> 00:45:16.450 align:middle line:90% 1 over 2 f switch. 00:45:16.450 --> 00:45:21.860 align:middle line:90% Delta q in 2 is going to be 0. 00:45:21.860 --> 00:45:27.830 align:middle line:84% And delta q out 2 is going to be equal to the negative of this, 00:45:27.830 --> 00:45:32.970 align:middle line:84% which is going to be minus delta qc 1. 00:45:32.970 --> 00:45:36.750 align:middle line:90% Does that make sense, everybody? 00:45:36.750 --> 00:45:40.090 align:middle line:90% AUDIENCE: [INAUDIBLE] 00:45:40.090 --> 00:45:40.945 align:middle line:90% 00:45:40.945 --> 00:45:41.570 align:middle line:90% PROFESSOR: Yes. 00:45:41.570 --> 00:45:48.937 align:middle line:90% 00:45:48.937 --> 00:45:50.270 align:middle line:90% That's what happens when I rush. 00:45:50.270 --> 00:45:50.840 align:middle line:90% Thank you. 00:45:50.840 --> 00:45:53.910 align:middle line:90% 00:45:53.910 --> 00:45:56.710 align:middle line:84% What constraint do I get off of this? 00:45:56.710 --> 00:46:02.370 align:middle line:84% Well, what I need is delta qc of 1 plus delta qc of 2 00:46:02.370 --> 00:46:05.130 align:middle line:90% have to add up to 0. 00:46:05.130 --> 00:46:09.450 align:middle line:84% I mean, that's a constraint for periodic steady state. 00:46:09.450 --> 00:46:20.700 align:middle line:84% So what I get is for PSS, what I get is delta qc of 1 00:46:20.700 --> 00:46:27.420 align:middle line:84% plus delta qc 2 is equal to 0, which gives me-- 00:46:27.420 --> 00:46:30.510 align:middle line:84% I can ignore the 1 over 4 f switch R switch. 00:46:30.510 --> 00:46:32.670 align:middle line:84% That gives me v in minus vc minus v 00:46:32.670 --> 00:46:52.260 align:middle line:84% out plus v out minus vc plus v out minus vc is equal to 0. 00:46:52.260 --> 00:46:58.910 align:middle line:84% And what this gives me is that vc is going to be half v in. 00:46:58.910 --> 00:47:03.360 align:middle line:90% 00:47:03.360 --> 00:47:05.340 align:middle line:84% So in periodic steady state, I'm going 00:47:05.340 --> 00:47:07.050 align:middle line:84% to be charging discharging the capacitor, 00:47:07.050 --> 00:47:11.030 align:middle line:84% but he's going to sit at an average value of half v in. 00:47:11.030 --> 00:47:16.382 align:middle line:84% I can then go and plug this value back in-- 00:47:16.382 --> 00:47:18.090 align:middle line:84% and I'm kind of running out of time here. 00:47:18.090 --> 00:47:23.040 align:middle line:84% I can go plug this back in and find q out 1 and q in 1. 00:47:23.040 --> 00:47:27.530 align:middle line:84% I can do the same game I do over here. 00:47:27.530 --> 00:47:34.640 align:middle line:84% And if you do that calculation, it's pretty easy. 00:47:34.640 --> 00:47:37.730 align:middle line:84% I can calculate i out as being the sum of q 1 00:47:37.730 --> 00:47:39.000 align:middle line:90% and q in and q out. 00:47:39.000 --> 00:47:50.890 align:middle line:84% And what I get is v out is equal to 1/2 v in minus 2 R switch i 00:47:50.890 --> 00:47:51.390 align:middle line:90% out. 00:47:51.390 --> 00:47:54.080 align:middle line:90% 00:47:54.080 --> 00:48:01.100 align:middle line:84% So it's of the exact same format that I had up here. 00:48:01.100 --> 00:48:05.800 align:middle line:90% So here, I get this in the SSL. 00:48:05.800 --> 00:48:08.480 align:middle line:90% 00:48:08.480 --> 00:48:14.335 align:middle line:90% And in the FSL-- 00:48:14.335 --> 00:48:17.360 align:middle line:84% I think should use a different color-- 00:48:17.360 --> 00:48:18.263 align:middle line:90% in the FSL. 00:48:18.263 --> 00:48:21.740 align:middle line:90% 00:48:21.740 --> 00:48:27.710 align:middle line:84% Req is simply equal to 2 R switch. 00:48:27.710 --> 00:48:30.650 align:middle line:84% Well, that actually kind of feels good in some sense 00:48:30.650 --> 00:48:34.010 align:middle line:84% because if you think about it, in either of these two states, 00:48:34.010 --> 00:48:38.440 align:middle line:84% I'm always dumping current through two switches. 00:48:38.440 --> 00:48:41.930 align:middle line:90% 00:48:41.930 --> 00:48:45.200 align:middle line:84% So half the time I'm doing in this configuration, half 00:48:45.200 --> 00:48:48.290 align:middle line:84% the time in that configuration, but if I think of a capacitor 00:48:48.290 --> 00:48:54.060 align:middle line:84% current as being of a plus and minus square wave of current, 00:48:54.060 --> 00:48:56.640 align:middle line:84% the input current is constant coming here, 00:48:56.640 --> 00:48:57.660 align:middle line:90% and the output current-- 00:48:57.660 --> 00:48:59.970 align:middle line:84% I'm sorry, the input current is a pulse square root. 00:48:59.970 --> 00:49:03.180 align:middle line:84% The output current is kind of constant. 00:49:03.180 --> 00:49:06.168 align:middle line:84% But the point is I'm always putting my charging 00:49:06.168 --> 00:49:08.460 align:middle line:84% and discharging current through two switch resistances, 00:49:08.460 --> 00:49:11.040 align:middle line:84% so it's not maybe surprising that I 00:49:11.040 --> 00:49:13.320 align:middle line:84% get down to this equivalent resistance 00:49:13.320 --> 00:49:16.480 align:middle line:90% being two switch resistances. 00:49:16.480 --> 00:49:20.290 align:middle line:84% So what happens in the real world is if I have a switch 00:49:20.290 --> 00:49:23.080 align:middle line:84% capacitor converter and I say I'm 00:49:23.080 --> 00:49:30.550 align:middle line:84% going to have this model for its behavior, all I'm going to get 00:49:30.550 --> 00:49:37.450 align:middle line:84% is if I plotted R equivalent on a log scale versus switching 00:49:37.450 --> 00:49:41.170 align:middle line:84% frequency on a log scale, what I'm going to get 00:49:41.170 --> 00:49:44.410 align:middle line:84% is something that falls linearly. 00:49:44.410 --> 00:49:49.030 align:middle line:90% This is 1 over 4 c f switch. 00:49:49.030 --> 00:49:54.460 align:middle line:84% And then he's going to have some minimum value, which 00:49:54.460 --> 00:49:55.945 align:middle line:90% is 2 R switch. 00:49:55.945 --> 00:49:58.480 align:middle line:90% 00:49:58.480 --> 00:50:00.700 align:middle line:84% And the actual value you're going to get 00:50:00.700 --> 00:50:04.680 align:middle line:84% is going to do something like this. 00:50:04.680 --> 00:50:07.490 align:middle line:90% 00:50:07.490 --> 00:50:10.940 align:middle line:84% So there's kind of some limiting efficiency you can get to. 00:50:10.940 --> 00:50:13.810 align:middle line:84% Well, if I'm charging through two switches all the time, 00:50:13.810 --> 00:50:16.610 align:middle line:84% I got to eat the on-state loss of those switches. 00:50:16.610 --> 00:50:19.420 align:middle line:84% I mean, I can't have 100% efficiency. 00:50:19.420 --> 00:50:21.670 align:middle line:84% But if I'm using 10 milliohm switches, 00:50:21.670 --> 00:50:22.940 align:middle line:90% maybe that's pretty damn low. 00:50:22.940 --> 00:50:28.210 align:middle line:84% So essentially, what I would tend to do 00:50:28.210 --> 00:50:31.750 align:middle line:84% is keep turning up the switching frequency 00:50:31.750 --> 00:50:34.570 align:middle line:84% until I get down to this regime where turning it up 00:50:34.570 --> 00:50:37.420 align:middle line:84% any more doesn't reduce my output 00:50:37.420 --> 00:50:40.925 align:middle line:84% resistance because, at that point, there are other losses, 00:50:40.925 --> 00:50:42.550 align:middle line:84% like gate drive losses and stuff, which 00:50:42.550 --> 00:50:44.060 align:middle line:90% get worse with frequency. 00:50:44.060 --> 00:50:45.622 align:middle line:84% So I ought to just go high enough 00:50:45.622 --> 00:50:47.330 align:middle line:84% that I can get to very high efficiencies. 00:50:47.330 --> 00:50:49.960 align:middle line:84% And the result of this is if what 00:50:49.960 --> 00:50:54.490 align:middle line:84% I want is a fixed conversion ratio close to this, 00:50:54.490 --> 00:50:59.140 align:middle line:84% I can get extraordinarily high efficiencies in power densities. 00:50:59.140 --> 00:51:02.560 align:middle line:84% If I deviate the voltage conversion ratio away from that, 00:51:02.560 --> 00:51:04.160 align:middle line:84% then the efficiency starts to droop. 00:51:04.160 --> 00:51:06.850 align:middle line:84% But for what they're good at, switch capacitor converters 00:51:06.850 --> 00:51:08.390 align:middle line:90% are very hard to beat. 00:51:08.390 --> 00:51:10.780 align:middle line:84% And if I was to come back and analyze any other switch 00:51:10.780 --> 00:51:12.850 align:middle line:84% capacitor converter, it's the same deal. 00:51:12.850 --> 00:51:14.920 align:middle line:84% It's some charge transfer analysis 00:51:14.920 --> 00:51:16.520 align:middle line:84% through the different capacitors. 00:51:16.520 --> 00:51:19.510 align:middle line:84% And I use charge balance, and you can work that out 00:51:19.510 --> 00:51:24.132 align:middle line:84% to being a current conversion ratio and then some equivalent 00:51:24.132 --> 00:51:26.590 align:middle line:84% resistance with a slow switching limit and a fast switching 00:51:26.590 --> 00:51:27.090 align:middle line:90% limit. 00:51:27.090 --> 00:51:29.410 align:middle line:90% 00:51:29.410 --> 00:51:31.190 align:middle line:84% We'll take this up again next class. 00:51:31.190 --> 00:51:34.400 align:middle line:84% But are there any final questions? 00:51:34.400 --> 00:51:34.937 align:middle line:90% Yeah? 00:51:34.937 --> 00:51:36.770 align:middle line:84% AUDIENCE: Now that you're switching quickly, 00:51:36.770 --> 00:51:40.760 align:middle line:84% can the duty ratio change the conversion ratio? 00:51:40.760 --> 00:51:45.230 align:middle line:84% PROFESSOR: Well, yes, but only through the action 00:51:45.230 --> 00:51:49.130 align:middle line:84% of essentially what this resistance is. 00:51:49.130 --> 00:51:51.410 align:middle line:90% So you can make the-- 00:51:51.410 --> 00:51:53.450 align:middle line:84% for any given converter, there's a duty ratio 00:51:53.450 --> 00:51:55.970 align:middle line:84% that will give you the lowest output resistance. 00:51:55.970 --> 00:51:57.740 align:middle line:84% Even in slow switching limit, you 00:51:57.740 --> 00:52:01.160 align:middle line:84% can change the conversion ratio, but you're doing it 00:52:01.160 --> 00:52:02.520 align:middle line:90% through a resistive drop. 00:52:02.520 --> 00:52:04.970 align:middle line:84% It's sort of like you have an ideal transformer and then 00:52:04.970 --> 00:52:06.510 align:middle line:84% a linear regulator kind of thing. 00:52:06.510 --> 00:52:10.460 align:middle line:84% So you can always use switching frequency and fast 00:52:10.460 --> 00:52:14.630 align:middle line:84% switching limit duty ratio to change the conversion ratio, 00:52:14.630 --> 00:52:17.976 align:middle line:84% but not in a perfectly efficient sense-- 00:52:17.976 --> 00:52:20.282 align:middle line:84% for the voltage conversion ratio. 00:52:20.282 --> 00:52:20.990 align:middle line:90% All right, great. 00:52:20.990 --> 00:52:23.640 align:middle line:90% We'll pick this up next class. 00:52:23.640 --> 00:52:26.000 align:middle line:90%