Course Meeting Times
Lectures: 3 sessions / week, 1 hour / session
Recitations: 1 session / week, 1 hour / session
On completion of 6.111 students will have confidence in their abilities to conceive and carry out a complex digital systems design project in a team of two or three people. More broadly, they will be ready to handle substantial, challenging design problems. In particular, students will be able to:
- explain the elements of digital system abstractions such as digital logic, Boolean algebra, flip-flops, finite-state machines (FSMs), and microprogrammed systems.
- design simple digital systems based on these digital abstractions,and the “digital paradigm” including discrete, sampled information.
- use basic digital tools and devices such as digital oscilloscopes, PALs, PROMs and VHDL.
- work in a design team that can propose, design, successfully implement, and report on a digital circuit design project.
- communicate the purpose and results of a design project in written and oral presentations.
Students will be able to:
- use Boolean Algebra and resulting logic for control and data paths.
- do simple design with basic digital building blocks such as multiplexors, selectors, and shift registers.
- characterize binary signals in terms of: input levels, output levels,and “noise margins”, specifically using the TTL specification.
- Specify digital circuit timing: setup and hold times and logic propagation delays.
- design and implement a simple FSM.
- design, implement and program a simple microprogrammed sequencer.
- use component parts, including complex parts, through their specifications.
- use programmable logic parts for implementation of logical component and system realizations.
- use industry standard CAD software that implements VHDL and can be used to program devices: for example Cypress’ Galaxy and Nova.
- explain communications “handshaking” paradigms.
- evaluate a design concept for appropriateness and achievability.
- organize a design concept into specific parts.
- debug and test an implementation of a digital design.
- give oral and written reports on all aspects of a design project.
One of the following books on VHDL, (or equivalent):
Skahill, Kevin. VHDL for Programmable Logic. Englewood Cliffs, NJ: Prentice Hall, 1996. ISBN: 0201895730.
Pellerin, David, and Taylor, Douglas. VHDL Made Easy. Englewood Cliffs, NJ: Prentice Hall, 1996. ISBN: 0136507638.
Ott, Douglas E. and Thomas J. Wilderotter. A Designer’s Guide to VHDL Synthesis. New York, NY: Springer, 1994. ISBN: 0792394720.
Fletcher, W. I. An Engineering Approach to Digital Design. Englewood Cliffs, NJ: Prentice-Hall, 1980. ISBN: 0132776995.
Mano, M. Morris. Computer Engineering: Hardware Design. Englewood Cliffs, NJ: Prentice-Hall, 1988. ISBN: 0131629263.
The TTL data book is no longer available. Required data and pinouts will be handed out, available on the web page, and available in the laboratory.
All logic diagrams submitted in this subject must be drawn with a template or on a computer, except for quizzes, where all that is required is that logic diagrams be legible. For homework and lab preparation, you may use a drawing template, though it is likely that you will use a computer-based drawing package. Preferred templates: MIL-STD-806C, in 1/2, 3/8 or 3/4 size, Koh-I-Noor No. 830544 or equivalent in Rapid Design or Pickett.
Conduct of the Subject (minor changes may be made)
At the beginning of the term, there are three lectures and one recitation meeting per week. After the second quiz, the lectures and recitations are discontinued. We will meet you frequently in the laboratory.
Five sets will be issued and your solutions will be graded; these are based on the lectures, text and labs.
All laboratory exercises must be completed; these are intended to prepare you for the term project. In doing these exercises, each student works individually.
The most important assignment is the Term Project, about which you will receive more detailed instruction later. In doing this assignment, you will work with one or, at most, two partners. You should begin finding your partner(s) early in the term.
There will be two quizzes during the term, both before Drop Date.
Late work will be penalized. Normally, homework will not be accepted after solutions have been distributed. Lateness of the lab assignments will result in a 20% per day penalty for work completed 1-5 working days after the due date. No point credit will be given for unexcused lateness exceeding 5 days.
The Lab 1 Check off sheet is to be initialed by a TA or LA and included with your report. Note that the check off sheet is NOT the report.
Labs 2 and 3 have intermediate due dates, such as check off, etc. Lateness on these intermediate due dates does NOT result in automatic extensions for later due dates, e.g. the report due date. For example, two days late on Lab 3 check off will result in a penalty of 40% for points assigned to the check off. The report is (still) due at the published due date. There is virtually no modification required to a report depending on the working of your lab implementation. However, reports with no lab effort will receive a zero.
The term project requirements must be completed in accordance with the schedule given in the instructions. You must make a presentation of your part of your project to the rest of the class after the logic diagram conference. You must demonstrate (i.e., present) your term project even if it does not fully function, and you must submit the written report in order to receive a passing grade.
The assignment of letter grades (A,B,C,D,F) is an inherently subjective process. We do, however, make use of numerical data. A single number is computed by weighting graded assignments. The formula used may change slightly from term to term.
The following weights are currently used:
We construct a histogram of these summary numbers and proceed to discuss individual performances of virtually all students. Some of the factors considered are:
- Diligence as measured by completion of most of the problem sets and by presence in the laboratory during final project time.
- Completion of Labs 2 and 3. Past history has been that it is extremely rare for a student to receive an A without completing Lab 3. Of course, it is possible to get a grade lower than an A even if Lab 3 is done.
- Project performance. NaN. Any student who does not turn in a final project report will receive an F. NaN. Students who do not construct a project will receive an F. NaN. Project complexity is an important factor in discriminating between an A and a B. An A is rarely given if the final project is not as complicated as the last Lab.
Although 6.111 has a significant classroom component, it is primarily a lab subject. Accomplishments in the lab tend to be weighted more heavily than other components. The classroom component is viewed as supportive of the lab components.
Traditionally, both average grade levels and average performance have been quite high in 6.111. A large number of students do “A” level work and are, indeed, rewarded with a grade of A. The corollary to this is that, since average performance levels are so high, punting any part of the subject, even the problem sets, can lead to a disappointing grade. It is important that you keep up with the work.
Finally, and unfortunately, it is important for us to outline our expectations for academic honesty in 6.111. We do this not because we expect any of you to be dishonest, nor to insult your intelligence or character, but to avoid any misunderstandings.
First, the quizzes are to be individual efforts. The problem sets and lab exercises are also to be individual efforts; however, it is okay to ask questions, get help from us, fellow students, or anyone else. But then, do them by yourself. Indications of collaboration such as incidents of identical code or copied figures are unacceptable and are liable to be dealt with in a seemingly harsh fashion. Do not “dry lab” the design part of the laboratory work. The TA’s will be asking you about your solutions to make sure you really do understand what you have done.
The Final Project is a different story. We do expect you to collaborate with the course staff and with your fellow students, especially with your lab partner. Joint or individual reports are acceptable, but in the case of joint reports it is important that responsibility for each section of the work be indicated.
Read the General Laboratory Information handout.
The schedule of the lectures and assignments is posted on the course website. Staying on schedule is very important in this subject, in order to be prepared to do the term project, which is the single most important assignment in 6.111. It will be an enjoyable experience if you are properly prepared.
Extra Units for 6.111
Many 6.111 students spend more hours per week than warranted by the 12 unit rating. Primarily this is due to large final projects. It is now possible to register for 6.905 and gain an additional 6 units of credit for 6.111. Your grade for 6.905 will be the same as your grade for 6.111. Your grade for 6.111 is not influenced by registration for 6.905.
Our motivation for enabling the availability of these extra units is two-fold. Foremost is our desire to convince 6.111 students that they need not do a project which is bigger and more complicated than ever done in the past. Secondly, recognizing that many students will continue to do ambitious projects, we would like to credit 6.111 students with units appropriate to work expended.
Procedures for registering for the extra units by DROP date will be announced later on in the term.Both the determination of grades and the project time requirements are inherently subjective. The last Lab provides some guidance to the evaluation of project size and complexity. Lab 3 can require almost a full kit’s worth of components. A reasonable guideline as to size of 6.111 projects is that it not require more than a kit and a proto board per person.
6.111 student projects often become too large because of a desire to effect computations in parallel and at high speed. Data paths are often unnecessarily wide and redundant. It is generally far better to minimize the type and extent of the data paths even though this results in more complicated control circuitry.
Use of microprogrammed sequencers and FSMs implemented with PALs and CPLD’s allows implementation of complicated control with a small number of ICs. Please remember that massive data paths that enable computation at speeds far faster than needed do not represent a good design! It is almost always better to spend more time thinking and less time wiring.