6.776 | Spring 2005 | Graduate

High Speed Communication Circuits


Lab Information Sheet


The lab space has oscilloscopes, multimeters, and 5 V power supplies (on breadboard boxes) at each station. There are also soldering irons, several curve tracers, and an LCR impedance analyzer in the room. We only have available one high frequency signal generator. This signal generator is on one of the desks and must be time-shared among groups. There is a parts cabinet located on the other side of the lab that contains general components such as resistors and capacitors.


Three different components needed for this lab were handed out in class.

  1. ON Semiconductor J310 JFET
  2. Sprague-Goodman GCL 20000 Variable Capacitor (0.8 pF - 20 pF)
  3. Toko 294SN-T1013Z Tunable Inductor - Nominal value of 0.47 µH

We have ordered additional transistors and variable capacitors, in addition to various fixed inductors (0.047 µH, 0.1 µH, 0.33 µH, 0.56 µH). We also have 1 µH tunable inductors. These parts will be made available in the lab. One other note is that the tunable inductors have limited tuning range. We advise you to use the tunable inductors as fixed inductors, and rely on the variable capacitors to tune your amplifier.


J310 Spice Model (SCS)

The J310 Spice model above is compatible with Spectre. This model may or may not be accurate as there are many different manufacturers of J310 transistors and there may be considerable variability in the transistor operating characteristics from lot to lot as well as part to part. I have tweaked the value of the threshold voltage, VTO, in the model based on DC measurements performed on one of the transistors. You are encouraged to verify and modify the model, as needed, by comparing simulation results to measured DC characteristics of your specific device. For example, the model currently does not model output conductance. You will want to either measure gds, or find its value from the datasheets at your operating point. Transconductance is another important DC device characteristic you should verify.

In order to use the model, copy the model file, jfet.scs, to your MIT server account. Then,

  1. Open a schematic.
  2. Open the Affirma Analog Design Environment window by clicking Tools -> _Analog Environment.
  3. Click Setup -> Model Libraries
  4. Under Model Library File, type in the name of the model file and click Add. For example, if you placed the model file in your home directory, you would type ~/jfet.scs.
  5. In your schematic view, add the symbol component, njfet, that can be found in analogLib.
  6. Edit the properties of your instance and under Model name, type jmod. This is the model name used in the model file.
  7. Make sure any scaling factors in the parameter list for njfet are set to 1.

You should then be able to run simulations based on the J310 Spice model.

Noise Simulation

In this lab project, you will be required to simulate the noise figure of your amplifier. I will list the basic steps necessary to simulate noise figure using Spectre.

  1. In the Affirma Analog Design Environment window, click Analysis -> Choose -> _noise.
  2. Under Sweep Variable, click _Frequency.
  3. Under Sweep Range, click Start-Stop and type in an appropriate frequency range.
  4. Choose a desired Sweep Type and type in either a number of points or a step size.
  5. Under Output Noise, select voltage and then select your output node as the Positive Output Node and the circuit gnd as your _Negative Output Node.
  6. Under Input Noise, you can either select an Input Voltage Source or an Input Port Source. In either case, click on the input source you are using on the schematic. This input source should have a source resistance of 50 ohms (either embedded in the source if it’s a port, or placed external to the source in series, if it’s a voltage source).
  7. Click OK.
  8. Run the simulation.
  9. Click on Results -> Direct Plot. From here, you can plot Equivalent Output Noise, Equivalent Input Noise, Squared Output Noise, Squared Input Noise, or Noise Figure. For Noise Figure, select the input node (the top of the input voltage source), the output node, and specify the source resistance as 50 ohms. You will then get a plot of noise figure vs. frequency. If you used a port, the noise figure will be plotted automatically.
  10. You can also do some analysis by clicking Results -> Print -> _Noise Summary.
  11. Specify spot noise, Frequency Spot = 50 MHz, flat weighting, and include All Types. You can then list the noise contributors individually to see what circuit elements are degrading your noise figure. You can also verify noise figure by taking the total output noise and dividing by the output noise contribution due to the source resistance.

Final Comments

Keep in mind that we are using JFETs, not MOSFETs. They are similar except their threshold voltage is negative. The device will draw plenty of current with Vgs = 0. Put some thought into how you want to bias your devices.

As we mentioned in class, we encourage you to use lab equipment and parts available to you through your research labs. Most noticeably, we do not have a network analyzer there, which makes it difficult to measure your input match.

Please do your best to clean up after yourselves in the lab. We are using lab space and equipment reserved for other classes so let’s not abuse our privileges.

Good luck and have fun!

Course Info

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