This section provides a list of recommended readings for those interested in communication system design.
Papers
Meng, T. H., B. McFarland, D. Su, and J. Thomson. “Design and Implementation of an All-CMOS 802.11a Wireless LAN Chipset.” Communications Magazine, IEEE 41, no. 8 (2003): 160-168.
Thomson, J., et al. “An Integrated 802.11a Baseband and MAC Processor.” Solid-State Circuits Conference, Digest of Technical Papers. ISSCC, IEEE International (2002): 92-415.
Grass, E., et al. “On the Single-Chip Implementation of a Hiperlan/2 and IEEE 802.11a Capable Modem.” Personal Communications, IEEE 8, no. 6 (2001): 48-57. (See also IEEE Wireless Communications.)
Krstic, M., K. Maharatna, A. Troya, E. Grass, and U. Jagdhold. “Implementation of An IEEE 802.11a Compliant Low-Power Baseband Processor.” Telecommunications in Modern Satellite, Cable and Broadcasting Service. TELSIKS 6th International Conference (2003): 97-100.
Weste, N., and D. J. Skellern. “VLSI for OFDM.” Communications Magazine, IEEE 36, no. 10 (1998): 127-131.
802.11a IEEE standard
Duhamel, P., and M. Vetterli. “Fast Fourier Transforms: A Tutorial Review and a State of The Art.” Signal Processing 19, no. 4 (1990): 259-299.
Heideman, M., D. Johnson, and C. Burrus. “Gauss and The History of The Fast Fourier Transform.” ASSP Magazine, IEEE 1, no. 4 (1984): 14-21. (See also IEEE Signal Processing Magazine.)
Cooley, J., and J. Tukey. “An Algorithm For The Machine Calculation of Complex Fourier Series.” Mathematics of Computation 19 (1965): 297-301.
Thompson, C. D. “Fourier Transforms in VLSI.” no. UCB/CSD-82-105 (1982). (Thompson, C. D. “Fourier Transforms in VLSI,” IEEE Trans. Computers 32, no. 11 (1983): 1047-1057.)
Shousheng, H. E., and M. Torkelson. “A New Approach To Pipeline FFT Processor.” The 10th International Parallel Processing Symposium (1996): 766-770.
———. “Designing Pipeline FFT Processor for OFDM (de)Modulation.” International Symposium on Signals, Systems, and Electronics (1998): 257-262.
Maharatna, K., E. Grass, and U. Jagdhold. “A 64-point Fourier Transform Chip for High-Speed Wireless LAN Application Using OFDM.” IEEE Journal of Solid-State Circuits 39, no. 3 (2004): 484-493.
Chiu, C., W. Hui, T. J. Ding, and J. V. McCanny. “A 64-point Fourier Transform Chip For Video Motion Compensation Using Phase Correlation.” IEEE Journal of Solid-State Circuits 31, no. 11 (1996): 1751-1761.
Sadat, A., and W. B. Mikhael. “Fast Fourier Transform for High Speed OFDM Wireless Multimedia System.” Midwest Symposium on Circuits and Systems 2 (2001): 938-942.
Pagiamtzis, K., and P. G. Gulak. “Empirical Performance Prediction For IFFT/FFT Cores For OFDM Systems-On-a-Chip.” Midwest Symposium on Circuits and Systems 1 (2002): I-583-586.
Hong, S., S. Kim, M. C. Papaefthymiou, and W. E. Stark. “Power-Complexity Analysis of Pipelined VLSI FFT Architectures For Low Energy Wireless Communication Applications.” Midwest Symposium on Circuits and Systems 1 (1999): 313-316.
Forney, G., Jr. “Convolutional Codes I: Algebraic Structure.” IEEE Transactions on Information Theory 16, no. 6 (1970): 720-738.
Viterbi, A. “Convolutional Codes and Their Performance in Communication Systems.” IEEE Transactions on Communications 19, no. 5 (1971): 751-772.
Ungerboeck, G. “Channel Coding with Multilevel/Phase Signals.” IEEE Transactions on Information Theory 28, no. 1 (1982): 55-67.
———. “Trellis-Coded Modulation with Redundant Signal Sets Part II: State of the Art.” IEEE Communications Magazine 25, no. 2 (1987): 12-21.
———. “Trellis-Coded Modulation with Redundant Signal Sets Part I: Introduction.” IEEE Communications Magazine 25, no. 2 (1987): 5-11.
Viterbi, A. “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm.” IEEE Transactions on Information Theory 13, no. 2 (1967): 260-269.
Forney, G., Jr. “The Viterbi Algorithm.” Proceedings of the IEEE 61, no. 3 (1973): 268-278.
———. “Maximum-Likelihood Sequence Estimation of Digital Sequences in the Presence of Intersymbol Interference.” IEEE Transactions on Information Theory 18, no. 3 (1972): 363-378.
Fettweis, G., and H. Meyr. “High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture.” Communications Magazine, IEEE 29, no. 5 (1991): 46-55.
Black, P. J., and T. H. Meng. “A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder.” Solid-State Circuits, IEEE Journal 27, no. 12 (1992): 1877-1885.
———. “A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder.” Solid-State Circuits, IEEE Journal 32, no. 6 (1997): 797-805.
Anders, M., S. Mathew, R. Krishnamurthy, and S. Borkar. “A 64-State 2GHz 500Mbps 40mW Viterbi Accelerator in 90nm CMOS.” Symposium on VLSI Circuits, Digest of Technical Papers (2004): 174-175.
Hekstra, A. P. “An Alternative To Metric Rescaling in Viterbi Decoders.” IEEE Transactions on__Communications 37, no. 11 (1989): 1220-1222.
Rader, C. “Memory Management in a Viterbi Decoder.” IEEE Transactions on Communications 29, no. 9 (1981): 1399-1401.
Cypher, R., and C. B. Shung. “Generalized Trace Back Techniques for Survivor Memory Management in the Viterbi Algorithm.” Global Telecommunications Conference and Exhibition. ‘Communications: Connecting the Future’, GLOBECOM ‘90. IEEE 2 (1990): 1318-1322.
Feygin, G., and P. G. Gulak. “Survivor Sequence Memory Management in Viterbi Decoders.” IEEE International Symposium on Circuits and Systems 5 (1991): 2967-2970.
Books
Augustsson, Lennart, Jacob Schwartz, and Rishiyur Nikhil. Bluespec™ Language Definition. Sandburst Corporation, December 2002.
Course readings were also taken from chapters of the Digital Communication: Signal Processing course reader written by John Cioffi at Stanford University.
Chapter 1 - Fundamentals of discrete data transmission (PDF - 2.4 MB)
Chapter 2 - Passband systems and analysis (PDF)
Chapter 3 - Equalization (PDF - 5.5 MB)
Chapter 4 - Multi-channel modulation
Chapter 6 - Fundamentals of synchronization (PDF - 1.0 MB)
Chapter 8 - Fundamental limits of coding and sequences
Chapter 9 - Sequence detection
Chapter 10 - System design with codes
