Computer System Architecture

Readings

The table below provides information on the required and optional readings for the course. Optional readings were provided for interested students to explore topics further and deepen their understanding of the course material.

Legend

Session Number

L: lecture
T: tutorial
Q: quiz

Topics

(A): Session taught by Professor Arvind
(J): Session taught by Dr. Joel Emer

Required Readings

H&P3: Hennessy, J. L., and D. A. Patterson. Computer Architecture: A Quantitative Approach, 3rd ed. San Mateo, CA: Morgan Kaufman, 2002. ISBN: 1558605967.

H&P2: Hennessy, J. L., and D. A. Patterson. Computer Architecture: A Quantitative Approach, 2nd ed. San Mateo, CA: Morgan Kaufman, 1995. ISBN: 1558603727.

P&H: Patterson, D. A., and J. L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 3rd ed. San Mateo, CA: Morgan Kaufman, 2004. ISBN: 1558606041.

SES #	TOPICS	REQUIRED READINGS	OPTIONAL READINGS
L1	History of Calculation and Computer Architecture (A)	H&P3, chapter 1, pp. 67-72. H&P2, chapter 1, pp. 53-60.	Burks, Arthur W., Herman H. Goldstine, and John von Neumann. Preliminary Discussion of the Logical Design of an Electronic Computing Instrument. Report to the U.S. Army Ordinance Department, 1946. Reprinted as: Bell and Newell. Computer Structures: Readings and Examples, chapter 4. New York, NY: McGraw-Hill, 1971. ISBN: 0070043574. Babbage, Charles, and Others. Charles Babbage and His Calculating Engines: Selected Writings. Edited by Philip and Emily Morrison. New York, NY: Dover, 1961. ISBN: 0486200124.
L2	Influence of Technology and Software on Instruction Sets: Up to the Dawn of IBM 360 (A)	H&P3, rest of chapter 1. H&P2, rest of chapter 1.	Amdahl, G. M., G. A. Blaauw, and F. P. Brooks, Jr. “Architecture of the IBM System/360.” IBM Journal of Research and Development, April 1964. Reprinted in: IBM Journal of Research and Development 44, no. 1/2 (2000).
L3	Complex Instruction Set Evolution in the Sixties: Stack and GPR Architectures (A)	H&P3, chapter 2, pp. 90-129. H&P2, chapter 2, pp. 69-96.
T1	Self-assessment Test and ISA
L4	Microprogramming (A)	H&P3, chapter 2, pp. 129-158. H&P2, chapter 2, pp. 96-116.
T2	MIPS ISA, Bus-based Implementation, and Microprogramming
L5	Simple Instruction Pipelining (A)	H&P3, appendix A, pp. 2-11 (Background: P&H, chapter 6). H&P2, chapter 3, pp. 125-160 (Background: P&H, chapter 6).
L6	Pipeline Hazards (A)	H&P3, appendix A, pp. 11-37. H&P2, chapter 3, pp. 161-178.
T3	Microprogramming, Pipelining, and Hazards
L7	Multilevel Memories - Technology (J)	H&P3, chapter 5, pp. 390-413. H&P2, chapter 5, pp. 373-390.
L8	Cache (Memory) Performance Optimization (J)	H&P3, chapter 5, pp. 413-460 and 478-489. H&P2, chapter 5, pp. 390-439 and 457-474.	Jouppi, Norm. “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers.” In The Proceedings of 17th International Symposium on Computer Architecture (ISCA) Seattle, Washington, May 1990, pp. 364-373.
Q1	ISAs, Microprogramming, Simple Pipelining and Hazards
L9	Virtual Memory Basics (J)	H&P3, chapter 5, pp. 460-478. H&P2, chapter 5, pp. 439-457.
T4	Quiz 1, Caches, and Virtual Memory Basics
L10	Virtual Memory: Part Deux (A)	H&P3, appendix A, pp. 37-47. H&P2, chapter 3, pp. 187-214.
L11	Complex Pipelining (A)	H&P3, appendix A, pp. 37-78. H&P2, chapter 3, pp. 187-214.
Q2	Caches, Virtual Memory
L12	Out of Order Execution and Register Renaming (A)	H&P3, chapter 3, pp. 172-196. H&P2, chapter 4, pp. 221-261.
L13	Branch Prediction and Speculative Execution (A)	H&P3, chapter 3, pp. 196-259. H&P2, chapter 4, pp. 262-289 and 317-335.
T5	Quiz 2, Scoreboarding, Register Renaming, and Branch Prediction
L14	Advanced Superscalar Architectures (J)
L15	Microprocessor Evolution: 4004 to Pentium 4 (J)	H&P3, chapter 3, pp. 259-283. H&P2, chapter 4, pp. 335-359.
Q3	Complex Pipelines
L16	Synchronization and Sequential Consistency (A)	H&P3, chapter 6, pp. 549. H&P3, appendix I. H&P2, chapter 8, pp. 694-713.
L17	Cache Coherence (A)	H&P3, chapter 6, pp. 549-590. H&P3, appendix I. H&P2, chapter 8, pp. 654-693. H&P2, appendix E.
L18	Cache Coherence (Implementation) (A)	H&P3, chapter 6, pp. 549-590. H&P3, appendix I. H&P2, chapter 8, pp. 654-693. H&P2, appendix E.
L19	Snoopy Protocols (A)
T6	Sequential Consistency, Synchronization, Cache Coherence Protocols
L20	Relaxed Memory Models (A)	H&P3, chapter 6, pp. 607-608 and 618-619. H&P2, chapter 8, pp. 714-720.	Adve, S., and K. Gharachorloo. “Shared memory consistency models: a tutorial.” In Technical Report WRL-TR 95/7, Digital Western Research Laboratory, September 1995.
Q4	SMPs, CC, Synch, Memory Models
L21	VLIW/EPIC: statically Scheduled ILP (J)	H&P3, chapter 4, pp. 304-362. H&P2, Chapter 4, pp. 223-240 and 284-317.
L22	Vector Computers (J)	H&P3, appendix G. H&P3, appendix B.
T7	Quiz 4 and VLIW
L23	Multithreaded Processors (J)	H&P3, chapter 3, pp.272-273. H&P3, chapter 6, pp. 608-615 and 635-636.	Tullsen, D., S. Eggers, and H. Levy. “Simultaneous Multithreading: Maximizing On-Chip Parallelism.” In The Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995. Tullsen, D., S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm, “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.” In The Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996.
L24	Reliable Architectures (J)		Reinhardt, S. K., and S. S. Mukherjee. “Transient Fault Detection via Simultaneous Multithreading.” In The Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000. Biswas, R., R. Cheveresan, J. Emer, S. Mukherjee, P. Racunas, and R. Rangan. “Computing Architectural Vulnerability Factors for Address-Based Structures.” In The Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005.
T8	Vector Computers, Multithreading and Reliable Architectures
L25	Virtual Machines (J)	H&P3, pp. 367-370.
Q5	VLIW/Vector/Threads