Tools
Lab #6
Description:
Supporting file for a lab assignment on RISC processor design. This code makes the following assumptions about the Beta design: after reset, the Beta starts executing at location 0; illegal instructions cause a trap to location 4; interrupts cause a trap to location 8.
Resource Type:
Tools
file
11 kB
Lab #6
Course Info
Instructor
Departments
As Taught In
Spring
2009
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Learning Resource Types
assignment_turned_in
Problem Sets with Solutions
grading
Exams with Solutions
notes
Lecture Notes
