Introductory Digital Systems Laboratory

Calendar

All lectures (not quizzes) have lecture notes in addition to the handouts listed below.

Day #	LEC #	Handouts	Due	Lecture Topics
1	1	First Day Packet includes: General Information Syllabus General Laboratory Information Computer Information Introduction to HP Logic Analyzer Beginner’s Guide to WARP PAL Programming Problem Set 1 Lab 1 Safety Memo Kit Sign-out Form Background Information and Schedule Form	6.111 Sign-up Sheet	Introduction, Basic Boolean
2	2	Gates, Symbols, and Busses Kmap		Example, Kmaps
3	3			Gates, Flip Flops, Building Blocks, Counters
4	4	Negative True and VHDL, PS 1 Solutions, PS 2	PS 1	Counters, Finite State, Machines, PALS
5	5			VHDL Intro; Entities, Galaxy demo
6	6		Lab 1	VHDL Statements
7	7	Lab 2 (CPLD and 6264 data sheets), PS 3, PS 2 Solutions	PS 2	VHDL FSM Example,Timing, Lab 2 assignment
8	8			Design Procedure,VHDL Packages, Memories
9	9	Report Guide, Phase II form Checklist, Writing, Style guide		Writing Phase II, Quiz 1 Review
10	Q1	QUIZ 1		QUIZ 1 (56-154, -169, -191)
11	10	PS 3 Solutions, PS 4	PS 3	VHDL Identifiers, Handshaking, Package examples
12	11	PS 5, FPGA Module	Lab 2, Design Check-off	VHDL Statements, ALU example
13	12	PS 4 Solutions	PS 4	Binary Arithmetic, Control Example (PI controller)
14	13	Lab 3	Lab 2, Check-off	Implementation using multiple FSM’s, FLEX10K parts
15	14			Lab 3 Assignment (demo)
16	15	PS 5 solutions	L2 Report, PS 5 due in the lab	A/D, D/A, Op Amps (demo)
17	16	Project Information		Project Kickoff
18	17		Project Abstracts, Lab 3 Design	Video 1
19	18	MC6847 data sheet		Video 2, Transmission Lines (demo)
20	19	How to Make Your Project Work		Encoders, Motors, Quiz 2 Review
21	Q2	Quiz 2	Proposal Conferences
22			Lab 3 Check-off
23			Design Conferences
25			Lab 3 Report
26			Project Design Presentations
27			Project Design Presentations
28			Project Design Presentations
29			Project Design Presentations
30			Project Presentations
31			Video-taping the Project Demonstrations
32			Project Reports due