6-884S05-th.jpg
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6-884S05-th.jpg
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NAND gate diagram.
Caption:
NAND gate layout from Lecture 3: CMOS Technology and Logic Gates. (Image by Professors Arvind and Asanovic.)
Course Info
Instructors
Departments
As Taught In
Spring
2005
Level
Course Info
Instructors
Departments
As Taught In
Spring
2005
Level
Learning Resource Types
notes
Lecture Notes