Computation Structures | Electrical Engineering and Computer Science | MIT OpenCourseWare

Laboratory Assignments

Ant

BETA Macro package

BSim

BSim

Design Project

JSim

JSim

Nominal Device Models

Project Checkoff

Project Checkoff

Project Checkoff

Summary of β Instruction Formats

Syntax table for use in JSim-mode buffers

TMSim

Unpipelined Beta

β Documentation

Lab #1

Lab #1: Checkoff

Lab #2

Lab #2: Checkoff

Lab #3

Lab #3: Adder

Lab #3: Boolean

Lab #3: Checkoff 10

Lab #3: Checkoff 6

Lab #3: compare

Lab #3: Multiply

Lab #3: Shifter

Lab #4

Lab #4: Header

5-stage Pipelined Beta

Lab #5

Lab #5: Checkoff

6.004 standard cell library

Lab #6

Lab #6

Lab #6: Basic Block

Lab #6: Basic Block

Lab #6: Checkoff

Lab #6: Control

Lab #6: PC

Lab #6: Reg File

Lab #7

Lab #7: Checkoff

Lab #7: Macros

Lab #7: Swap Regs

8 clocks

Lab #8

Lab #8 Checkoff

Lab #8: Simple OS demo for 6.004 Beta processor

6004

Course Info

Instructor

Prof. Steve Ward

Departments

Electrical Engineering and Computer Science

As Taught In

Spring 2009

Level

Undergraduate

Course Info

Instructor

Prof. Steve Ward

Departments

Electrical Engineering and Computer Science

As Taught In

Spring 2009

Level

Undergraduate

Topics

Topics

Learning Resource Types

Exam Solutions

Exams

Lecture Notes

Problem Set Solutions

Problem Sets

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